2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
16 #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
17 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
19 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
20 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
21 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
22 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
24 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
27 u32 control; /* Control Register [8:0] */
28 u32 mode; /* Mode Register [10:0] */
30 u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
32 u32 channel_sts; /* Channel Status [11:0] */
33 u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
34 u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
37 static struct uart_zynq *uart_zynq_ports[2] = {
38 [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
39 [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
42 #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
43 # define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
45 #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
46 # define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
49 struct uart_zynq_params {
53 static struct uart_zynq_params uart_zynq_ports_param[2] = {
54 [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
55 [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
58 /* Set up the baud rate in gd struct */
59 static void uart_zynq_serial_setbrg(const int port)
61 /* Calculation results. */
62 unsigned int calc_bauderror, bdiv, bgen;
63 unsigned long calc_baud = 0;
64 unsigned long baud = uart_zynq_ports_param[port].baudrate;
65 unsigned long clock = get_uart_clk(port);
66 struct uart_zynq *regs = uart_zynq_ports[port];
69 * Baud rate = ------------------
72 * Find acceptable values for baud generation.
74 for (bdiv = 4; bdiv < 255; bdiv++) {
75 bgen = clock / (baud * (bdiv + 1));
76 if (bgen < 2 || bgen > 65535)
79 calc_baud = clock / (bgen * (bdiv + 1));
82 * Use first calculated baudrate with
83 * an acceptable (<3%) error
86 calc_bauderror = baud - calc_baud;
88 calc_bauderror = calc_baud - baud;
89 if (((calc_bauderror * 100) / baud) < 3)
93 writel(bdiv, ®s->baud_rate_divider);
94 writel(bgen, ®s->baud_rate_gen);
97 /* Initialize the UART, with...some settings. */
98 static int uart_zynq_serial_init(const int port)
100 struct uart_zynq *regs = uart_zynq_ports[port];
105 /* RX/TX enabled & reset */
106 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
107 ZYNQ_UART_CR_RXRST, ®s->control);
108 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
109 uart_zynq_serial_setbrg(port);
114 static void uart_zynq_serial_putc(const char c, const int port)
116 struct uart_zynq *regs = uart_zynq_ports[port];
118 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
122 writel('\r', ®s->tx_rx_fifo);
123 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
126 writel(c, ®s->tx_rx_fifo);
129 static void uart_zynq_serial_puts(const char *s, const int port)
132 uart_zynq_serial_putc(*s++, port);
135 static int uart_zynq_serial_tstc(const int port)
137 struct uart_zynq *regs = uart_zynq_ports[port];
139 return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
142 static int uart_zynq_serial_getc(const int port)
144 struct uart_zynq *regs = uart_zynq_ports[port];
146 while (!uart_zynq_serial_tstc(port))
148 return readl(®s->tx_rx_fifo);
151 /* Multi serial device functions */
152 #define DECLARE_PSSERIAL_FUNCTIONS(port) \
153 int uart_zynq##port##_init(void) \
154 { return uart_zynq_serial_init(port); } \
155 void uart_zynq##port##_setbrg(void) \
156 { return uart_zynq_serial_setbrg(port); } \
157 int uart_zynq##port##_getc(void) \
158 { return uart_zynq_serial_getc(port); } \
159 int uart_zynq##port##_tstc(void) \
160 { return uart_zynq_serial_tstc(port); } \
161 void uart_zynq##port##_putc(const char c) \
162 { uart_zynq_serial_putc(c, port); } \
163 void uart_zynq##port##_puts(const char *s) \
164 { uart_zynq_serial_puts(s, port); }
166 /* Serial device descriptor */
167 #define INIT_PSSERIAL_STRUCTURE(port, __name) { \
169 .start = uart_zynq##port##_init, \
171 .setbrg = uart_zynq##port##_setbrg, \
172 .getc = uart_zynq##port##_getc, \
173 .tstc = uart_zynq##port##_tstc, \
174 .putc = uart_zynq##port##_putc, \
175 .puts = uart_zynq##port##_puts, \
178 DECLARE_PSSERIAL_FUNCTIONS(0);
179 struct serial_device uart_zynq_serial0_device =
180 INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
181 DECLARE_PSSERIAL_FUNCTIONS(1);
182 struct serial_device uart_zynq_serial1_device =
183 INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
185 __weak struct serial_device *default_serial_console(void)
187 #if defined(CONFIG_ZYNQ_SERIAL_UART0)
188 if (uart_zynq_ports[0])
189 return &uart_zynq_serial0_device;
191 #if defined(CONFIG_ZYNQ_SERIAL_UART1)
192 if (uart_zynq_ports[1])
193 return &uart_zynq_serial1_device;
198 void zynq_serial_initalize(void)
200 serial_register(&uart_zynq_serial0_device);
201 serial_register(&uart_zynq_serial1_device);