2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
59 struct uart_port port;
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
78 struct timer_list break_timer;
81 #ifdef CONFIG_HAVE_CLK
87 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
88 static struct sci_port *serial_console_port;
91 /* Function prototypes */
92 static void sci_stop_tx(struct uart_port *port);
94 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
96 static struct sci_port sci_ports[SCI_NPORTS];
97 static struct uart_driver sci_uart_driver;
99 static inline struct sci_port *
100 to_sci_port(struct uart_port *uart)
102 return container_of(uart, struct sci_port, port);
105 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
106 static inline void handle_error(struct uart_port *port)
108 /* Clear error flags */
109 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
112 static int sci_poll_get_char(struct uart_port *port)
114 unsigned short status;
118 status = sci_in(port, SCxSR);
119 if (status & SCxSR_ERRORS(port)) {
123 } while (!(status & SCxSR_RDxF(port)));
125 c = sci_in(port, SCxRDR);
129 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
134 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
136 unsigned short status;
139 status = sci_in(port, SCxSR);
140 } while (!(status & SCxSR_TDxE(port)));
142 sci_in(port, SCxSR); /* Dummy read */
143 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
144 sci_out(port, SCxTDR, c);
146 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
148 #if defined(__H8300S__)
149 enum { sci_disable, sci_enable };
151 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
153 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
154 int ch = (port->mapbase - SMR0) >> 3;
155 unsigned char mask = 1 << (ch+1);
157 if (ctrl == sci_disable)
163 static inline void h8300_sci_enable(struct uart_port *port)
165 h8300_sci_config(port, sci_enable);
168 static inline void h8300_sci_disable(struct uart_port *port)
170 h8300_sci_config(port, sci_disable);
174 #if defined(__H8300H__) || defined(__H8300S__)
175 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
177 int ch = (port->mapbase - SMR0) >> 3;
180 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
181 h8300_sci_pins[ch].rx,
183 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
184 h8300_sci_pins[ch].tx,
188 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
191 #define sci_init_pins_sci NULL
194 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
195 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
197 unsigned int fcr_val = 0;
200 fcr_val |= SCFCR_MCE;
202 sci_out(port, SCFCR, fcr_val);
205 #define sci_init_pins_irda NULL
208 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
209 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
211 unsigned int fcr_val = 0;
213 set_sh771x_scif_pfc(port);
215 fcr_val |= SCFCR_MCE;
216 sci_out(port, SCFCR, fcr_val);
218 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
219 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
221 unsigned int fcr_val = 0;
224 if (cflag & CRTSCTS) {
226 if (port->mapbase == 0xa4430000) { /* SCIF0 */
227 /* Clear PTCR bit 9-2; enable all scif pins but sck */
228 data = ctrl_inw(PORT_PTCR);
229 ctrl_outw((data & 0xfc03), PORT_PTCR);
230 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
231 /* Clear PVCR bit 9-2 */
232 data = ctrl_inw(PORT_PVCR);
233 ctrl_outw((data & 0xfc03), PORT_PVCR);
235 fcr_val |= SCFCR_MCE;
237 if (port->mapbase == 0xa4430000) { /* SCIF0 */
238 /* Clear PTCR bit 5-2; enable only tx and rx */
239 data = ctrl_inw(PORT_PTCR);
240 ctrl_outw((data & 0xffc3), PORT_PTCR);
241 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
242 /* Clear PVCR bit 5-2 */
243 data = ctrl_inw(PORT_PVCR);
244 ctrl_outw((data & 0xffc3), PORT_PVCR);
247 sci_out(port, SCFCR, fcr_val);
249 #elif defined(CONFIG_CPU_SH3)
250 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
251 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
253 unsigned int fcr_val = 0;
256 /* We need to set SCPCR to enable RTS/CTS */
257 data = ctrl_inw(SCPCR);
258 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
259 ctrl_outw(data & 0x0fcf, SCPCR);
262 fcr_val |= SCFCR_MCE;
264 /* We need to set SCPCR to enable RTS/CTS */
265 data = ctrl_inw(SCPCR);
266 /* Clear out SCP7MD1,0, SCP4MD1,0,
267 Set SCP6MD1,0 = {01} (output) */
268 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
270 data = ctrl_inb(SCPDR);
271 /* Set /RTS2 (bit6) = 0 */
272 ctrl_outb(data & 0xbf, SCPDR);
275 sci_out(port, SCFCR, fcr_val);
277 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
278 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
280 unsigned int fcr_val = 0;
283 if (port->mapbase == 0xffe00000) {
284 data = ctrl_inw(PSCR);
287 fcr_val |= SCFCR_MCE;
291 ctrl_outw(data, PSCR);
293 /* SCIF1 and SCIF2 should be setup by board code */
295 sci_out(port, SCFCR, fcr_val);
297 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
298 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
300 /* Nothing to do here.. */
301 sci_out(port, SCFCR, 0);
305 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307 unsigned int fcr_val = 0;
309 if (cflag & CRTSCTS) {
310 fcr_val |= SCFCR_MCE;
312 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
314 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
315 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
316 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
317 defined(CONFIG_CPU_SUBTYPE_SHX3)
318 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
320 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
323 sci_out(port, SCFCR, fcr_val);
327 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
328 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
329 defined(CONFIG_CPU_SUBTYPE_SH7785)
330 static inline int scif_txroom(struct uart_port *port)
332 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
335 static inline int scif_rxroom(struct uart_port *port)
337 return sci_in(port, SCRFDR) & 0xff;
339 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
340 static inline int scif_txroom(struct uart_port *port)
342 if ((port->mapbase == 0xffe00000) ||
343 (port->mapbase == 0xffe08000)) {
345 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
348 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
352 static inline int scif_rxroom(struct uart_port *port)
354 if ((port->mapbase == 0xffe00000) ||
355 (port->mapbase == 0xffe08000)) {
357 return sci_in(port, SCRFDR) & 0xff;
360 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
364 static inline int scif_txroom(struct uart_port *port)
366 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
369 static inline int scif_rxroom(struct uart_port *port)
371 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
375 static inline int sci_txroom(struct uart_port *port)
377 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
380 static inline int sci_rxroom(struct uart_port *port)
382 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
385 /* ********************************************************************** *
386 * the interrupt related routines *
387 * ********************************************************************** */
389 static void sci_transmit_chars(struct uart_port *port)
391 struct circ_buf *xmit = &port->info->xmit;
392 unsigned int stopped = uart_tx_stopped(port);
393 unsigned short status;
397 status = sci_in(port, SCxSR);
398 if (!(status & SCxSR_TDxE(port))) {
399 ctrl = sci_in(port, SCSCR);
400 if (uart_circ_empty(xmit))
401 ctrl &= ~SCI_CTRL_FLAGS_TIE;
403 ctrl |= SCI_CTRL_FLAGS_TIE;
404 sci_out(port, SCSCR, ctrl);
408 if (port->type == PORT_SCI)
409 count = sci_txroom(port);
411 count = scif_txroom(port);
419 } else if (!uart_circ_empty(xmit) && !stopped) {
420 c = xmit->buf[xmit->tail];
421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
426 sci_out(port, SCxTDR, c);
429 } while (--count > 0);
431 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
433 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
434 uart_write_wakeup(port);
435 if (uart_circ_empty(xmit)) {
438 ctrl = sci_in(port, SCSCR);
440 if (port->type != PORT_SCI) {
441 sci_in(port, SCxSR); /* Dummy read */
442 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
445 ctrl |= SCI_CTRL_FLAGS_TIE;
446 sci_out(port, SCSCR, ctrl);
450 /* On SH3, SCIF may read end-of-break as a space->mark char */
451 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
453 static inline void sci_receive_chars(struct uart_port *port)
455 struct sci_port *sci_port = to_sci_port(port);
456 struct tty_struct *tty = port->info->port.tty;
457 int i, count, copied = 0;
458 unsigned short status;
461 status = sci_in(port, SCxSR);
462 if (!(status & SCxSR_RDxF(port)))
466 if (port->type == PORT_SCI)
467 count = sci_rxroom(port);
469 count = scif_rxroom(port);
471 /* Don't copy more bytes than there is room for in the buffer */
472 count = tty_buffer_request_room(tty, count);
474 /* If for any reason we can't copy more data, we're done! */
478 if (port->type == PORT_SCI) {
479 char c = sci_in(port, SCxRDR);
480 if (uart_handle_sysrq_char(port, c) ||
481 sci_port->break_flag)
484 tty_insert_flip_char(tty, c, TTY_NORMAL);
486 for (i = 0; i < count; i++) {
487 char c = sci_in(port, SCxRDR);
488 status = sci_in(port, SCxSR);
489 #if defined(CONFIG_CPU_SH3)
490 /* Skip "chars" during break */
491 if (sci_port->break_flag) {
493 (status & SCxSR_FER(port))) {
498 /* Nonzero => end-of-break */
499 pr_debug("scif: debounce<%02x>\n", c);
500 sci_port->break_flag = 0;
507 #endif /* CONFIG_CPU_SH3 */
508 if (uart_handle_sysrq_char(port, c)) {
513 /* Store data and status */
514 if (status&SCxSR_FER(port)) {
516 pr_debug("sci: frame error\n");
517 } else if (status&SCxSR_PER(port)) {
519 pr_debug("sci: parity error\n");
522 tty_insert_flip_char(tty, c, flag);
526 sci_in(port, SCxSR); /* dummy read */
527 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
530 port->icount.rx += count;
534 /* Tell the rest of the system the news. New characters! */
535 tty_flip_buffer_push(tty);
537 sci_in(port, SCxSR); /* dummy read */
538 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
542 #define SCI_BREAK_JIFFIES (HZ/20)
543 /* The sci generates interrupts during the break,
544 * 1 per millisecond or so during the break period, for 9600 baud.
545 * So dont bother disabling interrupts.
546 * But dont want more than 1 break event.
547 * Use a kernel timer to periodically poll the rx line until
548 * the break is finished.
550 static void sci_schedule_break_timer(struct sci_port *port)
552 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
553 add_timer(&port->break_timer);
555 /* Ensure that two consecutive samples find the break over. */
556 static void sci_break_timer(unsigned long data)
558 struct sci_port *port = (struct sci_port *)data;
560 if (sci_rxd_in(&port->port) == 0) {
561 port->break_flag = 1;
562 sci_schedule_break_timer(port);
563 } else if (port->break_flag == 1) {
565 port->break_flag = 2;
566 sci_schedule_break_timer(port);
568 port->break_flag = 0;
571 static inline int sci_handle_errors(struct uart_port *port)
574 unsigned short status = sci_in(port, SCxSR);
575 struct tty_struct *tty = port->info->port.tty;
577 if (status & SCxSR_ORER(port)) {
579 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
581 pr_debug("sci: overrun error\n");
584 if (status & SCxSR_FER(port)) {
585 if (sci_rxd_in(port) == 0) {
586 /* Notify of BREAK */
587 struct sci_port *sci_port = to_sci_port(port);
589 if (!sci_port->break_flag) {
590 sci_port->break_flag = 1;
591 sci_schedule_break_timer(sci_port);
593 /* Do sysrq handling. */
594 if (uart_handle_break(port))
596 pr_debug("sci: BREAK detected\n");
597 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
603 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
605 pr_debug("sci: frame error\n");
609 if (status & SCxSR_PER(port)) {
611 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
613 pr_debug("sci: parity error\n");
617 tty_flip_buffer_push(tty);
622 static inline int sci_handle_breaks(struct uart_port *port)
625 unsigned short status = sci_in(port, SCxSR);
626 struct tty_struct *tty = port->info->port.tty;
627 struct sci_port *s = &sci_ports[port->line];
629 if (uart_handle_break(port))
632 if (!s->break_flag && status & SCxSR_BRK(port)) {
633 #if defined(CONFIG_CPU_SH3)
637 /* Notify of BREAK */
638 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
640 pr_debug("sci: BREAK detected\n");
643 #if defined(SCIF_ORER)
644 /* XXX: Handle SCIF overrun error */
645 if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
646 sci_out(port, SCLSR, 0);
647 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
649 pr_debug("sci: overrun error\n");
655 tty_flip_buffer_push(tty);
660 static irqreturn_t sci_rx_interrupt(int irq, void *port)
662 /* I think sci_receive_chars has to be called irrespective
663 * of whether the I_IXOFF is set, otherwise, how is the interrupt
666 sci_receive_chars(port);
671 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
673 struct uart_port *port = ptr;
675 spin_lock_irq(&port->lock);
676 sci_transmit_chars(port);
677 spin_unlock_irq(&port->lock);
682 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
684 struct uart_port *port = ptr;
687 if (port->type == PORT_SCI) {
688 if (sci_handle_errors(port)) {
689 /* discard character in rx buffer */
691 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
694 #if defined(SCIF_ORER)
695 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
696 struct tty_struct *tty = port->info->port.tty;
698 sci_out(port, SCLSR, 0);
699 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
700 tty_flip_buffer_push(tty);
701 pr_debug("scif: overrun error\n");
704 sci_rx_interrupt(irq, ptr);
707 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
709 /* Kick the transmission */
710 sci_tx_interrupt(irq, ptr);
715 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
717 struct uart_port *port = ptr;
720 sci_handle_breaks(port);
721 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
726 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
728 unsigned short ssr_status, scr_status;
729 struct uart_port *port = ptr;
730 irqreturn_t ret = IRQ_NONE;
732 ssr_status = sci_in(port, SCxSR);
733 scr_status = sci_in(port, SCSCR);
736 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
737 ret = sci_tx_interrupt(irq, ptr);
739 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
740 ret = sci_rx_interrupt(irq, ptr);
741 /* Error Interrupt */
742 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
743 ret = sci_er_interrupt(irq, ptr);
744 /* Break Interrupt */
745 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
746 ret = sci_br_interrupt(irq, ptr);
751 #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
753 * Here we define a transistion notifier so that we can update all of our
754 * ports' baud rate when the peripheral clock changes.
756 static int sci_notifier(struct notifier_block *self,
757 unsigned long phase, void *p)
759 struct cpufreq_freqs *freqs = p;
762 if ((phase == CPUFREQ_POSTCHANGE) ||
763 (phase == CPUFREQ_RESUMECHANGE)) {
764 for (i = 0; i < SCI_NPORTS; i++) {
765 struct uart_port *port = &sci_ports[i].port;
769 * Update the uartclk per-port if frequency has
770 * changed, since it will no longer necessarily be
771 * consistent with the old frequency.
773 * Really we want to be able to do something like
774 * uart_change_speed() or something along those lines
775 * here to implicitly reset the per-port baud rate..
777 * Clean this up later..
779 clk = clk_get(NULL, "module_clk");
780 port->uartclk = clk_get_rate(clk);
784 printk(KERN_INFO "%s: got a postchange notification "
785 "for cpu %d (old %d, new %d)\n",
786 __func__, freqs->cpu, freqs->old, freqs->new);
792 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
793 #endif /* CONFIG_CPU_FREQ && CONFIG_HAVE_CLK */
795 static int sci_request_irq(struct sci_port *port)
798 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
799 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
802 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
803 "SCI Transmit Data Empty", "SCI Break" };
805 if (port->irqs[0] == port->irqs[1]) {
806 if (!port->irqs[0]) {
807 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
811 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
812 IRQF_DISABLED, "sci", port)) {
813 printk(KERN_ERR "sci: Cannot allocate irq.\n");
817 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
820 if (request_irq(port->irqs[i], handlers[i],
821 IRQF_DISABLED, desc[i], port)) {
822 printk(KERN_ERR "sci: Cannot allocate irq.\n");
831 static void sci_free_irq(struct sci_port *port)
835 if (port->irqs[0] == port->irqs[1]) {
837 printk(KERN_ERR "sci: sci_free_irq error\n");
839 free_irq(port->irqs[0], port);
841 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
845 free_irq(port->irqs[i], port);
850 static unsigned int sci_tx_empty(struct uart_port *port)
856 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
858 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
859 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
860 /* If you have signals for DTR and DCD, please implement here. */
863 static unsigned int sci_get_mctrl(struct uart_port *port)
865 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
868 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
871 static void sci_start_tx(struct uart_port *port)
875 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
876 ctrl = sci_in(port, SCSCR);
877 ctrl |= SCI_CTRL_FLAGS_TIE;
878 sci_out(port, SCSCR, ctrl);
881 static void sci_stop_tx(struct uart_port *port)
885 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
886 ctrl = sci_in(port, SCSCR);
887 ctrl &= ~SCI_CTRL_FLAGS_TIE;
888 sci_out(port, SCSCR, ctrl);
891 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
895 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
896 ctrl = sci_in(port, SCSCR);
897 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
898 sci_out(port, SCSCR, ctrl);
901 static void sci_stop_rx(struct uart_port *port)
905 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
906 ctrl = sci_in(port, SCSCR);
907 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
908 sci_out(port, SCSCR, ctrl);
911 static void sci_enable_ms(struct uart_port *port)
913 /* Nothing here yet .. */
916 static void sci_break_ctl(struct uart_port *port, int break_state)
918 /* Nothing here yet .. */
921 static int sci_startup(struct uart_port *port)
923 struct sci_port *s = &sci_ports[port->line];
928 #ifdef CONFIG_HAVE_CLK
929 s->clk = clk_get(NULL, "module_clk");
934 sci_start_rx(port, 1);
939 static void sci_shutdown(struct uart_port *port)
941 struct sci_port *s = &sci_ports[port->line];
950 #ifdef CONFIG_HAVE_CLK
956 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
957 struct ktermios *old)
959 struct sci_port *s = &sci_ports[port->line];
960 unsigned int status, baud, smr_val;
963 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
965 t = SCBRR_VALUE(baud, port->uartclk);
968 status = sci_in(port, SCxSR);
969 } while (!(status & SCxSR_TEND(port)));
971 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
973 if (port->type != PORT_SCI)
974 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
976 smr_val = sci_in(port, SCSMR) & 3;
977 if ((termios->c_cflag & CSIZE) == CS7)
979 if (termios->c_cflag & PARENB)
981 if (termios->c_cflag & PARODD)
983 if (termios->c_cflag & CSTOPB)
986 uart_update_timeout(port, termios->c_cflag, baud);
988 sci_out(port, SCSMR, smr_val);
992 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
995 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
997 sci_out(port, SCBRR, t);
998 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1001 if (likely(s->init_pins))
1002 s->init_pins(port, termios->c_cflag);
1004 sci_out(port, SCSCR, SCSCR_INIT(port));
1006 if ((termios->c_cflag & CREAD) != 0)
1007 sci_start_rx(port, 0);
1010 static const char *sci_type(struct uart_port *port)
1012 switch (port->type) {
1026 static void sci_release_port(struct uart_port *port)
1028 /* Nothing here yet .. */
1031 static int sci_request_port(struct uart_port *port)
1033 /* Nothing here yet .. */
1037 static void sci_config_port(struct uart_port *port, int flags)
1039 struct sci_port *s = &sci_ports[port->line];
1041 port->type = s->type;
1043 switch (port->type) {
1045 s->init_pins = sci_init_pins_sci;
1049 s->init_pins = sci_init_pins_scif;
1052 s->init_pins = sci_init_pins_irda;
1056 if (port->flags & UPF_IOREMAP && !port->membase) {
1057 #if defined(CONFIG_SUPERH64)
1058 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1059 port->membase = (void __iomem *)port->mapbase;
1061 port->membase = ioremap_nocache(port->mapbase, 0x40);
1064 printk(KERN_ERR "sci: can't remap port#%d\n", port->line);
1068 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1070 struct sci_port *s = &sci_ports[port->line];
1072 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1074 if (ser->baud_base < 2400)
1075 /* No paper tape reader for Mitch.. */
1081 static struct uart_ops sci_uart_ops = {
1082 .tx_empty = sci_tx_empty,
1083 .set_mctrl = sci_set_mctrl,
1084 .get_mctrl = sci_get_mctrl,
1085 .start_tx = sci_start_tx,
1086 .stop_tx = sci_stop_tx,
1087 .stop_rx = sci_stop_rx,
1088 .enable_ms = sci_enable_ms,
1089 .break_ctl = sci_break_ctl,
1090 .startup = sci_startup,
1091 .shutdown = sci_shutdown,
1092 .set_termios = sci_set_termios,
1094 .release_port = sci_release_port,
1095 .request_port = sci_request_port,
1096 .config_port = sci_config_port,
1097 .verify_port = sci_verify_port,
1098 #ifdef CONFIG_CONSOLE_POLL
1099 .poll_get_char = sci_poll_get_char,
1100 .poll_put_char = sci_poll_put_char,
1104 static void __init sci_init_ports(void)
1106 static int first = 1;
1114 for (i = 0; i < SCI_NPORTS; i++) {
1115 sci_ports[i].port.ops = &sci_uart_ops;
1116 sci_ports[i].port.iotype = UPIO_MEM;
1117 sci_ports[i].port.line = i;
1118 sci_ports[i].port.fifosize = 1;
1120 #if defined(__H8300H__) || defined(__H8300S__)
1122 sci_ports[i].enable = h8300_sci_enable;
1123 sci_ports[i].disable = h8300_sci_disable;
1125 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1126 #elif defined(CONFIG_HAVE_CLK)
1128 * XXX: We should use a proper SCI/SCIF clock
1131 struct clk *clk = clk_get(NULL, "module_clk");
1132 sci_ports[i].port.uartclk = clk_get_rate(clk);
1136 #error "Need a valid uartclk"
1139 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1140 sci_ports[i].break_timer.function = sci_break_timer;
1142 init_timer(&sci_ports[i].break_timer);
1146 int __init early_sci_setup(struct uart_port *port)
1148 if (unlikely(port->line > SCI_NPORTS))
1153 sci_ports[port->line].port.membase = port->membase;
1154 sci_ports[port->line].port.mapbase = port->mapbase;
1155 sci_ports[port->line].port.type = port->type;
1160 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1162 * Print a string to the serial port trying not to disturb
1163 * any possible real use of the port...
1165 static void serial_console_write(struct console *co, const char *s,
1168 struct uart_port *port = &serial_console_port->port;
1171 for (i = 0; i < count; i++) {
1173 sci_poll_put_char(port, '\r');
1175 sci_poll_put_char(port, *s++);
1179 static int __init serial_console_setup(struct console *co, char *options)
1181 struct uart_port *port;
1189 * Check whether an invalid uart number has been specified, and
1190 * if so, search for the first available port that does have
1193 if (co->index >= SCI_NPORTS)
1196 serial_console_port = &sci_ports[co->index];
1197 port = &serial_console_port->port;
1200 * Also need to check port->type, we don't actually have any
1201 * UPIO_PORT ports, but uart_report_port() handily misreports
1202 * it anyways if we don't have a port available by the time this is
1207 if (!port->membase || !port->mapbase)
1210 port->type = serial_console_port->type;
1212 #ifdef CONFIG_HAVE_CLK
1213 if (!serial_console_port->clk)
1214 serial_console_port->clk = clk_get(NULL, "module_clk");
1217 if (port->flags & UPF_IOREMAP)
1218 sci_config_port(port, 0);
1220 if (serial_console_port->enable)
1221 serial_console_port->enable(port);
1224 uart_parse_options(options, &baud, &parity, &bits, &flow);
1226 ret = uart_set_options(port, co, baud, parity, bits, flow);
1227 #if defined(__H8300H__) || defined(__H8300S__)
1228 /* disable rx interrupt */
1235 static struct console serial_console = {
1237 .device = uart_console_device,
1238 .write = serial_console_write,
1239 .setup = serial_console_setup,
1240 .flags = CON_PRINTBUFFER,
1242 .data = &sci_uart_driver,
1245 static int __init sci_console_init(void)
1248 register_console(&serial_console);
1251 console_initcall(sci_console_init);
1252 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1254 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1255 #define SCI_CONSOLE (&serial_console)
1257 #define SCI_CONSOLE 0
1260 static char banner[] __initdata =
1261 KERN_INFO "SuperH SCI(F) driver initialized\n";
1263 static struct uart_driver sci_uart_driver = {
1264 .owner = THIS_MODULE,
1265 .driver_name = "sci",
1266 .dev_name = "ttySC",
1268 .minor = SCI_MINOR_START,
1270 .cons = SCI_CONSOLE,
1274 * Register a set of serial devices attached to a platform device. The
1275 * list is terminated with a zero flags entry, which means we expect
1276 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1277 * remapping (such as sh64) should also set UPF_IOREMAP.
1279 static int __devinit sci_probe(struct platform_device *dev)
1281 struct plat_sci_port *p = dev->dev.platform_data;
1282 int i, ret = -EINVAL;
1284 for (i = 0; p && p->flags != 0; p++, i++) {
1285 struct sci_port *sciport = &sci_ports[i];
1288 if (unlikely(i == SCI_NPORTS)) {
1289 dev_notice(&dev->dev, "Attempting to register port "
1290 "%d when only %d are available.\n",
1292 dev_notice(&dev->dev, "Consider bumping "
1293 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1297 sciport->port.mapbase = p->mapbase;
1299 if (p->mapbase && !p->membase) {
1300 if (p->flags & UPF_IOREMAP) {
1301 p->membase = ioremap_nocache(p->mapbase, 0x40);
1302 if (IS_ERR(p->membase)) {
1303 ret = PTR_ERR(p->membase);
1308 * For the simple (and majority of) cases
1309 * where we don't need to do any remapping,
1310 * just cast the cookie directly.
1312 p->membase = (void __iomem *)p->mapbase;
1316 sciport->port.membase = p->membase;
1318 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1319 sciport->port.flags = p->flags;
1320 sciport->port.dev = &dev->dev;
1322 sciport->type = sciport->port.type = p->type;
1324 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1326 uart_add_one_port(&sci_uart_driver, &sciport->port);
1329 #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
1330 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1331 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1334 #ifdef CONFIG_SH_STANDARD_BIOS
1335 sh_bios_gdb_detach();
1341 for (i = i - 1; i >= 0; i--)
1342 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1347 static int __devexit sci_remove(struct platform_device *dev)
1351 for (i = 0; i < SCI_NPORTS; i++)
1352 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1357 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1361 for (i = 0; i < SCI_NPORTS; i++) {
1362 struct sci_port *p = &sci_ports[i];
1364 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1365 uart_suspend_port(&sci_uart_driver, &p->port);
1371 static int sci_resume(struct platform_device *dev)
1375 for (i = 0; i < SCI_NPORTS; i++) {
1376 struct sci_port *p = &sci_ports[i];
1378 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1379 uart_resume_port(&sci_uart_driver, &p->port);
1385 static struct platform_driver sci_driver = {
1387 .remove = __devexit_p(sci_remove),
1388 .suspend = sci_suspend,
1389 .resume = sci_resume,
1392 .owner = THIS_MODULE,
1396 static int __init sci_init(void)
1404 ret = uart_register_driver(&sci_uart_driver);
1405 if (likely(ret == 0)) {
1406 ret = platform_driver_register(&sci_driver);
1408 uart_unregister_driver(&sci_uart_driver);
1414 static void __exit sci_exit(void)
1416 platform_driver_unregister(&sci_driver);
1417 uart_unregister_driver(&sci_uart_driver);
1420 module_init(sci_init);
1421 module_exit(sci_exit);
1423 MODULE_LICENSE("GPL");
1424 MODULE_ALIAS("platform:sh-sci");