1 #include <linux/serial_core.h>
3 #include <linux/gpio.h>
5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6 #include <asm/regs306x.h>
8 #if defined(CONFIG_H8S2678)
9 #include <asm/regs267x.h>
12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20 # define SCIF0 0xA4400000
21 # define SCIF2 0xA4410000
22 # define SCSMR_Ir 0xA44A0000
23 # define IRDA_SCIF SCIF0
24 # define SCPCR 0xA4000116
25 # define SCPDR 0xA4000136
27 /* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35 # define PORT_PTCR 0xA405011EUL
36 # define PORT_PVCR 0xA4050122UL
37 # define SCIF_ORER 0x0200 /* overrun error bit */
38 #elif defined(CONFIG_SH_RTS7751R2D)
39 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
40 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41 # define SCIF_ORER 0x0001 /* overrun error bit */
42 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
49 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
50 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51 # define SCIF_ORER 0x0001 /* overrun error bit */
52 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
55 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
56 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
59 # define SCIF_ORER 0x0001 /* overrun error bit */
60 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
61 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
62 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
63 # define SCIF_ORER 0x0001 /* overrun error bit */
64 # define PACR 0xa4050100
65 # define PBCR 0xa4050102
66 # define SCSCR_INIT(port) 0x3B
67 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
73 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
74 # define PADR 0xA4050120
75 # define PSDR 0xA405013e
76 # define PWDR 0xA4050166
77 # define PSCR 0xA405011E
78 # define SCIF_ORER 0x0001 /* overrun error bit */
79 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
80 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82 # define SCSPTR0 SCPDR0
83 # define SCIF_ORER 0x0001 /* overrun error bit */
84 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86 # define SCSPTR0 0xa4050160
87 # define SCSPTR1 0xa405013e
88 # define SCSPTR2 0xa4050160
89 # define SCSPTR3 0xa405013e
90 # define SCSPTR4 0xa4050128
91 # define SCSPTR5 0xa4050128
92 # define SCIF_ORER 0x0001 /* overrun error bit */
93 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
95 # define SCIF_ORER 0x0001 /* overrun error bit */
96 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
98 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
99 # define SCIF_ORER 0x0001 /* overrun error bit */
100 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
102 # define SCIF_BASE_ADDR 0x01030000
103 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
104 # define SCIF_PTR2_OFFS 0x0000020
105 # define SCIF_LSR2_OFFS 0x0000024
106 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
107 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
108 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
109 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
110 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
111 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
112 #elif defined(CONFIG_H8S2678)
113 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
114 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
115 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
116 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
117 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
118 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
119 # define SCIF_ORER 0x0001 /* overrun error bit */
120 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
121 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
122 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
123 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
124 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
125 # define SCIF_ORER 0x0001 /* overrun error bit */
126 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
127 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
128 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
129 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
130 # define SCIF_ORER 0x0001 /* Overrun error bit */
131 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
132 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
133 defined(CONFIG_CPU_SUBTYPE_SH7786)
134 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
135 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
136 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
137 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
138 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
139 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
140 # define SCIF_ORER 0x0001 /* Overrun error bit */
141 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
143 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
144 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
145 defined(CONFIG_CPU_SUBTYPE_SH7263)
146 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
147 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
148 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
149 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
150 # if defined(CONFIG_CPU_SUBTYPE_SH7201)
151 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
152 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
153 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
154 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
156 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
157 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
158 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
159 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
160 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
161 # define SCIF_ORER 0x0001 /* overrun error bit */
162 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
164 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
165 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
166 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
167 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
168 # define SCIF_ORER 0x0001 /* Overrun error bit */
169 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
171 # error CPU subtype not defined
175 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
176 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
177 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
178 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
179 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
190 defined(CONFIG_CPU_SUBTYPE_SHX3)
191 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
193 #define SCI_CTRL_FLAGS_REIE 0
195 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
196 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
198 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
201 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
213 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
223 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
224 defined(CONFIG_CPU_SUBTYPE_SH7721)
225 # define SCIF_ORER 0x0200
226 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
227 # define SCIF_RFDC_MASK 0x007f
228 # define SCIF_TXROOM_MAX 64
229 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
230 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
231 # define SCIF_RFDC_MASK 0x007f
232 # define SCIF_TXROOM_MAX 64
233 /* SH7763 SCIF2 support */
234 # define SCIF2_RFDC_MASK 0x001f
235 # define SCIF2_TXROOM_MAX 16
237 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
238 # define SCIF_RFDC_MASK 0x001f
239 # define SCIF_TXROOM_MAX 16
243 #define SCIF_ORER 0x0000
246 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
247 #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
248 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
249 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
250 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
251 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
252 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
253 #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
255 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
256 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7721)
258 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
259 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
260 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
261 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
263 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
264 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
265 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
266 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
270 #define SCFCR_RFRST 0x0002
271 #define SCFCR_TFRST 0x0004
272 #define SCFCR_TCRST 0x4000
273 #define SCFCR_MCE 0x0008
275 #define SCI_MAJOR 204
276 #define SCI_MINOR_START 8
278 /* Generic serial flags */
279 #define SCI_RX_THROTTLE 0x0000001
281 #define SCI_MAGIC 0xbabeface
284 * Events are used to schedule things to happen at timer-interrupt
285 * time, instead of at rs interrupt time.
287 #define SCI_EVENT_WRITE_WAKEUP 0
289 #define SCI_IN(size, offset) \
291 return ioread8(port->membase + (offset)); \
293 return ioread16(port->membase + (offset)); \
295 #define SCI_OUT(size, offset, value) \
297 iowrite8(value, port->membase + (offset)); \
298 } else if ((size) == 16) { \
299 iowrite16(value, port->membase + (offset)); \
302 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
303 static inline unsigned int sci_##name##_in(struct uart_port *port) \
305 if (port->type == PORT_SCIF) { \
306 SCI_IN(scif_size, scif_offset) \
307 } else { /* PORT_SCI or PORT_SCIFA */ \
308 SCI_IN(sci_size, sci_offset); \
311 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
313 if (port->type == PORT_SCIF) { \
314 SCI_OUT(scif_size, scif_offset, value) \
315 } else { /* PORT_SCI or PORT_SCIFA */ \
316 SCI_OUT(sci_size, sci_offset, value); \
320 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
321 static inline unsigned int sci_##name##_in(struct uart_port *port) \
323 SCI_IN(scif_size, scif_offset); \
325 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
327 SCI_OUT(scif_size, scif_offset, value); \
330 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
331 static inline unsigned int sci_##name##_in(struct uart_port* port) \
333 SCI_IN(sci_size, sci_offset); \
335 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
337 SCI_OUT(sci_size, sci_offset, value); \
340 #ifdef CONFIG_CPU_SH3
341 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
342 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
343 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
344 h8_sci_offset, h8_sci_size) \
345 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
346 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
347 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
348 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
349 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
350 defined(CONFIG_CPU_SUBTYPE_SH7721)
351 #define SCIF_FNS(name, scif_offset, scif_size) \
352 CPU_SCIF_FNS(name, scif_offset, scif_size)
354 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
355 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
356 h8_sci_offset, h8_sci_size) \
357 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
358 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
359 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
361 #elif defined(__H8300H__) || defined(__H8300S__)
362 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
363 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
364 h8_sci_offset, h8_sci_size) \
365 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
366 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
367 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
368 defined(CONFIG_CPU_SUBTYPE_SH7724)
369 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
370 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
371 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
372 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
374 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
375 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
376 h8_sci_offset, h8_sci_size) \
377 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
378 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
379 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
382 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
383 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
384 defined(CONFIG_CPU_SUBTYPE_SH7721)
386 SCIF_FNS(SCSMR, 0x00, 16)
387 SCIF_FNS(SCBRR, 0x04, 8)
388 SCIF_FNS(SCSCR, 0x08, 16)
389 SCIF_FNS(SCTDSR, 0x0c, 8)
390 SCIF_FNS(SCFER, 0x10, 16)
391 SCIF_FNS(SCxSR, 0x14, 16)
392 SCIF_FNS(SCFCR, 0x18, 16)
393 SCIF_FNS(SCFDR, 0x1c, 16)
394 SCIF_FNS(SCxTDR, 0x20, 8)
395 SCIF_FNS(SCxRDR, 0x24, 8)
396 SCIF_FNS(SCLSR, 0x24, 16)
397 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
398 defined(CONFIG_CPU_SUBTYPE_SH7724)
399 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
400 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
401 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
402 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
403 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
404 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
405 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
406 SCIF_FNS(SCTDSR, 0x0c, 8)
407 SCIF_FNS(SCFER, 0x10, 16)
408 SCIF_FNS(SCFCR, 0x18, 16)
409 SCIF_FNS(SCFDR, 0x1c, 16)
410 SCIF_FNS(SCLSR, 0x24, 16)
412 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
413 /* name off sz off sz off sz off sz off sz*/
414 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
415 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
416 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
417 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
418 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
419 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
420 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
421 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
422 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
423 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
424 defined(CONFIG_CPU_SUBTYPE_SH7786)
425 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
426 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
427 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
428 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
429 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
430 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
431 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
432 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
433 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
434 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
435 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
436 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
437 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
439 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
440 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
441 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
443 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
445 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
448 #define sci_in(port, reg) sci_##reg##_in(port)
449 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
451 /* H8/300 series SCI pins assignment */
452 #if defined(__H8300H__) || defined(__H8300S__)
453 static const struct __attribute__((packed)) {
454 int port; /* GPIO port no */
455 unsigned short rx,tx; /* GPIO bit no */
456 } h8300_sci_pins[] = {
457 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
459 .port = H8300_GPIO_P9,
464 .port = H8300_GPIO_P9,
469 .port = H8300_GPIO_PB,
473 #elif defined(CONFIG_H8S2678)
475 .port = H8300_GPIO_P3,
480 .port = H8300_GPIO_P3,
485 .port = H8300_GPIO_P5,
493 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
494 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
495 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
496 defined(CONFIG_CPU_SUBTYPE_SH7709)
497 static inline int sci_rxd_in(struct uart_port *port)
499 if (port->mapbase == 0xfffffe80)
500 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
501 if (port->mapbase == 0xa4000150)
502 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
503 if (port->mapbase == 0xa4000140)
504 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
507 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
508 static inline int sci_rxd_in(struct uart_port *port)
510 if (port->mapbase == SCIF0)
511 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
512 if (port->mapbase == SCIF2)
513 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
516 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
517 static inline int sci_rxd_in(struct uart_port *port)
519 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
521 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
522 defined(CONFIG_CPU_SUBTYPE_SH7721)
523 static inline int sci_rxd_in(struct uart_port *port)
525 if (port->mapbase == 0xa4430000)
526 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
527 else if (port->mapbase == 0xa4438000)
528 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
531 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
532 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
533 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
534 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
535 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
536 defined(CONFIG_CPU_SUBTYPE_SH7091)
537 static inline int sci_rxd_in(struct uart_port *port)
539 if (port->mapbase == 0xffe00000)
540 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
541 if (port->mapbase == 0xffe80000)
542 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
545 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
546 static inline int sci_rxd_in(struct uart_port *port)
548 if (port->mapbase == 0xffe80000)
549 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
552 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
553 static inline int sci_rxd_in(struct uart_port *port)
555 if (port->mapbase == 0xfe600000)
556 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
557 if (port->mapbase == 0xfe610000)
558 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
559 if (port->mapbase == 0xfe620000)
560 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
563 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
564 static inline int sci_rxd_in(struct uart_port *port)
566 if (port->mapbase == 0xffe00000)
567 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
568 if (port->mapbase == 0xffe10000)
569 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
570 if (port->mapbase == 0xffe20000)
571 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
572 if (port->mapbase == 0xffe30000)
573 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
576 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
577 static inline int sci_rxd_in(struct uart_port *port)
579 if (port->mapbase == 0xffe00000)
580 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
583 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
584 static inline int sci_rxd_in(struct uart_port *port)
586 if (port->mapbase == 0xffe00000)
587 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
588 if (port->mapbase == 0xffe10000)
589 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
590 if (port->mapbase == 0xffe20000)
591 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
595 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
596 static inline int sci_rxd_in(struct uart_port *port)
598 if (port->mapbase == 0xffe00000)
599 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
600 if (port->mapbase == 0xffe10000)
601 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
602 if (port->mapbase == 0xffe20000)
603 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
604 if (port->mapbase == 0xa4e30000)
605 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
606 if (port->mapbase == 0xa4e40000)
607 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
608 if (port->mapbase == 0xa4e50000)
609 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
612 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
613 # define SCFSR 0x0010
614 # define SCASSR 0x0014
615 static inline int sci_rxd_in(struct uart_port *port)
617 if (port->type == PORT_SCIF)
618 return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
619 if (port->type == PORT_SCIFA)
620 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
623 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
624 static inline int sci_rxd_in(struct uart_port *port)
626 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
628 #elif defined(__H8300H__) || defined(__H8300S__)
629 static inline int sci_rxd_in(struct uart_port *port)
631 int ch = (port->mapbase - SMR0) >> 3;
632 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
634 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
635 static inline int sci_rxd_in(struct uart_port *port)
637 if (port->mapbase == 0xffe00000)
638 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xffe08000)
640 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
641 if (port->mapbase == 0xffe10000)
642 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
646 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
647 static inline int sci_rxd_in(struct uart_port *port)
649 if (port->mapbase == 0xff923000)
650 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
651 if (port->mapbase == 0xff924000)
652 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port->mapbase == 0xff925000)
654 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
657 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
658 static inline int sci_rxd_in(struct uart_port *port)
660 if (port->mapbase == 0xffe00000)
661 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
662 if (port->mapbase == 0xffe10000)
663 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
666 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
667 defined(CONFIG_CPU_SUBTYPE_SH7786)
668 static inline int sci_rxd_in(struct uart_port *port)
670 if (port->mapbase == 0xffea0000)
671 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
672 if (port->mapbase == 0xffeb0000)
673 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
674 if (port->mapbase == 0xffec0000)
675 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
676 if (port->mapbase == 0xffed0000)
677 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
678 if (port->mapbase == 0xffee0000)
679 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
680 if (port->mapbase == 0xffef0000)
681 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
684 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
685 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
686 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
687 defined(CONFIG_CPU_SUBTYPE_SH7263)
688 static inline int sci_rxd_in(struct uart_port *port)
690 if (port->mapbase == 0xfffe8000)
691 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
692 if (port->mapbase == 0xfffe8800)
693 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
694 if (port->mapbase == 0xfffe9000)
695 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
696 if (port->mapbase == 0xfffe9800)
697 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
698 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
699 if (port->mapbase == 0xfffeA000)
700 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
701 if (port->mapbase == 0xfffeA800)
702 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
703 if (port->mapbase == 0xfffeB000)
704 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
705 if (port->mapbase == 0xfffeB800)
706 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
710 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
711 static inline int sci_rxd_in(struct uart_port *port)
713 if (port->mapbase == 0xf8400000)
714 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
715 if (port->mapbase == 0xf8410000)
716 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
717 if (port->mapbase == 0xf8420000)
718 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
721 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
722 static inline int sci_rxd_in(struct uart_port *port)
724 if (port->mapbase == 0xffc30000)
725 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
726 if (port->mapbase == 0xffc40000)
727 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
728 if (port->mapbase == 0xffc50000)
729 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
730 if (port->mapbase == 0xffc60000)
731 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
737 * Values for the BitRate Register (SCBRR)
739 * The values are actually divisors for a frequency which can
740 * be internal to the SH3 (14.7456MHz) or derived from an external
741 * clock source. This driver assumes the internal clock is used;
742 * to support using an external clock source, config options or
743 * possibly command-line options would need to be added.
745 * Also, to support speeds below 2400 (why?) the lower 2 bits of
746 * the SCSMR register would also need to be set to non-zero values.
748 * -- Greg Banks 27Feb2000
750 * Answer: The SCBRR register is only eight bits, and the value in
751 * it gets larger with lower baud rates. At around 2400 (depending on
752 * the peripherial module clock) you run out of bits. However the
753 * lower two bits of SCSMR allow the module clock to be divided down,
754 * scaling the value which is needed in SCBRR.
756 * -- Stuart Menefy - 23 May 2000
758 * I meant, why would anyone bother with bitrates below 2400.
760 * -- Greg Banks - 7Jul2000
762 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
763 * tape reader as a console!
765 * -- Mitch Davis - 15 Jul 2000
768 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
769 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
770 defined(CONFIG_CPU_SUBTYPE_SH7786)
771 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
772 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
773 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
774 defined(CONFIG_CPU_SUBTYPE_SH7721)
775 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
776 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
777 defined(CONFIG_CPU_SUBTYPE_SH7724)
778 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
780 if (port->type == PORT_SCIF)
781 return (clk+16*bps)/(32*bps)-1;
783 return ((clk*2)+16*bps)/(16*bps)-1;
785 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
786 #elif defined(__H8300H__) || defined(__H8300S__)
787 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
788 #else /* Generic SH */
789 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)