2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #define pr_fmt(fmt) "intc: " fmt
21 #include <linux/init.h>
22 #include <linux/irq.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/sh_intc.h>
27 #include <linux/sysdev.h>
28 #include <linux/list.h>
29 #include <linux/spinlock.h>
30 #include <linux/radix-tree.h>
31 #include "internals.h"
34 DEFINE_RAW_SPINLOCK(intc_big_lock);
35 unsigned int nr_intc_controllers;
38 * Default priority level
39 * - this needs to be at least 2 for 5-bit priorities on 7780
41 static unsigned int default_prio_level = 2; /* 2 - 16 */
42 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
44 unsigned int intc_get_dfl_prio_level(void)
46 return default_prio_level;
49 unsigned int intc_get_prio_level(unsigned int irq)
51 return intc_prio_level[irq];
54 void intc_set_prio_level(unsigned int irq, unsigned int level)
58 raw_spin_lock_irqsave(&intc_big_lock, flags);
59 intc_prio_level[irq] = level;
60 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
63 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
65 generic_handle_irq((unsigned int)get_irq_data(irq));
68 static void __init intc_register_irq(struct intc_desc *desc,
69 struct intc_desc_int *d,
73 struct intc_handle_int *hp;
74 struct irq_data *irq_data;
75 unsigned int data[2], primary;
79 * Register the IRQ position with the global IRQ map, then insert
80 * it in to the radix tree.
84 raw_spin_lock_irqsave(&intc_big_lock, flags);
85 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
86 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
89 * Prefer single interrupt source bitmap over other combinations:
91 * 1. bitmap, single interrupt source
92 * 2. priority, single interrupt source
93 * 3. bitmap, multiple interrupt sources (groups)
94 * 4. priority, multiple interrupt sources (groups)
96 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
97 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
100 if (!data[0] && data[1])
103 if (!data[0] && !data[1])
104 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
107 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
108 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
113 BUG_ON(!data[primary]); /* must have primary masking method */
115 irq_data = irq_get_irq_data(irq);
117 disable_irq_nosync(irq);
118 set_irq_chip_and_handler_name(irq, &d->chip,
119 handle_level_irq, "level");
120 set_irq_chip_data(irq, (void *)data[primary]);
125 intc_set_prio_level(irq, intc_get_dfl_prio_level());
127 /* enable secondary masking method if present */
129 _intc_enable(irq_data, data[!primary]);
131 /* add irq to d->prio list if priority is available */
133 hp = d->prio + d->nr_prio;
135 hp->handle = data[1];
139 * only secondary priority should access registers, so
140 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
142 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
143 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
148 /* add irq to d->sense list if sense is available */
149 data[0] = intc_get_sense_handle(desc, d, enum_id);
151 (d->sense + d->nr_sense)->irq = irq;
152 (d->sense + d->nr_sense)->handle = data[0];
156 /* irq should be disabled by default */
157 d->chip.irq_mask(irq_data);
159 intc_set_ack_handle(irq, desc, d, enum_id);
160 intc_set_dist_handle(irq, desc, d, enum_id);
165 static unsigned int __init save_reg(struct intc_desc_int *d,
171 value = intc_phys_to_virt(d, value);
183 int __init register_intc_controller(struct intc_desc *desc)
185 unsigned int i, k, smp;
186 struct intc_hw_desc *hw = &desc->hw;
187 struct intc_desc_int *d;
188 struct resource *res;
190 pr_info("Registered controller '%s' with %u IRQs\n",
191 desc->name, hw->nr_vectors);
193 d = kzalloc(sizeof(*d), GFP_NOWAIT);
197 INIT_LIST_HEAD(&d->list);
198 list_add_tail(&d->list, &intc_list);
200 raw_spin_lock_init(&d->lock);
202 d->index = nr_intc_controllers;
204 if (desc->num_resources) {
205 d->nr_windows = desc->num_resources;
206 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
211 for (k = 0; k < d->nr_windows; k++) {
212 res = desc->resource + k;
213 WARN_ON(resource_type(res) != IORESOURCE_MEM);
214 d->window[k].phys = res->start;
215 d->window[k].size = resource_size(res);
216 d->window[k].virt = ioremap_nocache(res->start,
218 if (!d->window[k].virt)
223 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
224 #ifdef CONFIG_INTC_BALANCING
226 d->nr_reg += hw->nr_mask_regs;
228 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
229 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
230 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
231 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
233 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
238 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
245 for (i = 0; i < hw->nr_mask_regs; i++) {
246 smp = IS_SMP(hw->mask_regs[i]);
247 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
248 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
249 #ifdef CONFIG_INTC_BALANCING
250 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
256 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
261 for (i = 0; i < hw->nr_prio_regs; i++) {
262 smp = IS_SMP(hw->prio_regs[i]);
263 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
264 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
268 if (hw->sense_regs) {
269 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
274 for (i = 0; i < hw->nr_sense_regs; i++)
275 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
279 for (i = 0; i < hw->nr_subgroups; i++)
280 if (hw->subgroups[i].reg)
281 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
283 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
284 d->chip.name = desc->name;
287 for (i = 0; i < hw->nr_ack_regs; i++)
288 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
290 d->chip.irq_mask_ack = d->chip.irq_disable;
292 /* disable bits matching force_disable before registering irqs */
293 if (desc->force_disable)
294 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
296 /* disable bits matching force_enable before registering irqs */
297 if (desc->force_enable)
298 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
300 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
302 /* register the vectors one by one */
303 for (i = 0; i < hw->nr_vectors; i++) {
304 struct intc_vect *vect = hw->vectors + i;
305 unsigned int irq = evt2irq(vect->vect);
311 res = irq_alloc_desc_at(irq, numa_node_id());
312 if (res != irq && res != -EEXIST) {
313 pr_err("can't get irq_desc for %d\n", irq);
317 intc_irq_xlate_set(irq, vect->enum_id, d);
318 intc_register_irq(desc, d, vect->enum_id, irq);
320 for (k = i + 1; k < hw->nr_vectors; k++) {
321 struct intc_vect *vect2 = hw->vectors + k;
322 unsigned int irq2 = evt2irq(vect2->vect);
324 if (vect->enum_id != vect2->enum_id)
328 * In the case of multi-evt handling and sparse
329 * IRQ support, each vector still needs to have
330 * its own backing irq_desc.
332 res = irq_alloc_desc_at(irq2, numa_node_id());
333 if (res != irq2 && res != -EEXIST) {
334 pr_err("can't get irq_desc for %d\n", irq2);
340 /* redirect this interrupts to the first one */
341 set_irq_chip(irq2, &dummy_irq_chip);
342 set_irq_chained_handler(irq2, intc_redirect_irq);
343 set_irq_data(irq2, (void *)irq);
347 intc_subgroup_init(desc, d);
349 /* enable bits matching force_enable after registering irqs */
350 if (desc->force_enable)
351 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
353 nr_intc_controllers++;
365 for (k = 0; k < d->nr_windows; k++)
366 if (d->window[k].virt)
367 iounmap(d->window[k].virt);
373 pr_err("unable to allocate INTC memory\n");
379 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
381 struct intc_desc_int *d;
383 d = container_of(dev, struct intc_desc_int, sysdev);
385 return sprintf(buf, "%s\n", d->chip.name);
388 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
390 static int intc_suspend(struct sys_device *dev, pm_message_t state)
392 struct intc_desc_int *d;
393 struct irq_data *data;
394 struct irq_desc *desc;
395 struct irq_chip *chip;
398 /* get intc controller associated with this sysdev */
399 d = container_of(dev, struct intc_desc_int, sysdev);
401 switch (state.event) {
403 if (d->state.event != PM_EVENT_FREEZE)
406 for_each_active_irq(irq) {
407 desc = irq_to_desc(irq);
408 data = irq_get_irq_data(irq);
409 chip = irq_data_get_irq_chip(data);
412 * This will catch the redirect and VIRQ cases
413 * due to the dummy_irq_chip being inserted.
415 if (chip != &d->chip)
417 if (desc->status & IRQ_DISABLED)
418 chip->irq_disable(data);
420 chip->irq_enable(data);
423 case PM_EVENT_FREEZE:
424 /* nothing has to be done */
426 case PM_EVENT_SUSPEND:
427 /* enable wakeup irqs belonging to this intc controller */
428 for_each_active_irq(irq) {
429 desc = irq_to_desc(irq);
430 data = irq_get_irq_data(irq);
431 chip = irq_data_get_irq_chip(data);
433 if (chip != &d->chip)
435 if ((desc->status & IRQ_WAKEUP))
436 chip->irq_enable(data);
446 static int intc_resume(struct sys_device *dev)
448 return intc_suspend(dev, PMSG_ON);
451 struct sysdev_class intc_sysdev_class = {
453 .suspend = intc_suspend,
454 .resume = intc_resume,
457 /* register this intc as sysdev to allow suspend/resume */
458 static int __init register_intc_sysdevs(void)
460 struct intc_desc_int *d;
463 error = sysdev_class_register(&intc_sysdev_class);
465 list_for_each_entry(d, &intc_list, list) {
466 d->sysdev.id = d->index;
467 d->sysdev.cls = &intc_sysdev_class;
468 error = sysdev_register(&d->sysdev);
470 error = sysdev_create_file(&d->sysdev,
478 pr_err("sysdev registration error\n");
482 device_initcall(register_intc_sysdevs);