2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/sh_intc.h>
26 #include <linux/sysdev.h>
27 #include <linux/list.h>
28 #include <linux/topology.h>
29 #include <linux/bitmap.h>
30 #include <linux/cpumask.h>
31 #include <asm/sizes.h>
33 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
34 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
35 ((addr_e) << 16) | ((addr_d << 24)))
37 #define _INTC_SHIFT(h) (h & 0x1f)
38 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
39 #define _INTC_FN(h) ((h >> 9) & 0xf)
40 #define _INTC_MODE(h) ((h >> 13) & 0x7)
41 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
42 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
44 struct intc_handle_int {
55 struct intc_desc_int {
56 struct list_head list;
57 struct sys_device sysdev;
64 struct intc_handle_int *prio;
66 struct intc_handle_int *sense;
67 unsigned int nr_sense;
68 struct intc_window *window;
69 unsigned int nr_windows;
73 static LIST_HEAD(intc_list);
76 * The intc_irq_map provides a global map of bound IRQ vectors for a
77 * given platform. Allocation of IRQs are either static through the CPU
78 * vector map, or dynamic in the case of board mux vectors or MSI.
80 * As this is a central point for all IRQ controllers on the system,
81 * each of the available sources are mapped out here. This combined with
82 * sparseirq makes it quite trivial to keep the vector map tightly packed
83 * when dynamically creating IRQs, as well as tying in to otherwise
84 * unused irq_desc positions in the sparse array.
86 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
87 static DEFINE_SPINLOCK(vector_lock);
90 #define IS_SMP(x) x.smp
91 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
92 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
95 #define INTC_REG(d, x, c) (d->reg[(x)])
96 #define SMP_NR(d, x) 1
99 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
100 static unsigned int default_prio_level = 2; /* 2 - 16 */
101 static unsigned long ack_handle[NR_IRQS];
102 #ifdef CONFIG_INTC_BALANCING
103 static unsigned long dist_handle[NR_IRQS];
106 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
108 struct irq_chip *chip = get_irq_chip(irq);
109 return container_of(chip, struct intc_desc_int, chip);
112 static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
113 unsigned long address)
115 struct intc_window *window;
118 /* scan through physical windows and convert address */
119 for (k = 0; k < d->nr_windows; k++) {
120 window = d->window + k;
122 if (address < window->phys)
125 if (address >= (window->phys + window->size))
128 address -= window->phys;
129 address += (unsigned long)window->virt;
134 /* no windows defined, register must be 1:1 mapped virt:phys */
138 static unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address)
142 address = intc_phys_to_virt(d, address);
144 for (k = 0; k < d->nr_reg; k++) {
145 if (d->reg[k] == address)
153 static inline unsigned int set_field(unsigned int value,
154 unsigned int field_value,
157 unsigned int width = _INTC_WIDTH(handle);
158 unsigned int shift = _INTC_SHIFT(handle);
160 value &= ~(((1 << width) - 1) << shift);
161 value |= field_value << shift;
165 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
167 __raw_writeb(set_field(0, data, h), addr);
168 (void)__raw_readb(addr); /* Defeat write posting */
171 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
173 __raw_writew(set_field(0, data, h), addr);
174 (void)__raw_readw(addr); /* Defeat write posting */
177 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
179 __raw_writel(set_field(0, data, h), addr);
180 (void)__raw_readl(addr); /* Defeat write posting */
183 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
186 local_irq_save(flags);
187 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
188 (void)__raw_readb(addr); /* Defeat write posting */
189 local_irq_restore(flags);
192 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
195 local_irq_save(flags);
196 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
197 (void)__raw_readw(addr); /* Defeat write posting */
198 local_irq_restore(flags);
201 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
204 local_irq_save(flags);
205 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
206 (void)__raw_readl(addr); /* Defeat write posting */
207 local_irq_restore(flags);
210 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
212 static void (*intc_reg_fns[])(unsigned long addr,
214 unsigned long data) = {
215 [REG_FN_WRITE_BASE + 0] = write_8,
216 [REG_FN_WRITE_BASE + 1] = write_16,
217 [REG_FN_WRITE_BASE + 3] = write_32,
218 [REG_FN_MODIFY_BASE + 0] = modify_8,
219 [REG_FN_MODIFY_BASE + 1] = modify_16,
220 [REG_FN_MODIFY_BASE + 3] = modify_32,
223 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
224 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
225 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
226 MODE_PRIO_REG, /* Priority value written to enable interrupt */
227 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
230 static void intc_mode_field(unsigned long addr,
231 unsigned long handle,
232 void (*fn)(unsigned long,
237 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
240 static void intc_mode_zero(unsigned long addr,
241 unsigned long handle,
242 void (*fn)(unsigned long,
250 static void intc_mode_prio(unsigned long addr,
251 unsigned long handle,
252 void (*fn)(unsigned long,
257 fn(addr, handle, intc_prio_level[irq]);
260 static void (*intc_enable_fns[])(unsigned long addr,
261 unsigned long handle,
262 void (*fn)(unsigned long,
265 unsigned int irq) = {
266 [MODE_ENABLE_REG] = intc_mode_field,
267 [MODE_MASK_REG] = intc_mode_zero,
268 [MODE_DUAL_REG] = intc_mode_field,
269 [MODE_PRIO_REG] = intc_mode_prio,
270 [MODE_PCLR_REG] = intc_mode_prio,
273 static void (*intc_disable_fns[])(unsigned long addr,
274 unsigned long handle,
275 void (*fn)(unsigned long,
278 unsigned int irq) = {
279 [MODE_ENABLE_REG] = intc_mode_zero,
280 [MODE_MASK_REG] = intc_mode_field,
281 [MODE_DUAL_REG] = intc_mode_field,
282 [MODE_PRIO_REG] = intc_mode_zero,
283 [MODE_PCLR_REG] = intc_mode_field,
286 #ifdef CONFIG_INTC_BALANCING
287 static inline void intc_balancing_enable(unsigned int irq)
289 struct intc_desc_int *d = get_intc_desc(irq);
290 unsigned long handle = dist_handle[irq];
293 if (irq_balancing_disabled(irq) || !handle)
296 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
297 intc_reg_fns[_INTC_FN(handle)](addr, handle, 1);
300 static inline void intc_balancing_disable(unsigned int irq)
302 struct intc_desc_int *d = get_intc_desc(irq);
303 unsigned long handle = dist_handle[irq];
306 if (irq_balancing_disabled(irq) || !handle)
309 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
310 intc_reg_fns[_INTC_FN(handle)](addr, handle, 0);
313 static unsigned int intc_dist_data(struct intc_desc *desc,
314 struct intc_desc_int *d,
317 struct intc_mask_reg *mr = desc->hw.mask_regs;
318 unsigned int i, j, fn, mode;
319 unsigned long reg_e, reg_d;
321 for (i = 0; mr && enum_id && i < desc->hw.nr_mask_regs; i++) {
322 mr = desc->hw.mask_regs + i;
325 * Skip this entry if there's no auto-distribution
326 * register associated with it.
331 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
332 if (mr->enum_ids[j] != enum_id)
335 fn = REG_FN_MODIFY_BASE;
336 mode = MODE_ENABLE_REG;
337 reg_e = mr->dist_reg;
338 reg_d = mr->dist_reg;
340 fn += (mr->reg_width >> 3) - 1;
341 return _INTC_MK(fn, mode,
342 intc_get_reg(d, reg_e),
343 intc_get_reg(d, reg_d),
345 (mr->reg_width - 1) - j);
350 * It's possible we've gotten here with no distribution options
351 * available for the IRQ in question, so we just skip over those.
356 static inline void intc_balancing_enable(unsigned int irq)
360 static inline void intc_balancing_disable(unsigned int irq)
365 static inline void _intc_enable(unsigned int irq, unsigned long handle)
367 struct intc_desc_int *d = get_intc_desc(irq);
371 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
373 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
376 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
377 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
378 [_INTC_FN(handle)], irq);
381 intc_balancing_enable(irq);
384 static void intc_enable(unsigned int irq)
386 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
389 static void intc_disable(unsigned int irq)
391 struct intc_desc_int *d = get_intc_desc(irq);
392 unsigned long handle = (unsigned long)get_irq_chip_data(irq);
396 intc_balancing_disable(irq);
398 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
400 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
403 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
404 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
405 [_INTC_FN(handle)], irq);
409 static void (*intc_enable_noprio_fns[])(unsigned long addr,
410 unsigned long handle,
411 void (*fn)(unsigned long,
414 unsigned int irq) = {
415 [MODE_ENABLE_REG] = intc_mode_field,
416 [MODE_MASK_REG] = intc_mode_zero,
417 [MODE_DUAL_REG] = intc_mode_field,
418 [MODE_PRIO_REG] = intc_mode_field,
419 [MODE_PCLR_REG] = intc_mode_field,
422 static void intc_enable_disable(struct intc_desc_int *d,
423 unsigned long handle, int do_enable)
427 void (*fn)(unsigned long, unsigned long,
428 void (*)(unsigned long, unsigned long, unsigned long),
432 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
433 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
434 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
435 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
438 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
439 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
440 fn = intc_disable_fns[_INTC_MODE(handle)];
441 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
446 static int intc_set_wake(unsigned int irq, unsigned int on)
448 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
453 * This is held with the irq desc lock held, so we don't require any
454 * additional locking here at the intc desc level. The affinity mask is
455 * later tested in the enable/disable paths.
457 static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
459 if (!cpumask_intersects(cpumask, cpu_online_mask))
462 cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
468 static void intc_mask_ack(unsigned int irq)
470 struct intc_desc_int *d = get_intc_desc(irq);
471 unsigned long handle = ack_handle[irq];
476 /* read register and write zero only to the associated bit */
478 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
479 switch (_INTC_FN(handle)) {
480 case REG_FN_MODIFY_BASE + 0: /* 8bit */
482 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
484 case REG_FN_MODIFY_BASE + 1: /* 16bit */
486 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
488 case REG_FN_MODIFY_BASE + 3: /* 32bit */
490 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
499 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
506 * this doesn't scale well, but...
508 * this function should only be used for cerain uncommon
509 * operations such as intc_set_priority() and intc_set_sense()
510 * and in those rare cases performance doesn't matter that much.
511 * keeping the memory footprint low is more important.
513 * one rather simple way to speed this up and still keep the
514 * memory footprint down is to make sure the array is sorted
515 * and then perform a bisect to lookup the irq.
517 for (i = 0; i < nr_hp; i++) {
518 if ((hp + i)->irq != irq)
527 int intc_set_priority(unsigned int irq, unsigned int prio)
529 struct intc_desc_int *d = get_intc_desc(irq);
530 struct intc_handle_int *ihp;
532 if (!intc_prio_level[irq] || prio <= 1)
535 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
537 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
540 intc_prio_level[irq] = prio;
543 * only set secondary masking method directly
544 * primary masking method is using intc_prio_level[irq]
545 * priority level will be set during next enable()
547 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
548 _intc_enable(irq, ihp->handle);
553 #define VALID(x) (x | 0x80)
555 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
556 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
557 [IRQ_TYPE_EDGE_RISING] = VALID(1),
558 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
559 /* SH7706, SH7707 and SH7709 do not support high level triggered */
560 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
561 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
562 !defined(CONFIG_CPU_SUBTYPE_SH7709)
563 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
567 static int intc_set_sense(unsigned int irq, unsigned int type)
569 struct intc_desc_int *d = get_intc_desc(irq);
570 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
571 struct intc_handle_int *ihp;
577 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
579 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
580 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
585 static intc_enum __init intc_grp_id(struct intc_desc *desc,
588 struct intc_group *g = desc->hw.groups;
591 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
592 g = desc->hw.groups + i;
594 for (j = 0; g->enum_ids[j]; j++) {
595 if (g->enum_ids[j] != enum_id)
605 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
606 struct intc_desc_int *d,
608 unsigned int *reg_idx,
609 unsigned int *fld_idx)
611 struct intc_mask_reg *mr = desc->hw.mask_regs;
612 unsigned int fn, mode;
613 unsigned long reg_e, reg_d;
615 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
616 mr = desc->hw.mask_regs + *reg_idx;
618 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
619 if (mr->enum_ids[*fld_idx] != enum_id)
622 if (mr->set_reg && mr->clr_reg) {
623 fn = REG_FN_WRITE_BASE;
624 mode = MODE_DUAL_REG;
628 fn = REG_FN_MODIFY_BASE;
630 mode = MODE_ENABLE_REG;
634 mode = MODE_MASK_REG;
640 fn += (mr->reg_width >> 3) - 1;
641 return _INTC_MK(fn, mode,
642 intc_get_reg(d, reg_e),
643 intc_get_reg(d, reg_d),
645 (mr->reg_width - 1) - *fld_idx);
655 static unsigned int __init intc_mask_data(struct intc_desc *desc,
656 struct intc_desc_int *d,
657 intc_enum enum_id, int do_grps)
663 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
668 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
673 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
674 struct intc_desc_int *d,
676 unsigned int *reg_idx,
677 unsigned int *fld_idx)
679 struct intc_prio_reg *pr = desc->hw.prio_regs;
680 unsigned int fn, n, mode, bit;
681 unsigned long reg_e, reg_d;
683 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
684 pr = desc->hw.prio_regs + *reg_idx;
686 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
687 if (pr->enum_ids[*fld_idx] != enum_id)
690 if (pr->set_reg && pr->clr_reg) {
691 fn = REG_FN_WRITE_BASE;
692 mode = MODE_PCLR_REG;
696 fn = REG_FN_MODIFY_BASE;
697 mode = MODE_PRIO_REG;
704 fn += (pr->reg_width >> 3) - 1;
707 BUG_ON(n * pr->field_width > pr->reg_width);
709 bit = pr->reg_width - (n * pr->field_width);
711 return _INTC_MK(fn, mode,
712 intc_get_reg(d, reg_e),
713 intc_get_reg(d, reg_d),
714 pr->field_width, bit);
724 static unsigned int __init intc_prio_data(struct intc_desc *desc,
725 struct intc_desc_int *d,
726 intc_enum enum_id, int do_grps)
732 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
737 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
742 static void __init intc_enable_disable_enum(struct intc_desc *desc,
743 struct intc_desc_int *d,
744 intc_enum enum_id, int enable)
746 unsigned int i, j, data;
748 /* go through and enable/disable all mask bits */
751 data = _intc_mask_data(desc, d, enum_id, &i, &j);
753 intc_enable_disable(d, data, enable);
757 /* go through and enable/disable all priority fields */
760 data = _intc_prio_data(desc, d, enum_id, &i, &j);
762 intc_enable_disable(d, data, enable);
768 static unsigned int __init intc_ack_data(struct intc_desc *desc,
769 struct intc_desc_int *d,
772 struct intc_mask_reg *mr = desc->hw.ack_regs;
773 unsigned int i, j, fn, mode;
774 unsigned long reg_e, reg_d;
776 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
777 mr = desc->hw.ack_regs + i;
779 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
780 if (mr->enum_ids[j] != enum_id)
783 fn = REG_FN_MODIFY_BASE;
784 mode = MODE_ENABLE_REG;
788 fn += (mr->reg_width >> 3) - 1;
789 return _INTC_MK(fn, mode,
790 intc_get_reg(d, reg_e),
791 intc_get_reg(d, reg_d),
793 (mr->reg_width - 1) - j);
800 static unsigned int __init intc_sense_data(struct intc_desc *desc,
801 struct intc_desc_int *d,
804 struct intc_sense_reg *sr = desc->hw.sense_regs;
805 unsigned int i, j, fn, bit;
807 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
808 sr = desc->hw.sense_regs + i;
810 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
811 if (sr->enum_ids[j] != enum_id)
814 fn = REG_FN_MODIFY_BASE;
815 fn += (sr->reg_width >> 3) - 1;
817 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
819 bit = sr->reg_width - ((j + 1) * sr->field_width);
821 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
822 0, sr->field_width, bit);
829 static void __init intc_register_irq(struct intc_desc *desc,
830 struct intc_desc_int *d,
834 struct intc_handle_int *hp;
835 unsigned int data[2], primary;
838 * Register the IRQ position with the global IRQ map
840 set_bit(irq, intc_irq_map);
843 * Prefer single interrupt source bitmap over other combinations:
845 * 1. bitmap, single interrupt source
846 * 2. priority, single interrupt source
847 * 3. bitmap, multiple interrupt sources (groups)
848 * 4. priority, multiple interrupt sources (groups)
850 data[0] = intc_mask_data(desc, d, enum_id, 0);
851 data[1] = intc_prio_data(desc, d, enum_id, 0);
854 if (!data[0] && data[1])
857 if (!data[0] && !data[1])
858 pr_warning("intc: missing unique irq mask for "
859 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
861 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
862 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
867 BUG_ON(!data[primary]); /* must have primary masking method */
869 disable_irq_nosync(irq);
870 set_irq_chip_and_handler_name(irq, &d->chip,
871 handle_level_irq, "level");
872 set_irq_chip_data(irq, (void *)data[primary]);
876 * - this needs to be at least 2 for 5-bit priorities on 7780
878 intc_prio_level[irq] = default_prio_level;
880 /* enable secondary masking method if present */
882 _intc_enable(irq, data[!primary]);
884 /* add irq to d->prio list if priority is available */
886 hp = d->prio + d->nr_prio;
888 hp->handle = data[1];
892 * only secondary priority should access registers, so
893 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
895 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
896 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
901 /* add irq to d->sense list if sense is available */
902 data[0] = intc_sense_data(desc, d, enum_id);
904 (d->sense + d->nr_sense)->irq = irq;
905 (d->sense + d->nr_sense)->handle = data[0];
909 /* irq should be disabled by default */
912 if (desc->hw.ack_regs)
913 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
915 #ifdef CONFIG_INTC_BALANCING
916 if (desc->hw.mask_regs)
917 dist_handle[irq] = intc_dist_data(desc, d, enum_id);
921 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
925 static unsigned int __init save_reg(struct intc_desc_int *d,
931 value = intc_phys_to_virt(d, value);
943 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
945 generic_handle_irq((unsigned int)get_irq_data(irq));
948 int __init register_intc_controller(struct intc_desc *desc)
950 unsigned int i, k, smp;
951 struct intc_hw_desc *hw = &desc->hw;
952 struct intc_desc_int *d;
953 struct resource *res;
955 pr_info("intc: Registered controller '%s' with %u IRQs\n",
956 desc->name, hw->nr_vectors);
958 d = kzalloc(sizeof(*d), GFP_NOWAIT);
962 INIT_LIST_HEAD(&d->list);
963 list_add(&d->list, &intc_list);
965 if (desc->num_resources) {
966 d->nr_windows = desc->num_resources;
967 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
972 for (k = 0; k < d->nr_windows; k++) {
973 res = desc->resource + k;
974 WARN_ON(resource_type(res) != IORESOURCE_MEM);
975 d->window[k].phys = res->start;
976 d->window[k].size = resource_size(res);
977 d->window[k].virt = ioremap_nocache(res->start,
979 if (!d->window[k].virt)
984 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
985 #ifdef CONFIG_INTC_BALANCING
987 d->nr_reg += hw->nr_mask_regs;
989 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
990 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
991 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
993 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
998 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
1004 if (hw->mask_regs) {
1005 for (i = 0; i < hw->nr_mask_regs; i++) {
1006 smp = IS_SMP(hw->mask_regs[i]);
1007 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
1008 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
1009 #ifdef CONFIG_INTC_BALANCING
1010 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
1015 if (hw->prio_regs) {
1016 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
1021 for (i = 0; i < hw->nr_prio_regs; i++) {
1022 smp = IS_SMP(hw->prio_regs[i]);
1023 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
1024 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
1028 if (hw->sense_regs) {
1029 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
1034 for (i = 0; i < hw->nr_sense_regs; i++)
1035 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
1038 d->chip.name = desc->name;
1039 d->chip.mask = intc_disable;
1040 d->chip.unmask = intc_enable;
1041 d->chip.mask_ack = intc_disable;
1042 d->chip.enable = intc_enable;
1043 d->chip.disable = intc_disable;
1044 d->chip.shutdown = intc_disable;
1045 d->chip.set_type = intc_set_sense;
1046 d->chip.set_wake = intc_set_wake;
1048 d->chip.set_affinity = intc_set_affinity;
1052 for (i = 0; i < hw->nr_ack_regs; i++)
1053 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
1055 d->chip.mask_ack = intc_mask_ack;
1058 /* disable bits matching force_disable before registering irqs */
1059 if (desc->force_disable)
1060 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
1062 /* disable bits matching force_enable before registering irqs */
1063 if (desc->force_enable)
1064 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
1066 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
1068 /* register the vectors one by one */
1069 for (i = 0; i < hw->nr_vectors; i++) {
1070 struct intc_vect *vect = hw->vectors + i;
1071 unsigned int irq = evt2irq(vect->vect);
1072 struct irq_desc *irq_desc;
1077 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
1078 if (unlikely(!irq_desc)) {
1079 pr_err("can't get irq_desc for %d\n", irq);
1083 intc_register_irq(desc, d, vect->enum_id, irq);
1085 for (k = i + 1; k < hw->nr_vectors; k++) {
1086 struct intc_vect *vect2 = hw->vectors + k;
1087 unsigned int irq2 = evt2irq(vect2->vect);
1089 if (vect->enum_id != vect2->enum_id)
1093 * In the case of multi-evt handling and sparse
1094 * IRQ support, each vector still needs to have
1095 * its own backing irq_desc.
1097 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
1098 if (unlikely(!irq_desc)) {
1099 pr_err("can't get irq_desc for %d\n", irq2);
1105 /* redirect this interrupts to the first one */
1106 set_irq_chip(irq2, &dummy_irq_chip);
1107 set_irq_chained_handler(irq2, intc_redirect_irq);
1108 set_irq_data(irq2, (void *)irq);
1112 /* enable bits matching force_enable after registering irqs */
1113 if (desc->force_enable)
1114 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
1126 for (k = 0; k < d->nr_windows; k++)
1127 if (d->window[k].virt)
1128 iounmap(d->window[k].virt);
1134 pr_err("unable to allocate INTC memory\n");
1139 #ifdef CONFIG_INTC_USERIMASK
1140 static void __iomem *uimask;
1142 int register_intc_userimask(unsigned long addr)
1144 if (unlikely(uimask))
1147 uimask = ioremap_nocache(addr, SZ_4K);
1148 if (unlikely(!uimask))
1151 pr_info("intc: userimask support registered for levels 0 -> %d\n",
1152 default_prio_level - 1);
1158 show_intc_userimask(struct sysdev_class *cls,
1159 struct sysdev_class_attribute *attr, char *buf)
1161 return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf);
1165 store_intc_userimask(struct sysdev_class *cls,
1166 struct sysdev_class_attribute *attr,
1167 const char *buf, size_t count)
1169 unsigned long level;
1171 level = simple_strtoul(buf, NULL, 10);
1174 * Minimal acceptable IRQ levels are in the 2 - 16 range, but
1175 * these are chomped so as to not interfere with normal IRQs.
1177 * Level 1 is a special case on some CPUs in that it's not
1178 * directly settable, but given that USERIMASK cuts off below a
1179 * certain level, we don't care about this limitation here.
1180 * Level 0 on the other hand equates to user masking disabled.
1182 * We use default_prio_level as a cut off so that only special
1183 * case opt-in IRQs can be mangled.
1185 if (level >= default_prio_level)
1188 __raw_writel(0xa5 << 24 | level << 4, uimask);
1193 static SYSDEV_CLASS_ATTR(userimask, S_IRUSR | S_IWUSR,
1194 show_intc_userimask, store_intc_userimask);
1198 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
1200 struct intc_desc_int *d;
1202 d = container_of(dev, struct intc_desc_int, sysdev);
1204 return sprintf(buf, "%s\n", d->chip.name);
1207 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
1209 static int intc_suspend(struct sys_device *dev, pm_message_t state)
1211 struct intc_desc_int *d;
1212 struct irq_desc *desc;
1215 /* get intc controller associated with this sysdev */
1216 d = container_of(dev, struct intc_desc_int, sysdev);
1218 switch (state.event) {
1220 if (d->state.event != PM_EVENT_FREEZE)
1222 for_each_irq_desc(irq, desc) {
1223 if (desc->handle_irq == intc_redirect_irq)
1225 if (desc->chip != &d->chip)
1227 if (desc->status & IRQ_DISABLED)
1233 case PM_EVENT_FREEZE:
1234 /* nothing has to be done */
1236 case PM_EVENT_SUSPEND:
1237 /* enable wakeup irqs belonging to this intc controller */
1238 for_each_irq_desc(irq, desc) {
1239 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
1249 static int intc_resume(struct sys_device *dev)
1251 return intc_suspend(dev, PMSG_ON);
1254 static struct sysdev_class intc_sysdev_class = {
1256 .suspend = intc_suspend,
1257 .resume = intc_resume,
1260 /* register this intc as sysdev to allow suspend/resume */
1261 static int __init register_intc_sysdevs(void)
1263 struct intc_desc_int *d;
1267 error = sysdev_class_register(&intc_sysdev_class);
1268 #ifdef CONFIG_INTC_USERIMASK
1269 if (!error && uimask)
1270 error = sysdev_class_create_file(&intc_sysdev_class,
1274 list_for_each_entry(d, &intc_list, list) {
1276 d->sysdev.cls = &intc_sysdev_class;
1277 error = sysdev_register(&d->sysdev);
1279 error = sysdev_create_file(&d->sysdev,
1289 pr_err("intc: sysdev registration error\n");
1293 device_initcall(register_intc_sysdevs);
1296 * Dynamic IRQ allocation and deallocation
1298 unsigned int create_irq_nr(unsigned int irq_want, int node)
1300 unsigned int irq = 0, new;
1301 unsigned long flags;
1302 struct irq_desc *desc;
1304 spin_lock_irqsave(&vector_lock, flags);
1307 * First try the wanted IRQ
1309 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1312 /* .. then fall back to scanning. */
1313 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1314 if (unlikely(new == nr_irqs))
1317 __set_bit(new, intc_irq_map);
1320 desc = irq_to_desc_alloc_node(new, node);
1321 if (unlikely(!desc)) {
1322 pr_err("can't get irq_desc for %d\n", new);
1326 desc = move_irq_desc(desc, node);
1330 spin_unlock_irqrestore(&vector_lock, flags);
1333 dynamic_irq_init(irq);
1335 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1342 int create_irq(void)
1344 int nid = cpu_to_node(smp_processor_id());
1347 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1354 void destroy_irq(unsigned int irq)
1356 unsigned long flags;
1358 dynamic_irq_cleanup(irq);
1360 spin_lock_irqsave(&vector_lock, flags);
1361 __clear_bit(irq, intc_irq_map);
1362 spin_unlock_irqrestore(&vector_lock, flags);
1365 int reserve_irq_vector(unsigned int irq)
1367 unsigned long flags;
1370 spin_lock_irqsave(&vector_lock, flags);
1371 if (test_and_set_bit(irq, intc_irq_map))
1373 spin_unlock_irqrestore(&vector_lock, flags);
1378 void reserve_irq_legacy(void)
1380 unsigned long flags;
1383 spin_lock_irqsave(&vector_lock, flags);
1384 j = find_first_bit(intc_irq_map, nr_irqs);
1385 for (i = 0; i < j; i++)
1386 __set_bit(i, intc_irq_map);
1387 spin_unlock_irqrestore(&vector_lock, flags);