2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28 #include <linux/bitmap.h>
30 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
31 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
32 ((addr_e) << 16) | ((addr_d << 24)))
34 #define _INTC_SHIFT(h) (h & 0x1f)
35 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
36 #define _INTC_FN(h) ((h >> 9) & 0xf)
37 #define _INTC_MODE(h) ((h >> 13) & 0x7)
38 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
39 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
41 struct intc_handle_int {
46 struct intc_desc_int {
47 struct list_head list;
48 struct sys_device sysdev;
55 struct intc_handle_int *prio;
57 struct intc_handle_int *sense;
58 unsigned int nr_sense;
62 static LIST_HEAD(intc_list);
65 * The intc_irq_map provides a global map of bound IRQ vectors for a
66 * given platform. Allocation of IRQs are either static through the CPU
67 * vector map, or dynamic in the case of board mux vectors or MSI.
69 * As this is a central point for all IRQ controllers on the system,
70 * each of the available sources are mapped out here. This combined with
71 * sparseirq makes it quite trivial to keep the vector map tightly packed
72 * when dynamically creating IRQs, as well as tying in to otherwise
73 * unused irq_desc positions in the sparse array.
75 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
76 static DEFINE_SPINLOCK(vector_lock);
79 #define IS_SMP(x) x.smp
80 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
81 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
84 #define INTC_REG(d, x, c) (d->reg[(x)])
85 #define SMP_NR(d, x) 1
88 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
89 static unsigned long ack_handle[NR_IRQS];
91 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
93 struct irq_chip *chip = get_irq_chip(irq);
94 return container_of(chip, struct intc_desc_int, chip);
97 static inline unsigned int set_field(unsigned int value,
98 unsigned int field_value,
101 unsigned int width = _INTC_WIDTH(handle);
102 unsigned int shift = _INTC_SHIFT(handle);
104 value &= ~(((1 << width) - 1) << shift);
105 value |= field_value << shift;
109 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
111 __raw_writeb(set_field(0, data, h), addr);
112 (void)__raw_readb(addr); /* Defeat write posting */
115 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
117 __raw_writew(set_field(0, data, h), addr);
118 (void)__raw_readw(addr); /* Defeat write posting */
121 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
123 __raw_writel(set_field(0, data, h), addr);
124 (void)__raw_readl(addr); /* Defeat write posting */
127 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
130 local_irq_save(flags);
131 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
132 (void)__raw_readb(addr); /* Defeat write posting */
133 local_irq_restore(flags);
136 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
139 local_irq_save(flags);
140 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
141 (void)__raw_readw(addr); /* Defeat write posting */
142 local_irq_restore(flags);
145 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
148 local_irq_save(flags);
149 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
150 (void)__raw_readl(addr); /* Defeat write posting */
151 local_irq_restore(flags);
154 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
156 static void (*intc_reg_fns[])(unsigned long addr,
158 unsigned long data) = {
159 [REG_FN_WRITE_BASE + 0] = write_8,
160 [REG_FN_WRITE_BASE + 1] = write_16,
161 [REG_FN_WRITE_BASE + 3] = write_32,
162 [REG_FN_MODIFY_BASE + 0] = modify_8,
163 [REG_FN_MODIFY_BASE + 1] = modify_16,
164 [REG_FN_MODIFY_BASE + 3] = modify_32,
167 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
168 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
169 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
170 MODE_PRIO_REG, /* Priority value written to enable interrupt */
171 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
174 static void intc_mode_field(unsigned long addr,
175 unsigned long handle,
176 void (*fn)(unsigned long,
181 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
184 static void intc_mode_zero(unsigned long addr,
185 unsigned long handle,
186 void (*fn)(unsigned long,
194 static void intc_mode_prio(unsigned long addr,
195 unsigned long handle,
196 void (*fn)(unsigned long,
201 fn(addr, handle, intc_prio_level[irq]);
204 static void (*intc_enable_fns[])(unsigned long addr,
205 unsigned long handle,
206 void (*fn)(unsigned long,
209 unsigned int irq) = {
210 [MODE_ENABLE_REG] = intc_mode_field,
211 [MODE_MASK_REG] = intc_mode_zero,
212 [MODE_DUAL_REG] = intc_mode_field,
213 [MODE_PRIO_REG] = intc_mode_prio,
214 [MODE_PCLR_REG] = intc_mode_prio,
217 static void (*intc_disable_fns[])(unsigned long addr,
218 unsigned long handle,
219 void (*fn)(unsigned long,
222 unsigned int irq) = {
223 [MODE_ENABLE_REG] = intc_mode_zero,
224 [MODE_MASK_REG] = intc_mode_field,
225 [MODE_DUAL_REG] = intc_mode_field,
226 [MODE_PRIO_REG] = intc_mode_zero,
227 [MODE_PCLR_REG] = intc_mode_field,
230 static inline void _intc_enable(unsigned int irq, unsigned long handle)
232 struct intc_desc_int *d = get_intc_desc(irq);
236 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
237 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
238 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
239 [_INTC_FN(handle)], irq);
243 static void intc_enable(unsigned int irq)
245 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
248 static void intc_disable(unsigned int irq)
250 struct intc_desc_int *d = get_intc_desc(irq);
251 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
255 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
256 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
257 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
258 [_INTC_FN(handle)], irq);
262 static void (*intc_enable_noprio_fns[])(unsigned long addr,
263 unsigned long handle,
264 void (*fn)(unsigned long,
267 unsigned int irq) = {
268 [MODE_ENABLE_REG] = intc_mode_field,
269 [MODE_MASK_REG] = intc_mode_zero,
270 [MODE_DUAL_REG] = intc_mode_field,
271 [MODE_PRIO_REG] = intc_mode_field,
272 [MODE_PCLR_REG] = intc_mode_field,
275 static void intc_enable_disable(struct intc_desc_int *d,
276 unsigned long handle, int do_enable)
280 void (*fn)(unsigned long, unsigned long,
281 void (*)(unsigned long, unsigned long, unsigned long),
285 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
286 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
287 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
288 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
291 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
292 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
293 fn = intc_disable_fns[_INTC_MODE(handle)];
294 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
299 static int intc_set_wake(unsigned int irq, unsigned int on)
301 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
304 static void intc_mask_ack(unsigned int irq)
306 struct intc_desc_int *d = get_intc_desc(irq);
307 unsigned long handle = ack_handle[irq];
312 /* read register and write zero only to the assocaited bit */
315 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
316 switch (_INTC_FN(handle)) {
317 case REG_FN_MODIFY_BASE + 0: /* 8bit */
319 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
321 case REG_FN_MODIFY_BASE + 1: /* 16bit */
323 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
325 case REG_FN_MODIFY_BASE + 3: /* 32bit */
327 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
336 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
342 /* this doesn't scale well, but...
344 * this function should only be used for cerain uncommon
345 * operations such as intc_set_priority() and intc_set_sense()
346 * and in those rare cases performance doesn't matter that much.
347 * keeping the memory footprint low is more important.
349 * one rather simple way to speed this up and still keep the
350 * memory footprint down is to make sure the array is sorted
351 * and then perform a bisect to lookup the irq.
354 for (i = 0; i < nr_hp; i++) {
355 if ((hp + i)->irq != irq)
364 int intc_set_priority(unsigned int irq, unsigned int prio)
366 struct intc_desc_int *d = get_intc_desc(irq);
367 struct intc_handle_int *ihp;
369 if (!intc_prio_level[irq] || prio <= 1)
372 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
374 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
377 intc_prio_level[irq] = prio;
380 * only set secondary masking method directly
381 * primary masking method is using intc_prio_level[irq]
382 * priority level will be set during next enable()
385 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
386 _intc_enable(irq, ihp->handle);
391 #define VALID(x) (x | 0x80)
393 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
394 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
395 [IRQ_TYPE_EDGE_RISING] = VALID(1),
396 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
397 /* SH7706, SH7707 and SH7709 do not support high level triggered */
398 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
399 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
400 !defined(CONFIG_CPU_SUBTYPE_SH7709)
401 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
405 static int intc_set_sense(unsigned int irq, unsigned int type)
407 struct intc_desc_int *d = get_intc_desc(irq);
408 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
409 struct intc_handle_int *ihp;
415 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
417 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
418 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
423 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
424 unsigned long address)
428 for (k = 0; k < d->nr_reg; k++) {
429 if (d->reg[k] == address)
437 static intc_enum __init intc_grp_id(struct intc_desc *desc,
440 struct intc_group *g = desc->hw.groups;
443 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
444 g = desc->hw.groups + i;
446 for (j = 0; g->enum_ids[j]; j++) {
447 if (g->enum_ids[j] != enum_id)
457 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
458 struct intc_desc_int *d,
460 unsigned int *reg_idx,
461 unsigned int *fld_idx)
463 struct intc_mask_reg *mr = desc->hw.mask_regs;
464 unsigned int fn, mode;
465 unsigned long reg_e, reg_d;
467 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
468 mr = desc->hw.mask_regs + *reg_idx;
470 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
471 if (mr->enum_ids[*fld_idx] != enum_id)
474 if (mr->set_reg && mr->clr_reg) {
475 fn = REG_FN_WRITE_BASE;
476 mode = MODE_DUAL_REG;
480 fn = REG_FN_MODIFY_BASE;
482 mode = MODE_ENABLE_REG;
486 mode = MODE_MASK_REG;
492 fn += (mr->reg_width >> 3) - 1;
493 return _INTC_MK(fn, mode,
494 intc_get_reg(d, reg_e),
495 intc_get_reg(d, reg_d),
497 (mr->reg_width - 1) - *fld_idx);
507 static unsigned int __init intc_mask_data(struct intc_desc *desc,
508 struct intc_desc_int *d,
509 intc_enum enum_id, int do_grps)
515 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
520 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
525 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
526 struct intc_desc_int *d,
528 unsigned int *reg_idx,
529 unsigned int *fld_idx)
531 struct intc_prio_reg *pr = desc->hw.prio_regs;
532 unsigned int fn, n, mode, bit;
533 unsigned long reg_e, reg_d;
535 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
536 pr = desc->hw.prio_regs + *reg_idx;
538 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
539 if (pr->enum_ids[*fld_idx] != enum_id)
542 if (pr->set_reg && pr->clr_reg) {
543 fn = REG_FN_WRITE_BASE;
544 mode = MODE_PCLR_REG;
548 fn = REG_FN_MODIFY_BASE;
549 mode = MODE_PRIO_REG;
556 fn += (pr->reg_width >> 3) - 1;
559 BUG_ON(n * pr->field_width > pr->reg_width);
561 bit = pr->reg_width - (n * pr->field_width);
563 return _INTC_MK(fn, mode,
564 intc_get_reg(d, reg_e),
565 intc_get_reg(d, reg_d),
566 pr->field_width, bit);
576 static unsigned int __init intc_prio_data(struct intc_desc *desc,
577 struct intc_desc_int *d,
578 intc_enum enum_id, int do_grps)
584 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
589 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
594 static void __init intc_enable_disable_enum(struct intc_desc *desc,
595 struct intc_desc_int *d,
596 intc_enum enum_id, int enable)
598 unsigned int i, j, data;
600 /* go through and enable/disable all mask bits */
603 data = _intc_mask_data(desc, d, enum_id, &i, &j);
605 intc_enable_disable(d, data, enable);
609 /* go through and enable/disable all priority fields */
612 data = _intc_prio_data(desc, d, enum_id, &i, &j);
614 intc_enable_disable(d, data, enable);
620 static unsigned int __init intc_ack_data(struct intc_desc *desc,
621 struct intc_desc_int *d,
624 struct intc_mask_reg *mr = desc->hw.ack_regs;
625 unsigned int i, j, fn, mode;
626 unsigned long reg_e, reg_d;
628 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
629 mr = desc->hw.ack_regs + i;
631 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
632 if (mr->enum_ids[j] != enum_id)
635 fn = REG_FN_MODIFY_BASE;
636 mode = MODE_ENABLE_REG;
640 fn += (mr->reg_width >> 3) - 1;
641 return _INTC_MK(fn, mode,
642 intc_get_reg(d, reg_e),
643 intc_get_reg(d, reg_d),
645 (mr->reg_width - 1) - j);
652 static unsigned int __init intc_sense_data(struct intc_desc *desc,
653 struct intc_desc_int *d,
656 struct intc_sense_reg *sr = desc->hw.sense_regs;
657 unsigned int i, j, fn, bit;
659 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
660 sr = desc->hw.sense_regs + i;
662 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
663 if (sr->enum_ids[j] != enum_id)
666 fn = REG_FN_MODIFY_BASE;
667 fn += (sr->reg_width >> 3) - 1;
669 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
671 bit = sr->reg_width - ((j + 1) * sr->field_width);
673 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
674 0, sr->field_width, bit);
681 static void __init intc_register_irq(struct intc_desc *desc,
682 struct intc_desc_int *d,
686 struct intc_handle_int *hp;
687 unsigned int data[2], primary;
690 * Register the IRQ position with the global IRQ map
692 set_bit(irq, intc_irq_map);
694 /* Prefer single interrupt source bitmap over other combinations:
695 * 1. bitmap, single interrupt source
696 * 2. priority, single interrupt source
697 * 3. bitmap, multiple interrupt sources (groups)
698 * 4. priority, multiple interrupt sources (groups)
701 data[0] = intc_mask_data(desc, d, enum_id, 0);
702 data[1] = intc_prio_data(desc, d, enum_id, 0);
705 if (!data[0] && data[1])
708 if (!data[0] && !data[1])
709 pr_warning("intc: missing unique irq mask for "
710 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
712 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
713 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
718 BUG_ON(!data[primary]); /* must have primary masking method */
720 disable_irq_nosync(irq);
721 set_irq_chip_and_handler_name(irq, &d->chip,
722 handle_level_irq, "level");
723 set_irq_chip_data(irq, (void *)data[primary]);
725 /* set priority level
726 * - this needs to be at least 2 for 5-bit priorities on 7780
728 intc_prio_level[irq] = 2;
730 /* enable secondary masking method if present */
732 _intc_enable(irq, data[!primary]);
734 /* add irq to d->prio list if priority is available */
736 hp = d->prio + d->nr_prio;
738 hp->handle = data[1];
742 * only secondary priority should access registers, so
743 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
746 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
747 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
752 /* add irq to d->sense list if sense is available */
753 data[0] = intc_sense_data(desc, d, enum_id);
755 (d->sense + d->nr_sense)->irq = irq;
756 (d->sense + d->nr_sense)->handle = data[0];
760 /* irq should be disabled by default */
763 if (desc->hw.ack_regs)
764 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
767 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
771 static unsigned int __init save_reg(struct intc_desc_int *d,
787 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
789 generic_handle_irq((unsigned int)get_irq_data(irq));
792 int __init register_intc_controller(struct intc_desc *desc)
794 unsigned int i, k, smp;
795 struct intc_hw_desc *hw = &desc->hw;
796 struct intc_desc_int *d;
798 d = kzalloc(sizeof(*d), GFP_NOWAIT);
802 INIT_LIST_HEAD(&d->list);
803 list_add(&d->list, &intc_list);
805 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
806 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
807 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
808 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
810 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
815 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
822 for (i = 0; i < hw->nr_mask_regs; i++) {
823 smp = IS_SMP(hw->mask_regs[i]);
824 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
825 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
830 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
835 for (i = 0; i < hw->nr_prio_regs; i++) {
836 smp = IS_SMP(hw->prio_regs[i]);
837 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
838 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
842 if (hw->sense_regs) {
843 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
848 for (i = 0; i < hw->nr_sense_regs; i++)
849 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
852 d->chip.name = desc->name;
853 d->chip.mask = intc_disable;
854 d->chip.unmask = intc_enable;
855 d->chip.mask_ack = intc_disable;
856 d->chip.enable = intc_enable;
857 d->chip.disable = intc_disable;
858 d->chip.shutdown = intc_disable;
859 d->chip.set_type = intc_set_sense;
860 d->chip.set_wake = intc_set_wake;
863 for (i = 0; i < hw->nr_ack_regs; i++)
864 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
866 d->chip.mask_ack = intc_mask_ack;
869 /* disable bits matching force_disable before registering irqs */
870 if (desc->force_disable)
871 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
873 /* disable bits matching force_enable before registering irqs */
874 if (desc->force_enable)
875 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
877 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
879 /* register the vectors one by one */
880 for (i = 0; i < hw->nr_vectors; i++) {
881 struct intc_vect *vect = hw->vectors + i;
882 unsigned int irq = evt2irq(vect->vect);
883 struct irq_desc *irq_desc;
888 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
889 if (unlikely(!irq_desc)) {
890 pr_info("can't get irq_desc for %d\n", irq);
894 intc_register_irq(desc, d, vect->enum_id, irq);
896 for (k = i + 1; k < hw->nr_vectors; k++) {
897 struct intc_vect *vect2 = hw->vectors + k;
898 unsigned int irq2 = evt2irq(vect2->vect);
900 if (vect->enum_id != vect2->enum_id)
904 * In the case of multi-evt handling and sparse
905 * IRQ support, each vector still needs to have
906 * its own backing irq_desc.
908 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
909 if (unlikely(!irq_desc)) {
910 pr_info("can't get irq_desc for %d\n", irq2);
916 /* redirect this interrupts to the first one */
917 set_irq_chip(irq2, &dummy_irq_chip);
918 set_irq_chained_handler(irq2, intc_redirect_irq);
919 set_irq_data(irq2, (void *)irq);
923 /* enable bits matching force_enable after registering irqs */
924 if (desc->force_enable)
925 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
939 pr_err("unable to allocate INTC memory\n");
944 static int intc_suspend(struct sys_device *dev, pm_message_t state)
946 struct intc_desc_int *d;
947 struct irq_desc *desc;
950 /* get intc controller associated with this sysdev */
951 d = container_of(dev, struct intc_desc_int, sysdev);
953 switch (state.event) {
955 if (d->state.event != PM_EVENT_FREEZE)
957 for_each_irq_desc(irq, desc) {
958 if (desc->handle_irq == intc_redirect_irq)
960 if (desc->chip != &d->chip)
962 if (desc->status & IRQ_DISABLED)
968 case PM_EVENT_FREEZE:
969 /* nothing has to be done */
971 case PM_EVENT_SUSPEND:
972 /* enable wakeup irqs belonging to this intc controller */
973 for_each_irq_desc(irq, desc) {
974 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
984 static int intc_resume(struct sys_device *dev)
986 return intc_suspend(dev, PMSG_ON);
989 static struct sysdev_class intc_sysdev_class = {
991 .suspend = intc_suspend,
992 .resume = intc_resume,
995 /* register this intc as sysdev to allow suspend/resume */
996 static int __init register_intc_sysdevs(void)
998 struct intc_desc_int *d;
1002 error = sysdev_class_register(&intc_sysdev_class);
1004 list_for_each_entry(d, &intc_list, list) {
1006 d->sysdev.cls = &intc_sysdev_class;
1007 error = sysdev_register(&d->sysdev);
1015 pr_warning("intc: sysdev registration error\n");
1019 device_initcall(register_intc_sysdevs);
1022 * Dynamic IRQ allocation and deallocation
1024 unsigned int create_irq_nr(unsigned int irq_want, int node)
1026 unsigned int irq = 0, new;
1027 unsigned long flags;
1028 struct irq_desc *desc;
1030 spin_lock_irqsave(&vector_lock, flags);
1033 * First try the wanted IRQ
1035 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1038 /* .. then fall back to scanning. */
1039 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1040 if (unlikely(new == nr_irqs))
1043 __set_bit(new, intc_irq_map);
1046 desc = irq_to_desc_alloc_node(new, node);
1047 if (unlikely(!desc)) {
1048 pr_info("can't get irq_desc for %d\n", new);
1052 desc = move_irq_desc(desc, node);
1056 spin_unlock_irqrestore(&vector_lock, flags);
1059 dynamic_irq_init(irq);
1061 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1068 int create_irq(void)
1070 int nid = cpu_to_node(smp_processor_id());
1073 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1080 void destroy_irq(unsigned int irq)
1082 unsigned long flags;
1084 dynamic_irq_cleanup(irq);
1086 spin_lock_irqsave(&vector_lock, flags);
1087 __clear_bit(irq, intc_irq_map);
1088 spin_unlock_irqrestore(&vector_lock, flags);
1091 int reserve_irq_vector(unsigned int irq)
1093 unsigned long flags;
1096 spin_lock_irqsave(&vector_lock, flags);
1097 if (test_and_set_bit(irq, intc_irq_map))
1099 spin_unlock_irqrestore(&vector_lock, flags);
1104 void reserve_irq_legacy(void)
1106 unsigned long flags;
1109 spin_lock_irqsave(&vector_lock, flags);
1110 j = find_first_bit(intc_irq_map, nr_irqs);
1111 for (i = 0; i < j; i++)
1112 __set_bit(i, intc_irq_map);
1113 spin_unlock_irqrestore(&vector_lock, flags);