2 * SuperH Pin Function Controller support.
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/sh_pfc.h>
16 #include <linux/module.h>
17 #include <linux/err.h>
19 #include <linux/bitops.h>
20 #include <linux/slab.h>
21 #include <linux/ioport.h>
23 static struct sh_pfc *sh_pfc __read_mostly;
25 static inline bool sh_pfc_initialized(void)
30 static void pfc_iounmap(struct sh_pfc *pfc)
34 for (k = 0; k < pfc->num_resources; k++)
35 if (pfc->window[k].virt)
36 iounmap(pfc->window[k].virt);
42 static int pfc_ioremap(struct sh_pfc *pfc)
47 if (!pfc->num_resources)
50 pfc->window = kzalloc(pfc->num_resources * sizeof(*pfc->window),
55 for (k = 0; k < pfc->num_resources; k++) {
56 res = pfc->resource + k;
57 WARN_ON(resource_type(res) != IORESOURCE_MEM);
58 pfc->window[k].phys = res->start;
59 pfc->window[k].size = resource_size(res);
60 pfc->window[k].virt = ioremap_nocache(res->start,
62 if (!pfc->window[k].virt)
74 static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
75 unsigned long address)
77 struct pfc_window *window;
80 /* scan through physical windows and convert address */
81 for (k = 0; k < pfc->num_resources; k++) {
82 window = pfc->window + k;
84 if (address < window->phys)
87 if (address >= (window->phys + window->size))
90 return window->virt + (address - window->phys);
93 /* no windows defined, register must be 1:1 mapped virt:phys */
94 return (void __iomem *)address;
97 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
99 if (enum_id < r->begin)
102 if (enum_id > r->end)
108 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
109 unsigned long reg_width)
113 return ioread8(mapped_reg);
115 return ioread16(mapped_reg);
117 return ioread32(mapped_reg);
124 static void gpio_write_raw_reg(void __iomem *mapped_reg,
125 unsigned long reg_width,
130 iowrite8(data, mapped_reg);
133 iowrite16(data, mapped_reg);
136 iowrite32(data, mapped_reg);
143 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
147 pos = dr->reg_width - (in_pos + 1);
149 pr_debug("read_bit: addr = %lx, pos = %ld, "
150 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
152 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
154 EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
156 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
161 pos = dr->reg_width - (in_pos + 1);
163 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
165 dr->reg, !!value, pos, dr->reg_width);
168 set_bit(pos, &dr->reg_shadow);
170 clear_bit(pos, &dr->reg_shadow);
172 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
174 EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
176 static void config_reg_helper(struct sh_pfc *pfc,
177 struct pinmux_cfg_reg *crp,
178 unsigned long in_pos,
179 void __iomem **mapped_regp,
180 unsigned long *maskp,
185 *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
187 if (crp->field_width) {
188 *maskp = (1 << crp->field_width) - 1;
189 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
191 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
192 *posp = crp->reg_width;
193 for (k = 0; k <= in_pos; k++)
194 *posp -= crp->var_field_width[k];
198 static int read_config_reg(struct sh_pfc *pfc,
199 struct pinmux_cfg_reg *crp,
202 void __iomem *mapped_reg;
203 unsigned long mask, pos;
205 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
207 pr_debug("read_reg: addr = %lx, field = %ld, "
208 "r_width = %ld, f_width = %ld\n",
209 crp->reg, field, crp->reg_width, crp->field_width);
211 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
214 static void write_config_reg(struct sh_pfc *pfc,
215 struct pinmux_cfg_reg *crp,
216 unsigned long field, unsigned long value)
218 void __iomem *mapped_reg;
219 unsigned long mask, pos, data;
221 config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
223 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
224 "r_width = %ld, f_width = %ld\n",
225 crp->reg, value, field, crp->reg_width, crp->field_width);
227 mask = ~(mask << pos);
228 value = value << pos;
230 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
235 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->unlock_reg),
238 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
241 static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
243 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
244 struct pinmux_data_reg *data_reg;
247 if (!enum_in_range(gpiop->enum_id, &pfc->data))
252 data_reg = pfc->data_regs + k;
254 if (!data_reg->reg_width)
257 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
259 for (n = 0; n < data_reg->reg_width; n++) {
260 if (data_reg->enum_ids[n] == gpiop->enum_id) {
261 gpiop->flags &= ~PINMUX_FLAG_DREG;
262 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
263 gpiop->flags &= ~PINMUX_FLAG_DBIT;
264 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
276 static void setup_data_regs(struct sh_pfc *pfc)
278 struct pinmux_data_reg *drp;
281 for (k = pfc->first_gpio; k <= pfc->last_gpio; k++)
282 setup_data_reg(pfc, k);
286 drp = pfc->data_regs + k;
291 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
297 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
298 struct pinmux_data_reg **drp, int *bitp)
300 struct pinmux_gpio *gpiop = &pfc->gpios[gpio];
303 if (!enum_in_range(gpiop->enum_id, &pfc->data))
306 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
307 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
308 *drp = pfc->data_regs + k;
312 EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
314 static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
315 struct pinmux_cfg_reg **crp,
316 int *fieldp, int *valuep,
317 unsigned long **cntp)
319 struct pinmux_cfg_reg *config_reg;
320 unsigned long r_width, f_width, curr_width, ncomb;
321 int k, m, n, pos, bit_pos;
325 config_reg = pfc->cfg_regs + k;
327 r_width = config_reg->reg_width;
328 f_width = config_reg->field_width;
335 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
337 curr_width = f_width;
339 curr_width = config_reg->var_field_width[m];
341 ncomb = 1 << curr_width;
342 for (n = 0; n < ncomb; n++) {
343 if (config_reg->enum_ids[pos + n] == enum_id) {
347 *cntp = &config_reg->cnt[m];
360 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
361 pinmux_enum_t *enum_idp)
363 pinmux_enum_t enum_id = pfc->gpios[gpio].enum_id;
364 pinmux_enum_t *data = pfc->gpio_data;
367 if (!enum_in_range(enum_id, &pfc->data)) {
368 if (!enum_in_range(enum_id, &pfc->mark)) {
369 pr_err("non data/mark enum_id for gpio %d\n", gpio);
375 *enum_idp = data[pos + 1];
379 for (k = 0; k < pfc->gpio_data_size; k++) {
380 if (data[k] == enum_id) {
381 *enum_idp = data[k + 1];
386 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
389 EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
391 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
394 struct pinmux_cfg_reg *cr = NULL;
395 pinmux_enum_t enum_id;
396 struct pinmux_range *range;
397 int in_range, pos, field, value;
400 switch (pinmux_type) {
402 case PINMUX_TYPE_FUNCTION:
406 case PINMUX_TYPE_OUTPUT:
407 range = &pfc->output;
410 case PINMUX_TYPE_INPUT:
414 case PINMUX_TYPE_INPUT_PULLUP:
415 range = &pfc->input_pu;
418 case PINMUX_TYPE_INPUT_PULLDOWN:
419 range = &pfc->input_pd;
431 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
438 /* first check if this is a function enum */
439 in_range = enum_in_range(enum_id, &pfc->function);
441 /* not a function enum */
444 * other range exists, so this pin is
445 * a regular GPIO pin that now is being
446 * bound to a specific direction.
448 * for this case we only allow function enums
449 * and the enums that match the other range.
451 in_range = enum_in_range(enum_id, range);
454 * special case pass through for fixed
455 * input-only or output-only pins without
456 * function enum register association.
458 if (in_range && enum_id == range->force)
462 * no other range exists, so this pin
463 * must then be of the function type.
465 * allow function type pins to select
466 * any combination of function/in/out
467 * in their MARK lists.
476 if (get_config_reg(pfc, enum_id, &cr,
477 &field, &value, &cntp) != 0)
481 case GPIO_CFG_DRYRUN:
483 (read_config_reg(pfc, cr, field) != value))
488 write_config_reg(pfc, cr, field, value);
502 EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
504 int sh_pfc_set_direction(struct sh_pfc *pfc, unsigned gpio,
513 pinmux_type = pfc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
515 switch (pinmux_type) {
516 case PINMUX_TYPE_GPIO:
518 case PINMUX_TYPE_OUTPUT:
519 case PINMUX_TYPE_INPUT:
520 case PINMUX_TYPE_INPUT_PULLUP:
521 case PINMUX_TYPE_INPUT_PULLDOWN:
522 sh_pfc_config_gpio(pfc, gpio, pinmux_type, GPIO_CFG_FREE);
528 if (sh_pfc_config_gpio(pfc, gpio,
530 GPIO_CFG_DRYRUN) != 0)
533 if (sh_pfc_config_gpio(pfc, gpio,
538 pfc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
539 pfc->gpios[gpio].flags |= new_pinmux_type;
545 EXPORT_SYMBOL_GPL(sh_pfc_set_direction);
547 int register_sh_pfc(struct sh_pfc *pfc)
549 int (*initroutine)(struct sh_pfc *) = NULL;
553 * Ensure that the type encoding fits
555 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
560 ret = pfc_ioremap(pfc);
561 if (unlikely(ret < 0))
564 spin_lock_init(&pfc->lock);
566 setup_data_regs(pfc);
569 pr_info("%s support registered\n", pfc->name);
571 initroutine = symbol_request(sh_pfc_register_gpiochip);
574 symbol_put_addr(initroutine);