2 * Pinmuxed GPIO support for SuperH.
4 * Copyright (C) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <linux/irq.h>
20 #include <linux/bitops.h>
21 #include <linux/gpio.h>
22 #include <linux/slab.h>
23 #include <linux/ioport.h>
25 static void pfc_iounmap(struct pinmux_info *pip)
29 for (k = 0; k < pip->num_resources; k++)
30 if (pip->window[k].virt)
31 iounmap(pip->window[k].virt);
37 static int pfc_ioremap(struct pinmux_info *pip)
42 if (!pip->num_resources)
45 pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
50 for (k = 0; k < pip->num_resources; k++) {
51 res = pip->resource + k;
52 WARN_ON(resource_type(res) != IORESOURCE_MEM);
53 pip->window[k].phys = res->start;
54 pip->window[k].size = resource_size(res);
55 pip->window[k].virt = ioremap_nocache(res->start,
57 if (!pip->window[k].virt)
69 static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
70 unsigned long address)
72 struct pfc_window *window;
75 /* scan through physical windows and convert address */
76 for (k = 0; k < pip->num_resources; k++) {
77 window = pip->window + k;
79 if (address < window->phys)
82 if (address >= (window->phys + window->size))
85 return window->virt + (address - window->phys);
88 /* no windows defined, register must be 1:1 mapped virt:phys */
89 return (void __iomem *)address;
92 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
94 if (enum_id < r->begin)
103 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
104 unsigned long reg_width)
108 return ioread8(mapped_reg);
110 return ioread16(mapped_reg);
112 return ioread32(mapped_reg);
119 static void gpio_write_raw_reg(void __iomem *mapped_reg,
120 unsigned long reg_width,
125 iowrite8(data, mapped_reg);
128 iowrite16(data, mapped_reg);
131 iowrite32(data, mapped_reg);
138 static int gpio_read_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos)
143 pos = dr->reg_width - (in_pos + 1);
145 pr_debug("read_bit: addr = %lx, pos = %ld, "
146 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
148 return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
151 static void gpio_write_bit(struct pinmux_data_reg *dr,
152 unsigned long in_pos, unsigned long value)
156 pos = dr->reg_width - (in_pos + 1);
158 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
160 dr->reg, !!value, pos, dr->reg_width);
163 set_bit(pos, &dr->reg_shadow);
165 clear_bit(pos, &dr->reg_shadow);
167 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
170 static void config_reg_helper(struct pinmux_info *gpioc,
171 struct pinmux_cfg_reg *crp,
172 unsigned long in_pos,
173 void __iomem **mapped_regp,
174 unsigned long *maskp,
179 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
181 if (crp->field_width) {
182 *maskp = (1 << crp->field_width) - 1;
183 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
185 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
186 *posp = crp->reg_width;
187 for (k = 0; k <= in_pos; k++)
188 *posp -= crp->var_field_width[k];
192 static int read_config_reg(struct pinmux_info *gpioc,
193 struct pinmux_cfg_reg *crp,
196 void __iomem *mapped_reg;
197 unsigned long mask, pos;
199 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
201 pr_debug("read_reg: addr = %lx, field = %ld, "
202 "r_width = %ld, f_width = %ld\n",
203 crp->reg, field, crp->reg_width, crp->field_width);
205 return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
208 static void write_config_reg(struct pinmux_info *gpioc,
209 struct pinmux_cfg_reg *crp,
210 unsigned long field, unsigned long value)
212 void __iomem *mapped_reg;
213 unsigned long mask, pos, data;
215 config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
217 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
218 "r_width = %ld, f_width = %ld\n",
219 crp->reg, value, field, crp->reg_width, crp->field_width);
221 mask = ~(mask << pos);
222 value = value << pos;
224 data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
228 if (gpioc->unlock_reg)
229 gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
232 gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
235 static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
237 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
238 struct pinmux_data_reg *data_reg;
241 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
246 data_reg = gpioc->data_regs + k;
248 if (!data_reg->reg_width)
251 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
253 for (n = 0; n < data_reg->reg_width; n++) {
254 if (data_reg->enum_ids[n] == gpiop->enum_id) {
255 gpiop->flags &= ~PINMUX_FLAG_DREG;
256 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
257 gpiop->flags &= ~PINMUX_FLAG_DBIT;
258 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
270 static void setup_data_regs(struct pinmux_info *gpioc)
272 struct pinmux_data_reg *drp;
275 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
276 setup_data_reg(gpioc, k);
280 drp = gpioc->data_regs + k;
285 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
291 static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
292 struct pinmux_data_reg **drp, int *bitp)
294 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
297 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
300 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
301 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
302 *drp = gpioc->data_regs + k;
307 static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
308 struct pinmux_cfg_reg **crp,
309 int *fieldp, int *valuep,
310 unsigned long **cntp)
312 struct pinmux_cfg_reg *config_reg;
313 unsigned long r_width, f_width, curr_width, ncomb;
314 int k, m, n, pos, bit_pos;
318 config_reg = gpioc->cfg_regs + k;
320 r_width = config_reg->reg_width;
321 f_width = config_reg->field_width;
328 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
330 curr_width = f_width;
332 curr_width = config_reg->var_field_width[m];
334 ncomb = 1 << curr_width;
335 for (n = 0; n < ncomb; n++) {
336 if (config_reg->enum_ids[pos + n] == enum_id) {
340 *cntp = &config_reg->cnt[m];
353 static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
354 int pos, pinmux_enum_t *enum_idp)
356 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
357 pinmux_enum_t *data = gpioc->gpio_data;
360 if (!enum_in_range(enum_id, &gpioc->data)) {
361 if (!enum_in_range(enum_id, &gpioc->mark)) {
362 pr_err("non data/mark enum_id for gpio %d\n", gpio);
368 *enum_idp = data[pos + 1];
372 for (k = 0; k < gpioc->gpio_data_size; k++) {
373 if (data[k] == enum_id) {
374 *enum_idp = data[k + 1];
379 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
383 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
385 static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
386 int pinmux_type, int cfg_mode)
388 struct pinmux_cfg_reg *cr = NULL;
389 pinmux_enum_t enum_id;
390 struct pinmux_range *range;
391 int in_range, pos, field, value;
394 switch (pinmux_type) {
396 case PINMUX_TYPE_FUNCTION:
400 case PINMUX_TYPE_OUTPUT:
401 range = &gpioc->output;
404 case PINMUX_TYPE_INPUT:
405 range = &gpioc->input;
408 case PINMUX_TYPE_INPUT_PULLUP:
409 range = &gpioc->input_pu;
412 case PINMUX_TYPE_INPUT_PULLDOWN:
413 range = &gpioc->input_pd;
425 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
432 /* first check if this is a function enum */
433 in_range = enum_in_range(enum_id, &gpioc->function);
435 /* not a function enum */
438 * other range exists, so this pin is
439 * a regular GPIO pin that now is being
440 * bound to a specific direction.
442 * for this case we only allow function enums
443 * and the enums that match the other range.
445 in_range = enum_in_range(enum_id, range);
448 * special case pass through for fixed
449 * input-only or output-only pins without
450 * function enum register association.
452 if (in_range && enum_id == range->force)
456 * no other range exists, so this pin
457 * must then be of the function type.
459 * allow function type pins to select
460 * any combination of function/in/out
461 * in their MARK lists.
470 if (get_config_reg(gpioc, enum_id, &cr,
471 &field, &value, &cntp) != 0)
475 case GPIO_CFG_DRYRUN:
477 (read_config_reg(gpioc, cr, field) != value))
482 write_config_reg(gpioc, cr, field, value);
497 static DEFINE_SPINLOCK(gpio_lock);
499 static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
501 return container_of(chip, struct pinmux_info, chip);
504 static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
506 struct pinmux_info *gpioc = chip_to_pinmux(chip);
507 struct pinmux_data_reg *dummy;
509 int i, ret, pinmux_type;
516 spin_lock_irqsave(&gpio_lock, flags);
518 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
521 /* setup pin function here if no data is associated with pin */
523 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
524 pinmux_type = PINMUX_TYPE_FUNCTION;
526 pinmux_type = PINMUX_TYPE_GPIO;
528 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
529 if (pinmux_config_gpio(gpioc, offset,
531 GPIO_CFG_DRYRUN) != 0)
534 if (pinmux_config_gpio(gpioc, offset,
540 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
541 gpioc->gpios[offset].flags |= pinmux_type;
545 spin_unlock_irqrestore(&gpio_lock, flags);
550 static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
552 struct pinmux_info *gpioc = chip_to_pinmux(chip);
559 spin_lock_irqsave(&gpio_lock, flags);
561 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
562 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
563 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
564 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
566 spin_unlock_irqrestore(&gpio_lock, flags);
569 static int pinmux_direction(struct pinmux_info *gpioc,
570 unsigned gpio, int new_pinmux_type)
578 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
580 switch (pinmux_type) {
581 case PINMUX_TYPE_GPIO:
583 case PINMUX_TYPE_OUTPUT:
584 case PINMUX_TYPE_INPUT:
585 case PINMUX_TYPE_INPUT_PULLUP:
586 case PINMUX_TYPE_INPUT_PULLDOWN:
587 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
593 if (pinmux_config_gpio(gpioc, gpio,
595 GPIO_CFG_DRYRUN) != 0)
598 if (pinmux_config_gpio(gpioc, gpio,
603 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
604 gpioc->gpios[gpio].flags |= new_pinmux_type;
611 static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
613 struct pinmux_info *gpioc = chip_to_pinmux(chip);
617 spin_lock_irqsave(&gpio_lock, flags);
618 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
619 spin_unlock_irqrestore(&gpio_lock, flags);
624 static void sh_gpio_set_value(struct pinmux_info *gpioc,
625 unsigned gpio, int value)
627 struct pinmux_data_reg *dr = NULL;
630 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
633 gpio_write_bit(dr, bit, value);
636 static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
639 struct pinmux_info *gpioc = chip_to_pinmux(chip);
643 sh_gpio_set_value(gpioc, offset, value);
644 spin_lock_irqsave(&gpio_lock, flags);
645 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
646 spin_unlock_irqrestore(&gpio_lock, flags);
651 static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
653 struct pinmux_data_reg *dr = NULL;
656 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
659 return gpio_read_bit(dr, bit);
662 static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
664 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
667 static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
669 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
672 static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
674 struct pinmux_info *gpioc = chip_to_pinmux(chip);
675 pinmux_enum_t enum_id;
676 pinmux_enum_t *enum_ids;
682 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
683 if (pos <= 0 || !enum_id)
686 for (i = 0; i < gpioc->gpio_irq_size; i++) {
687 enum_ids = gpioc->gpio_irq[i].enum_ids;
688 for (k = 0; enum_ids[k]; k++) {
689 if (enum_ids[k] == enum_id)
690 return gpioc->gpio_irq[i].irq;
698 int register_pinmux(struct pinmux_info *pip)
700 struct gpio_chip *chip = &pip->chip;
703 pr_info("%s handling gpio %d -> %d\n",
704 pip->name, pip->first_gpio, pip->last_gpio);
706 ret = pfc_ioremap(pip);
710 setup_data_regs(pip);
712 chip->request = sh_gpio_request;
713 chip->free = sh_gpio_free;
714 chip->direction_input = sh_gpio_direction_input;
715 chip->get = sh_gpio_get;
716 chip->direction_output = sh_gpio_direction_output;
717 chip->set = sh_gpio_set;
718 chip->to_irq = sh_gpio_to_irq;
720 WARN_ON(pip->first_gpio != 0); /* needs testing */
722 chip->label = pip->name;
723 chip->owner = THIS_MODULE;
724 chip->base = pip->first_gpio;
725 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
727 ret = gpiochip_add(chip);
734 int unregister_pinmux(struct pinmux_info *pip)
736 pr_info("%s deregistering\n", pip->name);
738 return gpiochip_remove(&pip->chip);