1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
67 #ifdef CONFIG_DRIVER_SMC91111
69 /* Use power-down feature of the chip */
77 static const char version[] =
78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
81 /*------------------------------------------------------------------------
83 . Configuration options, for the experienced user to change.
85 -------------------------------------------------------------------------*/
88 . Wait time for memory to be free. This probably shouldn't be
89 . tuned that much, as waiting for this means nothing else happens
92 #define MEMORY_WAIT_TIME 16
96 #define PRINTK3(args...) printf(args)
98 #define PRINTK3(args...)
102 #define PRINTK2(args...) printf(args)
104 #define PRINTK2(args...)
108 #define PRINTK(args...) printf(args)
110 #define PRINTK(args...)
114 /*------------------------------------------------------------------------
116 . The internal workings of the driver. If you are changing anything
117 . here with the SMC stuff, you should have the datasheet and know
118 . what you are doing.
120 -------------------------------------------------------------------------*/
121 #define CARDNAME "LAN91C111"
123 /* Memory sizing constant */
124 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
126 #ifndef CONFIG_SMC91111_BASE
127 #define CONFIG_SMC91111_BASE 0x20000300
130 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
132 #define SMC_DEV_NAME "SMC91111"
133 #define SMC_PHY_ADDR 0x0000
134 #define SMC_ALLOC_MAX_TRY 5
135 #define SMC_TX_TIMEOUT 30
137 #define SMC_PHY_CLOCK_DELAY 1000
141 #ifdef CONFIG_SMC_USE_32_BIT
146 /*-----------------------------------------------------------------
148 . The driver can be entered at any of the following entry points.
150 .------------------------------------------------------------------ */
152 extern int eth_init(bd_t *bd);
153 extern void eth_halt(void);
154 extern int eth_rx(void);
155 extern int eth_send(volatile void *packet, int length);
159 . This is called by register_netdev(). It is responsible for
160 . checking the portlist for the SMC9000 series chipset. If it finds
161 . one, then it will initialize the device, find the hardware information,
162 . and sets up the appropriate device parameters.
163 . NOTE: Interrupts are *OFF* when this procedure is called.
165 . NB:This shouldn't be static since it is referred to externally.
170 . This is called by unregister_netdev(). It is responsible for
171 . cleaning up before the driver is finally unregistered and discarded.
173 void smc_destructor(void);
176 . The kernel calls this function when someone wants to use the device,
177 . typically 'ifconfig ethX up'.
179 static int smc_open(bd_t *bd);
183 . This is called by the kernel in response to 'ifconfig ethX down'. It
184 . is responsible for cleaning up everything that the open routine
185 . does, and maybe putting the card into a powerdown state.
187 static int smc_close(void);
190 . Configures the PHY through the MII Management interface
192 #ifndef CONFIG_SMC91111_EXT_PHY
193 static void smc_phy_configure(void);
194 #endif /* !CONFIG_SMC91111_EXT_PHY */
197 . This is a separate procedure to handle the receipt of a packet, to
198 . leave the interrupt code looking slightly cleaner
200 static int smc_rcv(void);
202 /* See if a MAC address is defined in the current environment. If so use it. If not
203 . print a warning and set the environment and other globals with the default.
204 . If an EEPROM is present it really should be consulted.
206 int smc_get_ethaddr(bd_t *bd);
207 int get_rom_mac(char *v_rom_mac);
210 ------------------------------------------------------------
214 ------------------------------------------------------------
217 static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
220 * This function must be called before smc_open() if you want to override
221 * the default mac address.
224 void smc_set_mac_addr(const char *addr) {
227 for (i=0; i < sizeof(smc_mac_addr); i++){
228 smc_mac_addr[i] = addr[i];
233 * smc_get_macaddr is no longer used. If you want to override the default
234 * mac address, call smc_get_mac_addr as a part of the board initialization.
238 void smc_get_macaddr( byte *addr ) {
239 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
240 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
244 for (i=0; i<6; i++) {
245 addr[0] = *(dnp1110_mac+0);
246 addr[1] = *(dnp1110_mac+1);
247 addr[2] = *(dnp1110_mac+2);
248 addr[3] = *(dnp1110_mac+3);
249 addr[4] = *(dnp1110_mac+4);
250 addr[5] = *(dnp1110_mac+5);
255 /***********************************************
256 * Show available memory *
257 ***********************************************/
258 void dump_memory_info(void)
263 old_bank = SMC_inw(BANK_SELECT)&0xF;
266 mem_info = SMC_inw( MIR_REG );
267 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
269 SMC_SELECT_BANK(old_bank);
272 . A rather simple routine to print out a packet for debugging purposes.
275 static void print_packet( byte *, int );
278 #define tx_done(dev) 1
281 /* this does a soft reset on the device */
282 static void smc_reset( void );
284 /* Enable Interrupts, Receive, and Transmit */
285 static void smc_enable( void );
287 /* this puts the device in an inactive state */
288 static void smc_shutdown( void );
290 /* Routines to Read and Write the PHY Registers across the
291 MII Management Interface
294 #ifndef CONFIG_SMC91111_EXT_PHY
295 static word smc_read_phy_register(byte phyreg);
296 static void smc_write_phy_register(byte phyreg, word phydata);
297 #endif /* !CONFIG_SMC91111_EXT_PHY */
300 static int poll4int (byte mask, int timeout)
302 int tmo = get_timer (0) + timeout * CFG_HZ;
304 word old_bank = SMC_inw (BSR_REG);
306 PRINTK2 ("Polling...\n");
308 while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
309 if (get_timer (0) >= tmo) {
315 /* restore old bank selection */
316 SMC_SELECT_BANK (old_bank);
324 /* Only one release command at a time, please */
325 static inline void smc_wait_mmu_release_complete (void)
329 /* assume bank 2 selected */
330 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
331 udelay (1); /* Wait until not busy */
338 . Function: smc_reset( void )
340 . This sets the SMC91111 chip to its normal state, hopefully from whatever
341 . mess that any other DOS driver has put it in.
343 . Maybe I should reset more registers to defaults in here? SOFTRST should
347 . 1. send a SOFT RESET
348 . 2. wait for it to finish
349 . 3. enable autorelease mode
350 . 4. reset the memory management unit
351 . 5. clear all interrupts
354 static void smc_reset (void)
356 PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME);
358 /* This resets the registers mostly to defaults, but doesn't
359 affect EEPROM. That seems unnecessary */
361 SMC_outw (RCR_SOFTRST, RCR_REG);
363 /* Setup the Configuration Register */
364 /* This is necessary because the CONFIG_REG is not affected */
365 /* by a soft reset */
368 #if defined(CONFIG_SMC91111_EXT_PHY)
369 SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
371 SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
375 /* Release from possible power-down state */
376 /* Configuration register is not affected by Soft Reset */
377 SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
381 /* this should pause enough for the chip to be happy */
384 /* Disable transmit and receive functionality */
385 SMC_outw (RCR_CLEAR, RCR_REG);
386 SMC_outw (TCR_CLEAR, TCR_REG);
388 /* set the control register */
390 SMC_outw (CTL_DEFAULT, CTL_REG);
394 smc_wait_mmu_release_complete ();
395 SMC_outw (MC_RESET, MMU_CMD_REG);
396 while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
397 udelay (1); /* Wait until not busy */
399 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
400 but this is a place where future chipsets _COULD_ break. Be wary
401 of issuing another MMU command right after this */
403 /* Disable all interrupts */
404 SMC_outb (0, IM_REG);
408 . Function: smc_enable
409 . Purpose: let the chip talk to the outside work
411 . 1. Enable the transmitter
412 . 2. Enable the receiver
413 . 3. Enable interrupts
415 static void smc_enable()
417 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
418 SMC_SELECT_BANK( 0 );
419 /* see the header file for options in TCR/RCR DEFAULT*/
420 SMC_outw( TCR_DEFAULT, TCR_REG );
421 SMC_outw( RCR_DEFAULT, RCR_REG );
424 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
428 . Function: smc_shutdown
429 . Purpose: closes down the SMC91xxx chip.
431 . 1. zero the interrupt mask
432 . 2. clear the enable receive flag
433 . 3. clear the enable xmit flags
436 . (1) maybe utilize power down mode.
437 . Why not yet? Because while the chip will go into power down mode,
438 . the manual says that it will wake up in response to any I/O requests
439 . in the register space. Empirical results do not show this working.
441 static void smc_shutdown()
443 PRINTK2(CARDNAME ":smc_shutdown\n");
445 /* no more interrupts for me */
446 SMC_SELECT_BANK( 2 );
447 SMC_outb( 0, IM_REG );
449 /* and tell the card to stay away from that nasty outside world */
450 SMC_SELECT_BANK( 0 );
451 SMC_outb( RCR_CLEAR, RCR_REG );
452 SMC_outb( TCR_CLEAR, TCR_REG );
457 . Function: smc_hardware_send_packet(struct net_device * )
459 . This sends the actual packet to the SMC9xxx chip.
462 . First, see if a saved_skb is available.
463 . ( this should NOT be called if there is no 'saved_skb'
464 . Now, find the packet number that the chip allocated
465 . Point the data pointers at it in memory
466 . Set the length word in the chip's memory
467 . Dump the packet to chip memory
468 . Check if a last byte is needed ( odd length packet )
469 . if so, set the control flag right
470 . Tell the card to send it
471 . Enable the transmit interrupt, so I know if it failed
472 . Free the kernel data if I actually sent it.
474 static int smc_send_packet (volatile void *packet, int packet_length)
477 unsigned long ioaddr;
487 /* save PTR and PNR registers before manipulation */
489 saved_pnr = SMC_inb( PN_REG );
490 saved_ptr = SMC_inw( PTR_REG );
492 PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
494 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
497 ** The MMU wants the number of pages to be the number of 256 bytes
498 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
500 ** The 91C111 ignores the size bits, but the code is left intact
501 ** for backwards and future compatibility.
503 ** Pkt size for allocating is data length +6 (for additional status
504 ** words, length and ctl!)
506 ** If odd size then last byte is included in this header.
508 numPages = ((length & 0xfffe) + 6);
509 numPages >>= 8; /* Divide by 256 */
512 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
516 /* now, try to allocate the memory */
518 SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
520 /* FIXME: the ALLOC_INT bit never gets set *
521 * so the following will always give a *
522 * memory allocation error. *
523 * same code works in armboot though *
529 time_out = MEMORY_WAIT_TIME;
531 status = SMC_inb (SMC91111_INT_REG);
532 if (status & IM_ALLOC_INT) {
533 /* acknowledge the interrupt */
534 SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
537 } while (--time_out);
540 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
542 if (try < SMC_ALLOC_MAX_TRY)
548 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
551 /* I can send the packet now.. */
553 ioaddr = SMC_BASE_ADDRESS;
555 buf = (byte *) packet;
557 /* If I get here, I _know_ there is a packet slot waiting for me */
558 packet_no = SMC_inb (AR_REG);
559 if (packet_no & AR_FAILED) {
560 /* or isn't there? BAD CHIP! */
561 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
565 /* we have a packet address, so tell the card to use it */
566 SMC_outb (packet_no, PN_REG);
568 /* do not write new ptr value if Write data fifo not empty */
569 while ( saved_ptr & PTR_NOTEMPTY )
570 printf ("Write data fifo not empty!\n");
572 /* point to the beginning of the packet */
573 SMC_outw (PTR_AUTOINC, PTR_REG);
575 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
576 SMC_DEV_NAME, length);
579 printf ("Transmitting Packet\n");
580 print_packet (buf, length);
583 /* send the packet length ( +6 for status, length and ctl byte )
584 and the status word ( set to zeros ) */
586 SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
588 SMC_outw (0, SMC91111_DATA_REG);
589 /* send the packet length ( +6 for status words, length, and ctl */
590 SMC_outw ((length + 6), SMC91111_DATA_REG);
593 /* send the actual data
594 . I _think_ it's faster to send the longs first, and then
595 . mop up by sending the last word. It depends heavily
596 . on alignment, at least on the 486. Maybe it would be
597 . a good idea to check which is optimal? But that could take
598 . almost as much time as is saved?
601 SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
603 SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
606 SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
607 #endif /* USE_32_BIT */
609 /* Send the last byte, if there is one. */
610 if ((length & 1) == 0) {
611 SMC_outw (0, SMC91111_DATA_REG);
613 SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
616 /* and let the chipset deal with it */
617 SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
619 /* poll for TX INT */
620 /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
621 /* poll for TX_EMPTY INT - autorelease enabled */
622 if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
624 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
627 /* no need to release, MMU does that now */
628 /* SMC_outw (MC_FREEPKT, MMU_CMD_REG); */
630 /* wait for MMU getting ready (low) */
631 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
635 PRINTK2 ("MMU ready\n");
641 SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
642 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
643 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
647 /* no need to release, MMU does that now */
648 /* SMC_outw (MC_FREEPKT, MMU_CMD_REG); */
650 /* wait for MMU getting ready (low) */
651 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
655 PRINTK2 ("MMU ready\n");
660 /* restore previously saved registers */
661 SMC_outb( saved_pnr, PN_REG );
662 SMC_outw( saved_ptr, PTR_REG );
667 /*-------------------------------------------------------------------------
669 | smc_destructor( struct net_device * dev )
671 | dev, pointer to the device structure
676 ---------------------------------------------------------------------------
678 void smc_destructor()
680 PRINTK2(CARDNAME ":smc_destructor\n");
685 * Open and Initialize the board
687 * Set up everything, reset the card, etc ..
690 static int smc_open (bd_t * bd)
694 PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME);
696 /* reset the hardware */
700 /* Configure the PHY */
701 #ifndef CONFIG_SMC91111_EXT_PHY
702 smc_phy_configure ();
705 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
706 /* SMC_SELECT_BANK(0); */
707 /* SMC_outw(0, RPC_REG); */
710 err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
712 memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
713 return (-1); /* upper code ignores this, but NOT bi_enetaddr */
716 for (i = 0; i < 6; i += 2) {
719 address = smc_mac_addr[i + 1] << 8;
720 address |= smc_mac_addr[i];
721 SMC_outw (address, ADDR0_REG + i);
724 for (i = 0; i < 6; i++)
725 SMC_outb (smc_mac_addr[i], ADDR0_REG + i);
731 /*-------------------------------------------------------------
733 . smc_rcv - receive a packet from the card
735 . There is ( at least ) a packet waiting to be read from
739 . o If an error, record it
740 . o otherwise, read in the packet
741 --------------------------------------------------------------
756 /* save PTR and PTR registers */
757 saved_pnr = SMC_inb( PN_REG );
758 saved_ptr = SMC_inw( PTR_REG );
760 packet_number = SMC_inw( RXFIFO_REG );
762 if ( packet_number & RXFIFO_REMPTY ) {
767 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
768 /* start reading from the start of the packet */
769 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
771 /* First two words are status and packet_length */
773 stat_len = SMC_inl(SMC91111_DATA_REG);
774 status = stat_len & 0xffff;
775 packet_length = stat_len >> 16;
777 status = SMC_inw( SMC91111_DATA_REG );
778 packet_length = SMC_inw( SMC91111_DATA_REG );
781 packet_length &= 0x07ff; /* mask off top bits */
783 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
785 if ( !(status & RS_ERRORS ) ){
786 /* Adjust for having already read the first two words */
787 packet_length -= 4; /*4; */
790 /* set odd length for bug in LAN91C111, */
791 /* which never sets RS_ODDFRAME */
796 PRINTK3(" Reading %d dwords (and %d bytes) \n",
797 packet_length >> 2, packet_length & 3 );
798 /* QUESTION: Like in the TX routine, do I want
799 to send the DWORDs or the bytes first, or some
800 mixture. A mixture might improve already slow PIO
802 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
803 /* read the left over bytes */
804 if (packet_length & 3) {
807 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
808 dword leftover = SMC_inl(SMC91111_DATA_REG);
809 for (i=0; i<(packet_length & 3); i++)
810 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
813 PRINTK3(" Reading %d words and %d byte(s) \n",
814 (packet_length >> 1 ), packet_length & 1 );
815 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
817 #endif /* USE_32_BIT */
820 printf("Receiving Packet\n");
821 print_packet( NetRxPackets[0], packet_length );
829 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
830 udelay(1); /* Wait until not busy */
832 /* error or good, tell the card to get rid of this packet */
833 SMC_outw( MC_RELEASE, MMU_CMD_REG );
835 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
836 udelay(1); /* Wait until not busy */
838 /* restore saved registers */
839 SMC_outb( saved_pnr, PN_REG );
840 SMC_outw( saved_ptr, PTR_REG );
843 /* Pass the packet up to the protocol layers. */
844 NetReceive(NetRxPackets[0], packet_length);
845 return packet_length;
853 /*----------------------------------------------------
856 . this makes the board clean up everything that it can
857 . and not talk to the outside world. Caused by
858 . an 'ifconfig ethX down'
860 -----------------------------------------------------*/
861 static int smc_close()
863 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
865 /* clear everything */
873 /*------------------------------------------------------------
874 . Modify a bit in the LAN91C111 register set
875 .-------------------------------------------------------------*/
876 static word smc_modify_regbit(int bank, int ioaddr, int reg,
877 unsigned int bit, int val)
881 SMC_SELECT_BANK( bank );
883 regval = SMC_inw( reg );
889 SMC_outw( regval, 0 );
894 /*------------------------------------------------------------
895 . Retrieve a bit in the LAN91C111 register set
896 .-------------------------------------------------------------*/
897 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
899 SMC_SELECT_BANK( bank );
900 if ( SMC_inw( reg ) & bit)
907 /*------------------------------------------------------------
908 . Modify a LAN91C111 register (word access only)
909 .-------------------------------------------------------------*/
910 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
912 SMC_SELECT_BANK( bank );
913 SMC_outw( val, reg );
917 /*------------------------------------------------------------
918 . Retrieve a LAN91C111 register (word access only)
919 .-------------------------------------------------------------*/
920 static int smc_get_reg(int bank, int ioaddr, int reg)
922 SMC_SELECT_BANK( bank );
923 return(SMC_inw( reg ));
928 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
932 /*------------------------------------------------------------
933 . Debugging function for viewing MII Management serial bitstream
934 .-------------------------------------------------------------*/
935 static void smc_dump_mii_stream (byte * bits, int size)
940 for (i = 0; i < size; ++i) {
941 printf ("%d", i % 10);
945 for (i = 0; i < size; ++i) {
946 if (bits[i] & MII_MDOE)
953 for (i = 0; i < size; ++i) {
954 if (bits[i] & MII_MDO)
961 for (i = 0; i < size; ++i) {
962 if (bits[i] & MII_MDI)
972 /*------------------------------------------------------------
973 . Reads a register from the MII Management serial interface
974 .-------------------------------------------------------------*/
975 #ifndef CONFIG_SMC91111_EXT_PHY
976 static word smc_read_phy_register (byte phyreg)
986 byte phyaddr = SMC_PHY_ADDR;
988 /* 32 consecutive ones on MDO to establish sync */
989 for (i = 0; i < 32; ++i)
990 bits[clk_idx++] = MII_MDOE | MII_MDO;
992 /* Start code <01> */
993 bits[clk_idx++] = MII_MDOE;
994 bits[clk_idx++] = MII_MDOE | MII_MDO;
996 /* Read command <10> */
997 bits[clk_idx++] = MII_MDOE | MII_MDO;
998 bits[clk_idx++] = MII_MDOE;
1000 /* Output the PHY address, msb first */
1002 for (i = 0; i < 5; ++i) {
1004 bits[clk_idx++] = MII_MDOE | MII_MDO;
1006 bits[clk_idx++] = MII_MDOE;
1008 /* Shift to next lowest bit */
1012 /* Output the phy register number, msb first */
1014 for (i = 0; i < 5; ++i) {
1016 bits[clk_idx++] = MII_MDOE | MII_MDO;
1018 bits[clk_idx++] = MII_MDOE;
1020 /* Shift to next lowest bit */
1024 /* Tristate and turnaround (2 bit times) */
1025 bits[clk_idx++] = 0;
1026 /*bits[clk_idx++] = 0; */
1028 /* Input starts at this bit time */
1029 input_idx = clk_idx;
1031 /* Will input 16 bits */
1032 for (i = 0; i < 16; ++i)
1033 bits[clk_idx++] = 0;
1035 /* Final clock bit */
1036 bits[clk_idx++] = 0;
1038 /* Save the current bank */
1039 oldBank = SMC_inw (BANK_SELECT);
1042 SMC_SELECT_BANK (3);
1044 /* Get the current MII register value */
1045 mii_reg = SMC_inw (MII_REG);
1047 /* Turn off all MII Interface bits */
1048 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1050 /* Clock all 64 cycles */
1051 for (i = 0; i < sizeof bits; ++i) {
1052 /* Clock Low - output data */
1053 SMC_outw (mii_reg | bits[i], MII_REG);
1054 udelay (SMC_PHY_CLOCK_DELAY);
1057 /* Clock Hi - input data */
1058 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1059 udelay (SMC_PHY_CLOCK_DELAY);
1060 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1063 /* Return to idle state */
1064 /* Set clock to low, data to low, and output tristated */
1065 SMC_outw (mii_reg, MII_REG);
1066 udelay (SMC_PHY_CLOCK_DELAY);
1068 /* Restore original bank select */
1069 SMC_SELECT_BANK (oldBank);
1071 /* Recover input data */
1073 for (i = 0; i < 16; ++i) {
1076 if (bits[input_idx++] & MII_MDI)
1080 #if (SMC_DEBUG > 2 )
1081 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1082 phyaddr, phyreg, phydata);
1083 smc_dump_mii_stream (bits, sizeof bits);
1090 /*------------------------------------------------------------
1091 . Writes a register to the MII Management serial interface
1092 .-------------------------------------------------------------*/
1093 static void smc_write_phy_register (byte phyreg, word phydata)
1101 byte phyaddr = SMC_PHY_ADDR;
1103 /* 32 consecutive ones on MDO to establish sync */
1104 for (i = 0; i < 32; ++i)
1105 bits[clk_idx++] = MII_MDOE | MII_MDO;
1107 /* Start code <01> */
1108 bits[clk_idx++] = MII_MDOE;
1109 bits[clk_idx++] = MII_MDOE | MII_MDO;
1111 /* Write command <01> */
1112 bits[clk_idx++] = MII_MDOE;
1113 bits[clk_idx++] = MII_MDOE | MII_MDO;
1115 /* Output the PHY address, msb first */
1117 for (i = 0; i < 5; ++i) {
1119 bits[clk_idx++] = MII_MDOE | MII_MDO;
1121 bits[clk_idx++] = MII_MDOE;
1123 /* Shift to next lowest bit */
1127 /* Output the phy register number, msb first */
1129 for (i = 0; i < 5; ++i) {
1131 bits[clk_idx++] = MII_MDOE | MII_MDO;
1133 bits[clk_idx++] = MII_MDOE;
1135 /* Shift to next lowest bit */
1139 /* Tristate and turnaround (2 bit times) */
1140 bits[clk_idx++] = 0;
1141 bits[clk_idx++] = 0;
1143 /* Write out 16 bits of data, msb first */
1145 for (i = 0; i < 16; ++i) {
1147 bits[clk_idx++] = MII_MDOE | MII_MDO;
1149 bits[clk_idx++] = MII_MDOE;
1151 /* Shift to next lowest bit */
1155 /* Final clock bit (tristate) */
1156 bits[clk_idx++] = 0;
1158 /* Save the current bank */
1159 oldBank = SMC_inw (BANK_SELECT);
1162 SMC_SELECT_BANK (3);
1164 /* Get the current MII register value */
1165 mii_reg = SMC_inw (MII_REG);
1167 /* Turn off all MII Interface bits */
1168 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1170 /* Clock all cycles */
1171 for (i = 0; i < sizeof bits; ++i) {
1172 /* Clock Low - output data */
1173 SMC_outw (mii_reg | bits[i], MII_REG);
1174 udelay (SMC_PHY_CLOCK_DELAY);
1177 /* Clock Hi - input data */
1178 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1179 udelay (SMC_PHY_CLOCK_DELAY);
1180 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1183 /* Return to idle state */
1184 /* Set clock to low, data to low, and output tristated */
1185 SMC_outw (mii_reg, MII_REG);
1186 udelay (SMC_PHY_CLOCK_DELAY);
1188 /* Restore original bank select */
1189 SMC_SELECT_BANK (oldBank);
1191 #if (SMC_DEBUG > 2 )
1192 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1193 phyaddr, phyreg, phydata);
1194 smc_dump_mii_stream (bits, sizeof bits);
1197 #endif /* !CONFIG_SMC91111_EXT_PHY */
1200 /*------------------------------------------------------------
1201 . Waits the specified number of milliseconds - kernel friendly
1202 .-------------------------------------------------------------*/
1203 #ifndef CONFIG_SMC91111_EXT_PHY
1204 static void smc_wait_ms(unsigned int ms)
1208 #endif /* !CONFIG_SMC91111_EXT_PHY */
1211 /*------------------------------------------------------------
1212 . Configures the specified PHY using Autonegotiation. Calls
1213 . smc_phy_fixed() if the user has requested a certain config.
1214 .-------------------------------------------------------------*/
1215 #ifndef CONFIG_SMC91111_EXT_PHY
1216 static void smc_phy_configure ()
1220 word my_phy_caps; /* My PHY capabilities */
1221 word my_ad_caps; /* My Advertised capabilities */
1222 word status = 0; /*;my status = 0 */
1225 PRINTK3 ("%s:smc_program_phy()\n", SMC_DEV_NAME);
1228 /* Get the detected phy address */
1229 phyaddr = SMC_PHY_ADDR;
1231 /* Reset the PHY, setting all other bits to zero */
1232 smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
1234 /* Wait for the reset to complete, or time out */
1235 timeout = 6; /* Wait up to 3 seconds */
1237 if (!(smc_read_phy_register (PHY_CNTL_REG)
1239 /* reset complete */
1243 smc_wait_ms (500); /* wait 500 millisecs */
1247 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1248 goto smc_phy_configure_exit;
1251 /* Read PHY Register 18, Status Output */
1252 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1254 /* Enable PHY Interrupts (for register 18) */
1255 /* Interrupts listed here are disabled */
1256 smc_write_phy_register (PHY_MASK_REG, 0xffff);
1258 /* Configure the Receive/Phy Control register */
1259 SMC_SELECT_BANK (0);
1260 SMC_outw (RPC_DEFAULT, RPC_REG);
1262 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1263 my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
1264 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1266 if (my_phy_caps & PHY_STAT_CAP_T4)
1267 my_ad_caps |= PHY_AD_T4;
1269 if (my_phy_caps & PHY_STAT_CAP_TXF)
1270 my_ad_caps |= PHY_AD_TX_FDX;
1272 if (my_phy_caps & PHY_STAT_CAP_TXH)
1273 my_ad_caps |= PHY_AD_TX_HDX;
1275 if (my_phy_caps & PHY_STAT_CAP_TF)
1276 my_ad_caps |= PHY_AD_10_FDX;
1278 if (my_phy_caps & PHY_STAT_CAP_TH)
1279 my_ad_caps |= PHY_AD_10_HDX;
1281 /* Update our Auto-Neg Advertisement Register */
1282 smc_write_phy_register (PHY_AD_REG, my_ad_caps);
1284 /* Read the register back. Without this, it appears that when */
1285 /* auto-negotiation is restarted, sometimes it isn't ready and */
1286 /* the link does not come up. */
1287 smc_read_phy_register(PHY_AD_REG);
1289 PRINTK2 ("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1290 PRINTK2 ("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1292 /* Restart auto-negotiation process in order to advertise my caps */
1293 smc_write_phy_register (PHY_CNTL_REG,
1294 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1296 /* Wait for the auto-negotiation to complete. This may take from */
1297 /* 2 to 3 seconds. */
1298 /* Wait for the reset to complete, or time out */
1299 timeout = 20; /* Wait up to 10 seconds */
1301 status = smc_read_phy_register (PHY_STAT_REG);
1302 if (status & PHY_STAT_ANEG_ACK) {
1303 /* auto-negotiate complete */
1307 smc_wait_ms (500); /* wait 500 millisecs */
1309 /* Restart auto-negotiation if remote fault */
1310 if (status & PHY_STAT_REM_FLT) {
1311 printf ("%s:PHY remote fault detected\n",
1314 /* Restart auto-negotiation */
1315 printf ("%s:PHY restarting auto-negotiation\n",
1317 smc_write_phy_register (PHY_CNTL_REG,
1326 printf ("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1327 printf ("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1331 /* Fail if we detected an auto-negotiate remote fault */
1332 if (status & PHY_STAT_REM_FLT) {
1333 printf ("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1334 printf ("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1338 /* Re-Configure the Receive/Phy Control register */
1339 SMC_outw (RPC_DEFAULT, RPC_REG);
1341 smc_phy_configure_exit:
1344 #endif /* !CONFIG_SMC91111_EXT_PHY */
1348 static void print_packet( byte * buf, int length )
1354 printf("Packet of length %d \n", length );
1357 lines = length / 16;
1358 remainder = length % 16;
1360 for ( i = 0; i < lines ; i ++ ) {
1363 for ( cur = 0; cur < 8; cur ++ ) {
1368 printf("%02x%02x ", a, b );
1372 for ( i = 0; i < remainder/2 ; i++ ) {
1377 printf("%02x%02x ", a, b );
1384 int eth_init(bd_t *bd) {
1385 return (smc_open(bd));
1396 int eth_send(volatile void *packet, int length) {
1397 return smc_send_packet(packet, length);
1400 int smc_get_ethaddr (bd_t * bd)
1402 int env_size, rom_valid, env_present = 0, reg;
1403 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
1404 uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
1406 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1407 if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
1408 printf ("\n*** ERROR: ethaddr is not set properly!!\n");
1417 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
1418 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1420 s = (*e) ? e + 1 : e;
1423 rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */
1425 if (!env_present) { /* if NO env */
1426 if (rom_valid) { /* but ROM is valid */
1428 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
1429 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
1430 v_mac[4], v_mac[5]);
1431 setenv ("ethaddr", s_env_mac);
1432 } else { /* no env, bad ROM */
1433 printf ("\n*** ERROR: ethaddr is NOT set !!\n");
1436 } else { /* good env, don't care ROM */
1437 v_mac = v_env_mac; /* always use a good env over a ROM */
1440 if (env_present && rom_valid) { /* if both env and ROM are good */
1441 if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
1442 printf ("\nWarning: MAC addresses don't match:\n");
1443 printf ("\tHW MAC address: "
1444 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1445 v_rom_mac[0], v_rom_mac[1],
1446 v_rom_mac[2], v_rom_mac[3],
1447 v_rom_mac[4], v_rom_mac[5] );
1448 printf ("\t\"ethaddr\" value: "
1449 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1450 v_env_mac[0], v_env_mac[1],
1451 v_env_mac[2], v_env_mac[3],
1452 v_env_mac[4], v_env_mac[5]) ;
1453 debug ("### Set MAC addr from environment\n");
1456 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
1457 smc_set_mac_addr (v_mac); /* use old function to update smc default */
1458 PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
1459 v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
1463 int get_rom_mac (char *v_rom_mac)
1465 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1466 char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1468 memcpy (v_rom_mac, hw_mac_addr, 6);
1472 SMC_SELECT_BANK (1);
1475 v_rom_mac[i] = SMC_inb (ADDR0_REG + i);
1480 #endif /* CONFIG_DRIVER_SMC91111 */