2 * Rockchip Generic power domain support.
4 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/err.h>
13 #include <linux/pm_clock.h>
14 #include <linux/pm_domain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/clk.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 #include <dt-bindings/power/rk3288-power.h>
21 #include <dt-bindings/power/rk3368-power.h>
23 struct rockchip_domain_info {
31 struct rockchip_pmu_info {
38 u32 core_pwrcnt_offset;
39 u32 gpu_pwrcnt_offset;
41 unsigned int core_power_transition_time;
42 unsigned int gpu_power_transition_time;
45 const struct rockchip_domain_info *domain_info;
48 struct rockchip_pm_domain {
49 struct generic_pm_domain genpd;
50 const struct rockchip_domain_info *info;
51 struct rockchip_pmu *pmu;
58 struct regmap *regmap;
59 const struct rockchip_pmu_info *info;
60 struct mutex mutex; /* mutex lock for pmu */
61 struct genpd_onecell_data genpd_data;
62 struct generic_pm_domain *domains[];
65 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
67 #define DOMAIN(pwr, status, req, idle, ack) \
69 .pwr_mask = BIT(pwr), \
70 .status_mask = BIT(status), \
71 .req_mask = BIT(req), \
72 .idle_mask = BIT(idle), \
73 .ack_mask = BIT(ack), \
76 #define DOMAIN_RK3288(pwr, status, req) \
77 DOMAIN(pwr, status, req, req, (req) + 16)
79 #define DOMAIN_RK3368(pwr, status, req) \
80 DOMAIN(pwr, status, req, (req) + 16, req)
82 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
84 struct rockchip_pmu *pmu = pd->pmu;
85 const struct rockchip_domain_info *pd_info = pd->info;
88 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
89 return (val & pd_info->idle_mask) == pd_info->idle_mask;
92 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
95 const struct rockchip_domain_info *pd_info = pd->info;
96 struct rockchip_pmu *pmu = pd->pmu;
99 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
100 pd_info->req_mask, idle ? -1U : 0);
105 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
106 } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
108 while (rockchip_pmu_domain_is_idle(pd) != idle)
114 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
116 struct rockchip_pmu *pmu = pd->pmu;
119 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
121 /* 1'b0: power on, 1'b1: power off */
122 return !(val & pd->info->status_mask);
125 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
128 struct rockchip_pmu *pmu = pd->pmu;
130 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
131 pd->info->pwr_mask, on ? 0 : -1U);
135 while (rockchip_pmu_domain_is_on(pd) != on)
139 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
143 mutex_lock(&pd->pmu->mutex);
145 if (rockchip_pmu_domain_is_on(pd) != power_on) {
146 for (i = 0; i < pd->num_clks; i++)
147 clk_enable(pd->clks[i]);
150 /* FIXME: add code to save AXI_QOS */
152 /* if powering down, idle request to NIU first */
153 rockchip_pmu_set_idle_request(pd, true);
156 rockchip_do_pmu_set_power_domain(pd, power_on);
159 /* if powering up, leave idle mode */
160 rockchip_pmu_set_idle_request(pd, false);
162 /* FIXME: add code to restore AXI_QOS */
165 for (i = pd->num_clks - 1; i >= 0; i--)
166 clk_disable(pd->clks[i]);
169 mutex_unlock(&pd->pmu->mutex);
173 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
175 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
177 return rockchip_pd_power(pd, true);
180 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
182 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
184 return rockchip_pd_power(pd, false);
187 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
194 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
196 error = pm_clk_create(dev);
198 dev_err(dev, "pm_clk_create failed %d\n", error);
203 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
204 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
205 error = pm_clk_add_clk(dev, clk);
207 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
217 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
220 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
225 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
226 struct device_node *node)
228 const struct rockchip_domain_info *pd_info;
229 struct rockchip_pm_domain *pd;
236 error = of_property_read_u32(node, "reg", &id);
239 "%s: failed to retrieve domain id (reg): %d\n",
244 if (id >= pmu->info->num_domains) {
245 dev_err(pmu->dev, "%s: invalid domain id %d\n",
250 pd_info = &pmu->info->domain_info[id];
252 dev_err(pmu->dev, "%s: undefined domain id %d\n",
257 clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
258 pd = devm_kzalloc(pmu->dev,
259 sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
267 for (i = 0; i < clk_cnt; i++) {
268 clk = of_clk_get(node, i);
270 error = PTR_ERR(clk);
272 "%s: failed to get clk at index %d: %d\n",
273 node->name, i, error);
277 error = clk_prepare(clk);
280 "%s: failed to prepare clk %pC (index %d): %d\n",
281 node->name, clk, i, error);
286 pd->clks[pd->num_clks++] = clk;
288 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
292 error = rockchip_pd_power(pd, true);
295 "failed to power on domain '%s': %d\n",
300 pd->genpd.name = node->name;
301 pd->genpd.power_off = rockchip_pd_power_off;
302 pd->genpd.power_on = rockchip_pd_power_on;
303 pd->genpd.attach_dev = rockchip_pd_attach_dev;
304 pd->genpd.detach_dev = rockchip_pd_detach_dev;
305 pd->genpd.flags = GENPD_FLAG_PM_CLK;
306 pm_genpd_init(&pd->genpd, NULL, false);
308 pmu->genpd_data.domains[id] = &pd->genpd;
313 clk_unprepare(pd->clks[i]);
314 clk_put(pd->clks[i]);
319 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
323 for (i = 0; i < pd->num_clks; i++) {
324 clk_unprepare(pd->clks[i]);
325 clk_put(pd->clks[i]);
328 /* protect the zeroing of pm->num_clks */
329 mutex_lock(&pd->pmu->mutex);
331 mutex_unlock(&pd->pmu->mutex);
333 /* devm will free our memory */
336 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
338 struct generic_pm_domain *genpd;
339 struct rockchip_pm_domain *pd;
342 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
343 genpd = pmu->genpd_data.domains[i];
345 pd = to_rockchip_pd(genpd);
346 rockchip_pm_remove_one_domain(pd);
350 /* devm will free our memory */
353 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
354 u32 domain_reg_offset,
357 /* First configure domain power down transition count ... */
358 regmap_write(pmu->regmap, domain_reg_offset, count);
359 /* ... and then power up count. */
360 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
363 static int rockchip_pm_domain_probe(struct platform_device *pdev)
365 struct device *dev = &pdev->dev;
366 struct device_node *np = dev->of_node;
367 struct device_node *node;
368 struct device *parent;
369 struct rockchip_pmu *pmu;
370 const struct of_device_id *match;
371 const struct rockchip_pmu_info *pmu_info;
375 dev_err(dev, "device tree node not found\n");
379 match = of_match_device(dev->driver->of_match_table, dev);
380 if (!match || !match->data) {
381 dev_err(dev, "missing pmu data\n");
385 pmu_info = match->data;
387 pmu = devm_kzalloc(dev,
389 pmu_info->num_domains * sizeof(pmu->domains[0]),
394 pmu->dev = &pdev->dev;
395 mutex_init(&pmu->mutex);
397 pmu->info = pmu_info;
399 pmu->genpd_data.domains = pmu->domains;
400 pmu->genpd_data.num_domains = pmu_info->num_domains;
402 parent = dev->parent;
404 dev_err(dev, "no parent for syscon devices\n");
408 pmu->regmap = syscon_node_to_regmap(parent->of_node);
411 * Configure power up and down transition delays for CORE
414 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
415 pmu_info->core_power_transition_time);
416 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
417 pmu_info->gpu_power_transition_time);
421 for_each_available_child_of_node(np, node) {
422 error = rockchip_pm_add_one_domain(pmu, node);
424 dev_err(dev, "failed to handle node %s: %d\n",
432 dev_dbg(dev, "no power domains defined\n");
436 of_genpd_add_provider_onecell(np, &pmu->genpd_data);
441 rockchip_pm_domain_cleanup(pmu);
445 static const struct rockchip_domain_info rk3288_pm_domains[] = {
446 [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4),
447 [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9),
448 [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3),
449 [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2),
452 static const struct rockchip_domain_info rk3368_pm_domains[] = {
453 [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6),
454 [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8),
455 [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7),
456 [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2),
457 [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2),
460 static const struct rockchip_pmu_info rk3288_pmu = {
462 .status_offset = 0x0c,
467 .core_pwrcnt_offset = 0x34,
468 .gpu_pwrcnt_offset = 0x3c,
470 .core_power_transition_time = 24, /* 1us */
471 .gpu_power_transition_time = 24, /* 1us */
473 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
474 .domain_info = rk3288_pm_domains,
477 static const struct rockchip_pmu_info rk3368_pmu = {
479 .status_offset = 0x10,
484 .core_pwrcnt_offset = 0x48,
485 .gpu_pwrcnt_offset = 0x50,
487 .core_power_transition_time = 24,
488 .gpu_power_transition_time = 24,
490 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
491 .domain_info = rk3368_pm_domains,
494 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
496 .compatible = "rockchip,rk3288-power-controller",
497 .data = (void *)&rk3288_pmu,
500 .compatible = "rockchip,rk3368-power-controller",
501 .data = (void *)&rk3368_pmu,
506 static struct platform_driver rockchip_pm_domain_driver = {
507 .probe = rockchip_pm_domain_probe,
509 .name = "rockchip-pm-domain",
510 .of_match_table = rockchip_pm_domain_dt_match,
512 * We can't forcibly eject devices form power domain,
513 * so we can't really remove power domains once they
516 .suppress_bind_attrs = true,
520 static int __init rockchip_pm_domain_drv_register(void)
522 return platform_driver_register(&rockchip_pm_domain_driver);
524 postcore_initcall(rockchip_pm_domain_drv_register);