2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chandrasekar <rcsekar@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/clk.h>
24 #include <asm/arch/cpu.h>
33 #include "wm8994_registers.h"
35 /* defines for wm8994 system clock selection */
36 #define SEL_MCLK1 0x00
37 #define SEL_MCLK2 0x08
41 /* fll config to configure fll */
42 struct wm8994_fll_config {
44 int in; /* Input frequency in Hz */
45 int out; /* output frequency in Hz */
48 /* codec private data */
50 enum wm8994_type type; /* codec type of wolfson */
51 int revision; /* Revision */
52 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
53 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
54 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
55 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
58 /* wm 8994 supported sampling rate values */
59 static unsigned int src_rate[] = {
60 8000, 11025, 12000, 16000, 22050, 24000,
61 32000, 44100, 48000, 88200, 96000
64 /* op clock divisions */
65 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
67 /* lr clock frame size ratio */
68 static int fs_ratios[] = {
69 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
72 /* bit clock divisors */
73 static int bclk_divs[] = {
74 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
75 640, 880, 960, 1280, 1760, 1920
78 static struct wm8994_priv g_wm8994_info;
79 static unsigned char g_wm8994_i2c_dev_addr;
82 * Initialise I2C for wm 8994
84 * @param bus no i2c bus number in which wm8994 is connected
86 static void wm8994_i2c_init(int bus_no)
88 i2c_set_bus_num(bus_no);
92 * Writes value to a device register through i2c
94 * @param reg reg number to be write
95 * @param data data to be writen to the above registor
97 * @return int value 1 for change, 0 for no change or negative error code.
99 static int wm8994_i2c_write(unsigned int reg, unsigned short data)
101 unsigned char val[2];
103 val[0] = (unsigned char)((data >> 8) & 0xff);
104 val[1] = (unsigned char)(data & 0xff);
105 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
107 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
111 * Read a value from a device register through i2c
113 * @param reg reg number to be read
114 * @param data address of read data to be stored
116 * @return int value 0 for success, -1 in case of error.
118 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
120 unsigned char val[2];
123 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
125 debug("%s: Error while reading register %#04x\n",
138 * update device register bits through i2c
140 * @param reg codec register
141 * @param mask register mask
142 * @param value new value
144 * @return int value 1 if change in the register value,
145 * 0 for no change or negative error code.
147 static int wm8994_update_bits(unsigned int reg, unsigned short mask,
148 unsigned short value)
150 int change , ret = 0;
151 unsigned short old, new;
153 if (wm8994_i2c_read(reg, &old) != 0)
155 new = (old & ~mask) | (value & mask);
156 change = (old != new) ? 1 : 0;
158 ret = wm8994_i2c_write(reg, new);
166 * Sets i2s set format
168 * @param aif_id Interface ID
169 * @param fmt i2S format
171 * @return -1 for error and 0 Success.
173 int wm8994_set_fmt(int aif_id, unsigned int fmt)
184 ms_reg = WM8994_AIF1_MASTER_SLAVE;
185 aif_reg = WM8994_AIF1_CONTROL_1;
186 aif_clk = WM8994_AIF1_CLOCKING_1;
189 ms_reg = WM8994_AIF2_MASTER_SLAVE;
190 aif_reg = WM8994_AIF2_CONTROL_1;
191 aif_clk = WM8994_AIF2_CLOCKING_1;
194 debug("%s: Invalid audio interface selection\n", __func__);
198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199 case SND_SOC_DAIFMT_CBS_CFS:
201 case SND_SOC_DAIFMT_CBM_CFM:
202 ms = WM8994_AIF1_MSTR;
205 debug("%s: Invalid i2s master selection\n", __func__);
209 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
210 case SND_SOC_DAIFMT_DSP_B:
211 aif |= WM8994_AIF1_LRCLK_INV;
212 case SND_SOC_DAIFMT_DSP_A:
215 case SND_SOC_DAIFMT_I2S:
218 case SND_SOC_DAIFMT_RIGHT_J:
220 case SND_SOC_DAIFMT_LEFT_J:
224 debug("%s: Invalid i2s format selection\n", __func__);
228 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
229 case SND_SOC_DAIFMT_DSP_A:
230 case SND_SOC_DAIFMT_DSP_B:
231 /* frame inversion not valid for DSP modes */
232 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
233 case SND_SOC_DAIFMT_NB_NF:
235 case SND_SOC_DAIFMT_IB_NF:
236 aif |= WM8994_AIF1_BCLK_INV;
239 debug("%s: Invalid i2s frame inverse selection\n",
245 case SND_SOC_DAIFMT_I2S:
246 case SND_SOC_DAIFMT_RIGHT_J:
247 case SND_SOC_DAIFMT_LEFT_J:
248 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
249 case SND_SOC_DAIFMT_NB_NF:
251 case SND_SOC_DAIFMT_IB_IF:
252 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
254 case SND_SOC_DAIFMT_IB_NF:
255 aif |= WM8994_AIF1_BCLK_INV;
257 case SND_SOC_DAIFMT_NB_IF:
258 aif |= WM8994_AIF1_LRCLK_INV;
261 debug("%s: Invalid i2s clock polarity selection\n",
267 debug("%s: Invalid i2s format selection\n", __func__);
271 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
272 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
274 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
275 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
278 debug("%s: codec register access error\n", __func__);
286 * Sets hw params FOR WM8994
288 * @param wm8994 wm8994 information pointer
289 * @param aif_id Audio interface ID
290 * @param sampling_rate Sampling rate
291 * @param bits_per_sample Bits per sample
292 * @param Channels Channels in the given audio input
294 * @return -1 for error and 0 Success.
296 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
297 unsigned int sampling_rate, unsigned int bits_per_sample,
298 unsigned int channels)
309 int i, cur_val, best_val, bclk_rate, best;
310 unsigned short reg_data;
315 aif1_reg = WM8994_AIF1_CONTROL_1;
316 aif2_reg = WM8994_AIF1_CONTROL_2;
317 bclk_reg = WM8994_AIF1_BCLK;
318 rate_reg = WM8994_AIF1_RATE;
321 aif1_reg = WM8994_AIF2_CONTROL_1;
322 aif2_reg = WM8994_AIF2_CONTROL_2;
323 bclk_reg = WM8994_AIF2_BCLK;
324 rate_reg = WM8994_AIF2_RATE;
330 bclk_rate = sampling_rate * 32;
331 switch (bits_per_sample) {
351 /* Try to find an appropriate sample rate; look for an exact match. */
352 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
353 if (src_rate[i] == sampling_rate)
356 if (i == ARRAY_SIZE(src_rate)) {
357 debug("%s: Could not get the best matching samplingrate\n",
362 rate_val |= i << WM8994_AIF1_SR_SHIFT;
364 /* AIFCLK/fs ratio; look for a close match in either direction */
366 best_val = abs((fs_ratios[0] * sampling_rate)
367 - wm8994->aifclk[id]);
369 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
370 cur_val = abs((fs_ratios[i] * sampling_rate)
371 - wm8994->aifclk[id]);
372 if (cur_val >= best_val)
381 * We may not get quite the right frequency if using
382 * approximate clocks so look for the closest match that is
383 * higher than the target (we need to ensure that there enough
384 * BCLKs to clock out the samples).
387 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
388 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
389 if (cur_val < 0) /* BCLK table is sorted */
394 if (i == ARRAY_SIZE(bclk_divs)) {
395 debug("%s: Could not get the best matching bclk division\n",
400 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
401 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
403 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
404 debug("%s: AIF1 register read Failed\n", __func__);
408 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
409 aif2 |= WM8994_AIF1_MONO;
411 if (wm8994->aifclk[id] == 0) {
412 debug("%s:Audio interface clock not set\n", __func__);
416 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
417 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
418 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
419 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
420 WM8994_AIF1CLK_RATE_MASK, rate_val);
422 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
425 debug("%s: codec register access error\n", __func__);
433 * Configures Audio interface Clock
435 * @param wm8994 wm8994 information pointer
436 * @param aif Audio Interface ID
438 * @return -1 for error and 0 Success.
440 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
447 /* AIF(1/0) register adress offset calculated */
453 switch (wm8994->sysclk[aif]) {
454 case WM8994_SYSCLK_MCLK1:
456 rate = wm8994->mclk[0];
459 case WM8994_SYSCLK_MCLK2:
461 rate = wm8994->mclk[1];
464 case WM8994_SYSCLK_FLL1:
466 rate = wm8994->fll[0].out;
469 case WM8994_SYSCLK_FLL2:
471 rate = wm8994->fll[1].out;
475 debug("%s: Invalid input clock selection [%d]\n",
476 __func__, wm8994->sysclk[aif]);
480 /* if input clock frequenct is more than 135Mhz then divide */
481 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
483 reg1 |= WM8994_AIF1CLK_DIV;
486 wm8994->aifclk[aif] = rate;
488 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
489 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
492 ret |= wm8994_update_bits(WM8994_CLOCKING_1,
493 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
494 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
495 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
498 debug("%s: codec register access error\n", __func__);
506 * Configures Audio interface for the given frequency
508 * @param wm8994 wm8994 information
509 * @param aif_id Audio Interface
510 * @param clk_id Input Clock ID
511 * @param freq Sampling frequency in Hz
513 * @return -1 for error and 0 success.
515 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
516 int clk_id, unsigned int freq)
521 wm8994->sysclk[aif_id - 1] = clk_id;
524 case WM8994_SYSCLK_MCLK1:
525 wm8994->mclk[0] = freq;
527 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
528 WM8994_AIF2DAC_DIV_MASK , 0);
532 case WM8994_SYSCLK_MCLK2:
533 /* TODO: Set GPIO AF */
534 wm8994->mclk[1] = freq;
537 case WM8994_SYSCLK_FLL1:
538 case WM8994_SYSCLK_FLL2:
541 case WM8994_SYSCLK_OPCLK:
543 * Special case - a division (times 10) is given and
544 * no effect on main clocking.
547 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
548 if (opclk_divs[i] == freq)
550 if (i == ARRAY_SIZE(opclk_divs)) {
551 debug("%s frequency divisor not found\n",
555 ret = wm8994_update_bits(WM8994_CLOCKING_2,
556 WM8994_OPCLK_DIV_MASK, i);
557 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
558 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
560 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
561 WM8994_OPCLK_ENA, 0);
565 debug("%s Invalid input clock selection [%d]\n",
570 ret |= configure_aif_clock(wm8994, aif_id - 1);
573 debug("%s: codec register access error\n", __func__);
581 * Initializes Volume for AIF2 to HP path
583 * @returns -1 for error and 0 Success.
586 static int wm8994_init_volume_aif2_dac1(void)
591 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
592 WM8994_AIF2DAC_MUTE_MASK, 0);
595 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
596 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
597 WM8994_AIF2DAC_VU | 0xff);
599 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
600 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
601 WM8994_AIF2DAC_VU | 0xff);
604 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
605 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
606 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
608 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
609 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
610 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
611 /* Head Phone Volume */
612 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
613 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
616 debug("%s: codec register access error\n", __func__);
624 * Intialise wm8994 codec device
626 * @param wm8994 wm8994 information
628 * @returns -1 for error and 0 Success.
630 static int wm8994_device_init(struct wm8994_priv *wm8994)
633 unsigned short reg_data;
636 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
638 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
640 debug("Failed to read ID register\n");
644 if (reg_data == WM8994_ID) {
646 debug("Device registered as type %d\n", wm8994->type);
647 wm8994->type = WM8994;
649 debug("Device is not a WM8994, ID is %x\n", ret);
654 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
656 debug("Failed to read revision register: %d\n", ret);
659 wm8994->revision = reg_data;
660 debug("%s revision %c\n", devname, 'A' + wm8994->revision);
663 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
664 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
666 /* Charge Pump Enable */
667 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
670 /* Head Phone Power Enable */
671 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
672 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
674 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
675 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
677 /* Power enable for AIF2 and DAC1 */
678 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
679 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
680 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
681 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
684 /* Head Phone Initialisation */
685 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
686 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
687 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
689 ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
690 WM8994_DCS_ENA_CHAN_0_MASK |
691 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
692 WM8994_DCS_ENA_CHAN_1);
694 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
695 WM8994_HPOUT1L_DLY_MASK |
696 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
697 WM8994_HPOUT1R_OUTP_MASK |
698 WM8994_HPOUT1L_RMV_SHORT_MASK |
699 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
700 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
701 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
702 WM8994_HPOUT1R_RMV_SHORT);
704 /* MIXER Config DAC1 to HP */
705 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
706 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
708 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
709 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
711 /* Routing AIF2 to DAC1 */
712 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
713 WM8994_AIF2DACL_TO_DAC1L_MASK,
714 WM8994_AIF2DACL_TO_DAC1L);
716 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
717 WM8994_AIF2DACR_TO_DAC1R_MASK,
718 WM8994_AIF2DACR_TO_DAC1R);
720 /* GPIO Settings for AIF2 */
722 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
723 WM8994_GPIO_FUNCTION_MASK ,
724 WM8994_GPIO_DIR_OUTPUT |
725 WM8994_GPIO_FUNCTION_I2S_CLK);
728 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
729 WM8994_GPIO_FUNCTION_MASK,
730 WM8994_GPIO_DIR_OUTPUT |
731 WM8994_GPIO_FUNCTION_I2S_CLK);
734 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
735 WM8994_GPIO_FUNCTION_MASK,
736 WM8994_GPIO_DIR_OUTPUT |
737 WM8994_GPIO_FUNCTION_I2S_CLK);
739 ret |= wm8994_init_volume_aif2_dac1();
743 debug("%s: Codec chip init ok\n", __func__);
746 debug("%s: Codec chip init error\n", __func__);
750 /*wm8994 Device Initialisation */
751 int wm8994_init(struct sound_codec_info *pcodec_info,
752 enum en_audio_interface aif_id,
753 int sampling_rate, int mclk_freq,
754 int bits_per_sample, unsigned int channels)
758 /* shift the device address by 1 for 7 bit addressing */
759 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
760 wm8994_i2c_init(pcodec_info->i2c_bus);
762 if (pcodec_info->codec_type == CODEC_WM_8994)
763 g_wm8994_info.type = WM8994;
765 debug("%s: Codec id [%d] not defined\n", __func__,
766 pcodec_info->codec_type);
770 ret = wm8994_device_init(&g_wm8994_info);
772 debug("%s: wm8994 codec chip init failed\n", __func__);
776 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
779 debug("%s: wm8994 codec set sys clock failed\n", __func__);
783 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
784 bits_per_sample, channels);
787 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
788 SND_SOC_DAIFMT_NB_NF |
789 SND_SOC_DAIFMT_CBS_CFS);