drivers/spi/atmel_spi.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22
  23 #include <asm/io.h>
  24 #include <mach/board.h>
  25 #include <mach/gpio.h>
  26 #include <mach/cpu.h>
  27
  28 #include "atmel_spi.h"
  29
  30 /*
  31  * The core SPI transfer engine just talks to a register bank to set up
  32  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
  33  * framework provides the base clock, subdivided for each spi_device.
  34  */
  35 struct atmel_spi {
  36         spinlock_t              lock;
  37
  38         void __iomem            *regs;
  39         int                     irq;
  40         struct clk              *clk;
  41         struct platform_device  *pdev;
  42         struct spi_device       *stay;
  43
  44         u8                      stopping;
  45         struct list_head        queue;
  46         struct spi_transfer     *current_transfer;
  47         unsigned long           current_remaining_bytes;
  48         struct spi_transfer     *next_transfer;
  49         unsigned long           next_remaining_bytes;
  50
  51         void                    *buffer;
  52         dma_addr_t              buffer_dma;
  53 };
  54
  55 /* Controller-specific per-slave state */
  56 struct atmel_spi_device {
  57         unsigned int            npcs_pin;
  58         u32                     csr;
  59 };
  60
  61 #define BUFFER_SIZE             PAGE_SIZE
  62 #define INVALID_DMA_ADDRESS     0xffffffff
  63
  64 /*
  65  * Version 2 of the SPI controller has
  66  *  - CR.LASTXFER
  67  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  68  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  69  *  - SPI_CSRx.CSAAT
  70  *  - SPI_CSRx.SBCR allows faster clocking
  71  *
  72  * We can determine the controller version by reading the VERSION
  73  * register, but I haven't checked that it exists on all chips, and
  74  * this is cheaper anyway.
  75  */
  76 static bool atmel_spi_is_v2(void)
  77 {
  78         return !cpu_is_at91rm9200();
  79 }
  80
  81 /*
  82  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  83  * they assume that spi slave device state will not change on deselect, so
  84  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
  85  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
  86  * controllers have CSAAT and friends.
  87  *
  88  * Since the CSAAT functionality is a bit weird on newer controllers as
  89  * well, we use GPIO to control nCSx pins on all controllers, updating
  90  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
  91  * support active-high chipselects despite the controller's belief that
  92  * only active-low devices/systems exists.
  93  *
  94  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
  95  * right when driven with GPIO.  ("Mode Fault does not allow more than one
  96  * Master on Chip Select 0.")  No workaround exists for that ... so for
  97  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
  98  * and (c) will trigger that first erratum in some cases.
  99  *
 100  * TODO: Test if the atmel_spi_is_v2() branch below works on
 101  * AT91RM9200 if we use some other register than CSR0. However, don't
 102  * do this unconditionally since AP7000 has an errata where the BITS
 103  * field in CSR0 overrides all other CSRs.
 104  */
 105
 106 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 107 {
 108         struct atmel_spi_device *asd = spi->controller_state;
 109         unsigned active = spi->mode & SPI_CS_HIGH;
 110         u32 mr;
 111
 112         if (atmel_spi_is_v2()) {
 113                 /*
 114                  * Always use CSR0. This ensures that the clock
 115                  * switches to the correct idle polarity before we
 116                  * toggle the CS.
 117                  */
 118                 spi_writel(as, CSR0, asd->csr);
 119                 spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
 120                                 | SPI_BIT(MSTR));
 121                 mr = spi_readl(as, MR);
 122                 gpio_set_value(asd->npcs_pin, active);
 123         } else {
 124                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 125                 int i;
 126                 u32 csr;
 127
 128                 /* Make sure clock polarity is correct */
 129                 for (i = 0; i < spi->master->num_chipselect; i++) {
 130                         csr = spi_readl(as, CSR0 + 4 * i);
 131                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 132                                 spi_writel(as, CSR0 + 4 * i,
 133                                                 csr ^ SPI_BIT(CPOL));
 134                 }
 135
 136                 mr = spi_readl(as, MR);
 137                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 138                 if (spi->chip_select != 0)
 139                         gpio_set_value(asd->npcs_pin, active);
 140                 spi_writel(as, MR, mr);
 141         }
 142
 143         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 144                         asd->npcs_pin, active ? " (high)" : "",
 145                         mr);
 146 }
 147
 148 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 149 {
 150         struct atmel_spi_device *asd = spi->controller_state;
 151         unsigned active = spi->mode & SPI_CS_HIGH;
 152         u32 mr;
 153
 154         /* only deactivate *this* device; sometimes transfers to
 155          * another device may be active when this routine is called.
 156          */
 157         mr = spi_readl(as, MR);
 158         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 159                 mr = SPI_BFINS(PCS, 0xf, mr);
 160                 spi_writel(as, MR, mr);
 161         }
 162
 163         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 164                         asd->npcs_pin, active ? " (low)" : "",
 165                         mr);
 166
 167         if (atmel_spi_is_v2() || spi->chip_select != 0)
 168                 gpio_set_value(asd->npcs_pin, !active);
 169 }
 170
 171 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 172                                         struct spi_transfer *xfer)
 173 {
 174         return msg->transfers.prev == &xfer->transfer_list;
 175 }
 176
 177 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 178 {
 179         return xfer->delay_usecs == 0 && !xfer->cs_change;
 180 }
 181
 182 static void atmel_spi_next_xfer_data(struct spi_master *master,
 183                                 struct spi_transfer *xfer,
 184                                 dma_addr_t *tx_dma,
 185                                 dma_addr_t *rx_dma,
 186                                 u32 *plen)
 187 {
 188         struct atmel_spi        *as = spi_master_get_devdata(master);
 189         u32                     len = *plen;
 190
 191         /* use scratch buffer only when rx or tx data is unspecified */
 192         if (xfer->rx_buf)
 193                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 194         else {
 195                 *rx_dma = as->buffer_dma;
 196                 if (len > BUFFER_SIZE)
 197                         len = BUFFER_SIZE;
 198         }
 199         if (xfer->tx_buf)
 200                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 201         else {
 202                 *tx_dma = as->buffer_dma;
 203                 if (len > BUFFER_SIZE)
 204                         len = BUFFER_SIZE;
 205                 memset(as->buffer, 0, len);
 206                 dma_sync_single_for_device(&as->pdev->dev,
 207                                 as->buffer_dma, len, DMA_TO_DEVICE);
 208         }
 209
 210         *plen = len;
 211 }
 212
 213 /*
 214  * Submit next transfer for DMA.
 215  * lock is held, spi irq is blocked
 216  */
 217 static void atmel_spi_next_xfer(struct spi_master *master,
 218                                 struct spi_message *msg)
 219 {
 220         struct atmel_spi        *as = spi_master_get_devdata(master);
 221         struct spi_transfer     *xfer;
 222         u32                     len, remaining;
 223         u32                     ieval;
 224         dma_addr_t              tx_dma, rx_dma;
 225
 226         if (!as->current_transfer)
 227                 xfer = list_entry(msg->transfers.next,
 228                                 struct spi_transfer, transfer_list);
 229         else if (!as->next_transfer)
 230                 xfer = list_entry(as->current_transfer->transfer_list.next,
 231                                 struct spi_transfer, transfer_list);
 232         else
 233                 xfer = NULL;
 234
 235         if (xfer) {
 236                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 237
 238                 len = xfer->len;
 239                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 240                 remaining = xfer->len - len;
 241
 242                 spi_writel(as, RPR, rx_dma);
 243                 spi_writel(as, TPR, tx_dma);
 244
 245                 if (msg->spi->bits_per_word > 8)
 246                         len >>= 1;
 247                 spi_writel(as, RCR, len);
 248                 spi_writel(as, TCR, len);
 249
 250                 dev_dbg(&msg->spi->dev,
 251                         "  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 252                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 253                         xfer->rx_buf, xfer->rx_dma);
 254         } else {
 255                 xfer = as->next_transfer;
 256                 remaining = as->next_remaining_bytes;
 257         }
 258
 259         as->current_transfer = xfer;
 260         as->current_remaining_bytes = remaining;
 261
 262         if (remaining > 0)
 263                 len = remaining;
 264         else if (!atmel_spi_xfer_is_last(msg, xfer)
 265                         && atmel_spi_xfer_can_be_chained(xfer)) {
 266                 xfer = list_entry(xfer->transfer_list.next,
 267                                 struct spi_transfer, transfer_list);
 268                 len = xfer->len;
 269         } else
 270                 xfer = NULL;
 271
 272         as->next_transfer = xfer;
 273
 274         if (xfer) {
 275                 u32     total;
 276
 277                 total = len;
 278                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 279                 as->next_remaining_bytes = total - len;
 280
 281                 spi_writel(as, RNPR, rx_dma);
 282                 spi_writel(as, TNPR, tx_dma);
 283
 284                 if (msg->spi->bits_per_word > 8)
 285                         len >>= 1;
 286                 spi_writel(as, RNCR, len);
 287                 spi_writel(as, TNCR, len);
 288
 289                 dev_dbg(&msg->spi->dev,
 290                         "  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 291                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 292                         xfer->rx_buf, xfer->rx_dma);
 293                 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 294         } else {
 295                 spi_writel(as, RNCR, 0);
 296                 spi_writel(as, TNCR, 0);
 297                 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 298         }
 299
 300         /* REVISIT: We're waiting for ENDRX before we start the next
 301          * transfer because we need to handle some difficult timing
 302          * issues otherwise. If we wait for ENDTX in one transfer and
 303          * then starts waiting for ENDRX in the next, it's difficult
 304          * to tell the difference between the ENDRX interrupt we're
 305          * actually waiting for and the ENDRX interrupt of the
 306          * previous transfer.
 307          *
 308          * It should be doable, though. Just not now...
 309          */
 310         spi_writel(as, IER, ieval);
 311         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 312 }
 313
 314 static void atmel_spi_next_message(struct spi_master *master)
 315 {
 316         struct atmel_spi        *as = spi_master_get_devdata(master);
 317         struct spi_message      *msg;
 318         struct spi_device       *spi;
 319
 320         BUG_ON(as->current_transfer);
 321
 322         msg = list_entry(as->queue.next, struct spi_message, queue);
 323         spi = msg->spi;
 324
 325         dev_dbg(master->dev.parent, "start message %p for %s\n",
 326                         msg, dev_name(&spi->dev));
 327
 328         /* select chip if it's not still active */
 329         if (as->stay) {
 330                 if (as->stay != spi) {
 331                         cs_deactivate(as, as->stay);
 332                         cs_activate(as, spi);
 333                 }
 334                 as->stay = NULL;
 335         } else
 336                 cs_activate(as, spi);
 337
 338         atmel_spi_next_xfer(master, msg);
 339 }
 340
 341 /*
 342  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 343  *  - The buffer is either valid for CPU access, else NULL
 344  *  - If the buffer is valid, so is its DMA addresss
 345  *
 346  * This driver manages the dma addresss unless message->is_dma_mapped.
 347  */
 348 static int
 349 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 350 {
 351         struct device   *dev = &as->pdev->dev;
 352
 353         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 354         if (xfer->tx_buf) {
 355                 xfer->tx_dma = dma_map_single(dev,
 356                                 (void *) xfer->tx_buf, xfer->len,
 357                                 DMA_TO_DEVICE);
 358                 if (dma_mapping_error(dev, xfer->tx_dma))
 359                         return -ENOMEM;
 360         }
 361         if (xfer->rx_buf) {
 362                 xfer->rx_dma = dma_map_single(dev,
 363                                 xfer->rx_buf, xfer->len,
 364                                 DMA_FROM_DEVICE);
 365                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 366                         if (xfer->tx_buf)
 367                                 dma_unmap_single(dev,
 368                                                 xfer->tx_dma, xfer->len,
 369                                                 DMA_TO_DEVICE);
 370                         return -ENOMEM;
 371                 }
 372         }
 373         return 0;
 374 }
 375
 376 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 377                                      struct spi_transfer *xfer)
 378 {
 379         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 380                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 381                                  xfer->len, DMA_TO_DEVICE);
 382         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 383                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 384                                  xfer->len, DMA_FROM_DEVICE);
 385 }
 386
 387 static void
 388 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 389                 struct spi_message *msg, int status, int stay)
 390 {
 391         if (!stay || status < 0)
 392                 cs_deactivate(as, msg->spi);
 393         else
 394                 as->stay = msg->spi;
 395
 396         list_del(&msg->queue);
 397         msg->status = status;
 398
 399         dev_dbg(master->dev.parent,
 400                 "xfer complete: %u bytes transferred\n",
 401                 msg->actual_length);
 402
 403         spin_unlock(&as->lock);
 404         msg->complete(msg->context);
 405         spin_lock(&as->lock);
 406
 407         as->current_transfer = NULL;
 408         as->next_transfer = NULL;
 409
 410         /* continue if needed */
 411         if (list_empty(&as->queue) || as->stopping)
 412                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 413         else
 414                 atmel_spi_next_message(master);
 415 }
 416
 417 static irqreturn_t
 418 atmel_spi_interrupt(int irq, void *dev_id)
 419 {
 420         struct spi_master       *master = dev_id;
 421         struct atmel_spi        *as = spi_master_get_devdata(master);
 422         struct spi_message      *msg;
 423         struct spi_transfer     *xfer;
 424         u32                     status, pending, imr;
 425         int                     ret = IRQ_NONE;
 426
 427         spin_lock(&as->lock);
 428
 429         xfer = as->current_transfer;
 430         msg = list_entry(as->queue.next, struct spi_message, queue);
 431
 432         imr = spi_readl(as, IMR);
 433         status = spi_readl(as, SR);
 434         pending = status & imr;
 435
 436         if (pending & SPI_BIT(OVRES)) {
 437                 int timeout;
 438
 439                 ret = IRQ_HANDLED;
 440
 441                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 442                                      | SPI_BIT(OVRES)));
 443
 444                 /*
 445                  * When we get an overrun, we disregard the current
 446                  * transfer. Data will not be copied back from any
 447                  * bounce buffer and msg->actual_len will not be
 448                  * updated with the last xfer.
 449                  *
 450                  * We will also not process any remaning transfers in
 451                  * the message.
 452                  *
 453                  * First, stop the transfer and unmap the DMA buffers.
 454                  */
 455                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 456                 if (!msg->is_dma_mapped)
 457                         atmel_spi_dma_unmap_xfer(master, xfer);
 458
 459                 /* REVISIT: udelay in irq is unfriendly */
 460                 if (xfer->delay_usecs)
 461                         udelay(xfer->delay_usecs);
 462
 463                 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
 464                          spi_readl(as, TCR), spi_readl(as, RCR));
 465
 466                 /*
 467                  * Clean up DMA registers and make sure the data
 468                  * registers are empty.
 469                  */
 470                 spi_writel(as, RNCR, 0);
 471                 spi_writel(as, TNCR, 0);
 472                 spi_writel(as, RCR, 0);
 473                 spi_writel(as, TCR, 0);
 474                 for (timeout = 1000; timeout; timeout--)
 475                         if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
 476                                 break;
 477                 if (!timeout)
 478                         dev_warn(master->dev.parent,
 479                                  "timeout waiting for TXEMPTY");
 480                 while (spi_readl(as, SR) & SPI_BIT(RDRF))
 481                         spi_readl(as, RDR);
 482
 483                 /* Clear any overrun happening while cleaning up */
 484                 spi_readl(as, SR);
 485
 486                 atmel_spi_msg_done(master, as, msg, -EIO, 0);
 487         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 488                 ret = IRQ_HANDLED;
 489
 490                 spi_writel(as, IDR, pending);
 491
 492                 if (as->current_remaining_bytes == 0) {
 493                         msg->actual_length += xfer->len;
 494
 495                         if (!msg->is_dma_mapped)
 496                                 atmel_spi_dma_unmap_xfer(master, xfer);
 497
 498                         /* REVISIT: udelay in irq is unfriendly */
 499                         if (xfer->delay_usecs)
 500                                 udelay(xfer->delay_usecs);
 501
 502                         if (atmel_spi_xfer_is_last(msg, xfer)) {
 503                                 /* report completed message */
 504                                 atmel_spi_msg_done(master, as, msg, 0,
 505                                                 xfer->cs_change);
 506                         } else {
 507                                 if (xfer->cs_change) {
 508                                         cs_deactivate(as, msg->spi);
 509                                         udelay(1);
 510                                         cs_activate(as, msg->spi);
 511                                 }
 512
 513                                 /*
 514                                  * Not done yet. Submit the next transfer.
 515                                  *
 516                                  * FIXME handle protocol options for xfer
 517                                  */
 518                                 atmel_spi_next_xfer(master, msg);
 519                         }
 520                 } else {
 521                         /*
 522                          * Keep going, we still have data to send in
 523                          * the current transfer.
 524                          */
 525                         atmel_spi_next_xfer(master, msg);
 526                 }
 527         }
 528
 529         spin_unlock(&as->lock);
 530
 531         return ret;
 532 }
 533
 534 static int atmel_spi_setup(struct spi_device *spi)
 535 {
 536         struct atmel_spi        *as;
 537         struct atmel_spi_device *asd;
 538         u32                     scbr, csr;
 539         unsigned int            bits = spi->bits_per_word;
 540         unsigned long           bus_hz;
 541         unsigned int            npcs_pin;
 542         int                     ret;
 543
 544         as = spi_master_get_devdata(spi->master);
 545
 546         if (as->stopping)
 547                 return -ESHUTDOWN;
 548
 549         if (spi->chip_select > spi->master->num_chipselect) {
 550                 dev_dbg(&spi->dev,
 551                                 "setup: invalid chipselect %u (%u defined)\n",
 552                                 spi->chip_select, spi->master->num_chipselect);
 553                 return -EINVAL;
 554         }
 555
 556         if (bits < 8 || bits > 16) {
 557                 dev_dbg(&spi->dev,
 558                                 "setup: invalid bits_per_word %u (8 to 16)\n",
 559                                 bits);
 560                 return -EINVAL;
 561         }
 562
 563         /* see notes above re chipselect */
 564         if (!atmel_spi_is_v2()
 565                         && spi->chip_select == 0
 566                         && (spi->mode & SPI_CS_HIGH)) {
 567                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 568                 return -EINVAL;
 569         }
 570
 571         /* v1 chips start out at half the peripheral bus speed. */
 572         bus_hz = clk_get_rate(as->clk);
 573         if (!atmel_spi_is_v2())
 574                 bus_hz /= 2;
 575
 576         if (spi->max_speed_hz) {
 577                 /*
 578                  * Calculate the lowest divider that satisfies the
 579                  * constraint, assuming div32/fdiv/mbz == 0.
 580                  */
 581                 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
 582
 583                 /*
 584                  * If the resulting divider doesn't fit into the
 585                  * register bitfield, we can't satisfy the constraint.
 586                  */
 587                 if (scbr >= (1 << SPI_SCBR_SIZE)) {
 588                         dev_dbg(&spi->dev,
 589                                 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 590                                 spi->max_speed_hz, scbr, bus_hz/255);
 591                         return -EINVAL;
 592                 }
 593         } else
 594                 /* speed zero means "as slow as possible" */
 595                 scbr = 0xff;
 596
 597         csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
 598         if (spi->mode & SPI_CPOL)
 599                 csr |= SPI_BIT(CPOL);
 600         if (!(spi->mode & SPI_CPHA))
 601                 csr |= SPI_BIT(NCPHA);
 602
 603         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
 604          *
 605          * DLYBCT would add delays between words, slowing down transfers.
 606          * It could potentially be useful to cope with DMA bottlenecks, but
 607          * in those cases it's probably best to just use a lower bitrate.
 608          */
 609         csr |= SPI_BF(DLYBS, 0);
 610         csr |= SPI_BF(DLYBCT, 0);
 611
 612         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
 613         npcs_pin = (unsigned int)spi->controller_data;
 614         asd = spi->controller_state;
 615         if (!asd) {
 616                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
 617                 if (!asd)
 618                         return -ENOMEM;
 619
 620                 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
 621                 if (ret) {
 622                         kfree(asd);
 623                         return ret;
 624                 }
 625
 626                 asd->npcs_pin = npcs_pin;
 627                 spi->controller_state = asd;
 628                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 629         } else {
 630                 unsigned long           flags;
 631
 632                 spin_lock_irqsave(&as->lock, flags);
 633                 if (as->stay == spi)
 634                         as->stay = NULL;
 635                 cs_deactivate(as, spi);
 636                 spin_unlock_irqrestore(&as->lock, flags);
 637         }
 638
 639         asd->csr = csr;
 640
 641         dev_dbg(&spi->dev,
 642                 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 643                 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
 644
 645         if (!atmel_spi_is_v2())
 646                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 647
 648         return 0;
 649 }
 650
 651 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 652 {
 653         struct atmel_spi        *as;
 654         struct spi_transfer     *xfer;
 655         unsigned long           flags;
 656         struct device           *controller = spi->master->dev.parent;
 657
 658         as = spi_master_get_devdata(spi->master);
 659
 660         dev_dbg(controller, "new message %p submitted for %s\n",
 661                         msg, dev_name(&spi->dev));
 662
 663         if (unlikely(list_empty(&msg->transfers)))
 664                 return -EINVAL;
 665
 666         if (as->stopping)
 667                 return -ESHUTDOWN;
 668
 669         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 670                 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
 671                         dev_dbg(&spi->dev, "missing rx or tx buf\n");
 672                         return -EINVAL;
 673                 }
 674
 675                 /* FIXME implement these protocol options!! */
 676                 if (xfer->bits_per_word || xfer->speed_hz) {
 677                         dev_dbg(&spi->dev, "no protocol options yet\n");
 678                         return -ENOPROTOOPT;
 679                 }
 680
 681                 /*
 682                  * DMA map early, for performance (empties dcache ASAP) and
 683                  * better fault reporting.  This is a DMA-only driver.
 684                  *
 685                  * NOTE that if dma_unmap_single() ever starts to do work on
 686                  * platforms supported by this driver, we would need to clean
 687                  * up mappings for previously-mapped transfers.
 688                  */
 689                 if (!msg->is_dma_mapped) {
 690                         if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 691                                 return -ENOMEM;
 692                 }
 693         }
 694
 695 #ifdef VERBOSE
 696         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 697                 dev_dbg(controller,
 698                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 699                         xfer, xfer->len,
 700                         xfer->tx_buf, xfer->tx_dma,
 701                         xfer->rx_buf, xfer->rx_dma);
 702         }
 703 #endif
 704
 705         msg->status = -EINPROGRESS;
 706         msg->actual_length = 0;
 707
 708         spin_lock_irqsave(&as->lock, flags);
 709         list_add_tail(&msg->queue, &as->queue);
 710         if (!as->current_transfer)
 711                 atmel_spi_next_message(spi->master);
 712         spin_unlock_irqrestore(&as->lock, flags);
 713
 714         return 0;
 715 }
 716
 717 static void atmel_spi_cleanup(struct spi_device *spi)
 718 {
 719         struct atmel_spi        *as = spi_master_get_devdata(spi->master);
 720         struct atmel_spi_device *asd = spi->controller_state;
 721         unsigned                gpio = (unsigned) spi->controller_data;
 722         unsigned long           flags;
 723
 724         if (!asd)
 725                 return;
 726
 727         spin_lock_irqsave(&as->lock, flags);
 728         if (as->stay == spi) {
 729                 as->stay = NULL;
 730                 cs_deactivate(as, spi);
 731         }
 732         spin_unlock_irqrestore(&as->lock, flags);
 733
 734         spi->controller_state = NULL;
 735         gpio_free(gpio);
 736         kfree(asd);
 737 }
 738
 739 /*-------------------------------------------------------------------------*/
 740
 741 static int __init atmel_spi_probe(struct platform_device *pdev)
 742 {
 743         struct resource         *regs;
 744         int                     irq;
 745         struct clk              *clk;
 746         int                     ret;
 747         struct spi_master       *master;
 748         struct atmel_spi        *as;
 749
 750         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 751         if (!regs)
 752                 return -ENXIO;
 753
 754         irq = platform_get_irq(pdev, 0);
 755         if (irq < 0)
 756                 return irq;
 757
 758         clk = clk_get(&pdev->dev, "spi_clk");
 759         if (IS_ERR(clk))
 760                 return PTR_ERR(clk);
 761
 762         /* setup spi core then atmel-specific driver state */
 763         ret = -ENOMEM;
 764         master = spi_alloc_master(&pdev->dev, sizeof *as);
 765         if (!master)
 766                 goto out_free;
 767
 768         /* the spi->mode bits understood by this driver: */
 769         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 770
 771         master->bus_num = pdev->id;
 772         master->num_chipselect = 4;
 773         master->setup = atmel_spi_setup;
 774         master->transfer = atmel_spi_transfer;
 775         master->cleanup = atmel_spi_cleanup;
 776         platform_set_drvdata(pdev, master);
 777
 778         as = spi_master_get_devdata(master);
 779
 780         /*
 781          * Scratch buffer is used for throwaway rx and tx data.
 782          * It's coherent to minimize dcache pollution.
 783          */
 784         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 785                                         &as->buffer_dma, GFP_KERNEL);
 786         if (!as->buffer)
 787                 goto out_free;
 788
 789         spin_lock_init(&as->lock);
 790         INIT_LIST_HEAD(&as->queue);
 791         as->pdev = pdev;
 792         as->regs = ioremap(regs->start, resource_size(regs));
 793         if (!as->regs)
 794                 goto out_free_buffer;
 795         as->irq = irq;
 796         as->clk = clk;
 797
 798         ret = request_irq(irq, atmel_spi_interrupt, 0,
 799                         dev_name(&pdev->dev), master);
 800         if (ret)
 801                 goto out_unmap_regs;
 802
 803         /* Initialize the hardware */
 804         clk_enable(clk);
 805         spi_writel(as, CR, SPI_BIT(SWRST));
 806         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 807         spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 808         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 809         spi_writel(as, CR, SPI_BIT(SPIEN));
 810
 811         /* go! */
 812         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 813                         (unsigned long)regs->start, irq);
 814
 815         ret = spi_register_master(master);
 816         if (ret)
 817                 goto out_reset_hw;
 818
 819         return 0;
 820
 821 out_reset_hw:
 822         spi_writel(as, CR, SPI_BIT(SWRST));
 823         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 824         clk_disable(clk);
 825         free_irq(irq, master);
 826 out_unmap_regs:
 827         iounmap(as->regs);
 828 out_free_buffer:
 829         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 830                         as->buffer_dma);
 831 out_free:
 832         clk_put(clk);
 833         spi_master_put(master);
 834         return ret;
 835 }
 836
 837 static int __exit atmel_spi_remove(struct platform_device *pdev)
 838 {
 839         struct spi_master       *master = platform_get_drvdata(pdev);
 840         struct atmel_spi        *as = spi_master_get_devdata(master);
 841         struct spi_message      *msg;
 842
 843         /* reset the hardware and block queue progress */
 844         spin_lock_irq(&as->lock);
 845         as->stopping = 1;
 846         spi_writel(as, CR, SPI_BIT(SWRST));
 847         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 848         spi_readl(as, SR);
 849         spin_unlock_irq(&as->lock);
 850
 851         /* Terminate remaining queued transfers */
 852         list_for_each_entry(msg, &as->queue, queue) {
 853                 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
 854                  * but we shouldn't depend on that...
 855                  */
 856                 msg->status = -ESHUTDOWN;
 857                 msg->complete(msg->context);
 858         }
 859
 860         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 861                         as->buffer_dma);
 862
 863         clk_disable(as->clk);
 864         clk_put(as->clk);
 865         free_irq(as->irq, master);
 866         iounmap(as->regs);
 867
 868         spi_unregister_master(master);
 869
 870         return 0;
 871 }
 872
 873 #ifdef  CONFIG_PM
 874
 875 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 876 {
 877         struct spi_master       *master = platform_get_drvdata(pdev);
 878         struct atmel_spi        *as = spi_master_get_devdata(master);
 879
 880         clk_disable(as->clk);
 881         return 0;
 882 }
 883
 884 static int atmel_spi_resume(struct platform_device *pdev)
 885 {
 886         struct spi_master       *master = platform_get_drvdata(pdev);
 887         struct atmel_spi        *as = spi_master_get_devdata(master);
 888
 889         clk_enable(as->clk);
 890         return 0;
 891 }
 892
 893 #else
 894 #define atmel_spi_suspend       NULL
 895 #define atmel_spi_resume        NULL
 896 #endif
 897
 898
 899 static struct platform_driver atmel_spi_driver = {
 900         .driver         = {
 901                 .name   = "atmel_spi",
 902                 .owner  = THIS_MODULE,
 903         },
 904         .suspend        = atmel_spi_suspend,
 905         .resume         = atmel_spi_resume,
 906         .remove         = __exit_p(atmel_spi_remove),
 907 };
 908
 909 static int __init atmel_spi_init(void)
 910 {
 911         return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
 912 }
 913 module_init(atmel_spi_init);
 914
 915 static void __exit atmel_spi_exit(void)
 916 {
 917         platform_driver_unregister(&atmel_spi_driver);
 918 }
 919 module_exit(atmel_spi_exit);
 920
 921 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
 922 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 923 MODULE_LICENSE("GPL");
 924 MODULE_ALIAS("platform:atmel_spi");