drivers/spi/atmel_spi.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21
  22 #include <asm/io.h>
  23 #include <mach/board.h>
  24 #include <mach/gpio.h>
  25 #include <mach/cpu.h>
  26
  27 #include "atmel_spi.h"
  28
  29 /*
  30  * The core SPI transfer engine just talks to a register bank to set up
  31  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
  32  * framework provides the base clock, subdivided for each spi_device.
  33  */
  34 struct atmel_spi {
  35         spinlock_t              lock;
  36
  37         void __iomem            *regs;
  38         int                     irq;
  39         struct clk              *clk;
  40         struct platform_device  *pdev;
  41         struct spi_device       *stay;
  42
  43         u8                      stopping;
  44         struct list_head        queue;
  45         struct spi_transfer     *current_transfer;
  46         unsigned long           current_remaining_bytes;
  47         struct spi_transfer     *next_transfer;
  48         unsigned long           next_remaining_bytes;
  49
  50         void                    *buffer;
  51         dma_addr_t              buffer_dma;
  52 };
  53
  54 #define BUFFER_SIZE             PAGE_SIZE
  55 #define INVALID_DMA_ADDRESS     0xffffffff
  56
  57 /*
  58  * Version 2 of the SPI controller has
  59  *  - CR.LASTXFER
  60  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  61  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  62  *  - SPI_CSRx.CSAAT
  63  *  - SPI_CSRx.SBCR allows faster clocking
  64  *
  65  * We can determine the controller version by reading the VERSION
  66  * register, but I haven't checked that it exists on all chips, and
  67  * this is cheaper anyway.
  68  */
  69 static bool atmel_spi_is_v2(void)
  70 {
  71         return !cpu_is_at91rm9200();
  72 }
  73
  74 /*
  75  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  76  * they assume that spi slave device state will not change on deselect, so
  77  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
  78  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
  79  * controllers have CSAAT and friends.
  80  *
  81  * Since the CSAAT functionality is a bit weird on newer controllers as
  82  * well, we use GPIO to control nCSx pins on all controllers, updating
  83  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
  84  * support active-high chipselects despite the controller's belief that
  85  * only active-low devices/systems exists.
  86  *
  87  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
  88  * right when driven with GPIO.  ("Mode Fault does not allow more than one
  89  * Master on Chip Select 0.")  No workaround exists for that ... so for
  90  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
  91  * and (c) will trigger that first erratum in some cases.
  92  */
  93
  94 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
  95 {
  96         unsigned gpio = (unsigned) spi->controller_data;
  97         unsigned active = spi->mode & SPI_CS_HIGH;
  98         u32 mr;
  99         int i;
 100         u32 csr;
 101         u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 102
 103         /* Make sure clock polarity is correct */
 104         for (i = 0; i < spi->master->num_chipselect; i++) {
 105                 csr = spi_readl(as, CSR0 + 4 * i);
 106                 if ((csr ^ cpol) & SPI_BIT(CPOL))
 107                         spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
 108         }
 109
 110         mr = spi_readl(as, MR);
 111         mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 112
 113         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 114                         gpio, active ? " (high)" : "",
 115                         mr);
 116
 117         if (atmel_spi_is_v2() || spi->chip_select != 0)
 118                 gpio_set_value(gpio, active);
 119         spi_writel(as, MR, mr);
 120 }
 121
 122 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 123 {
 124         unsigned gpio = (unsigned) spi->controller_data;
 125         unsigned active = spi->mode & SPI_CS_HIGH;
 126         u32 mr;
 127
 128         /* only deactivate *this* device; sometimes transfers to
 129          * another device may be active when this routine is called.
 130          */
 131         mr = spi_readl(as, MR);
 132         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 133                 mr = SPI_BFINS(PCS, 0xf, mr);
 134                 spi_writel(as, MR, mr);
 135         }
 136
 137         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 138                         gpio, active ? " (low)" : "",
 139                         mr);
 140
 141         if (atmel_spi_is_v2() || spi->chip_select != 0)
 142                 gpio_set_value(gpio, !active);
 143 }
 144
 145 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 146                                         struct spi_transfer *xfer)
 147 {
 148         return msg->transfers.prev == &xfer->transfer_list;
 149 }
 150
 151 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 152 {
 153         return xfer->delay_usecs == 0 && !xfer->cs_change;
 154 }
 155
 156 static void atmel_spi_next_xfer_data(struct spi_master *master,
 157                                 struct spi_transfer *xfer,
 158                                 dma_addr_t *tx_dma,
 159                                 dma_addr_t *rx_dma,
 160                                 u32 *plen)
 161 {
 162         struct atmel_spi        *as = spi_master_get_devdata(master);
 163         u32                     len = *plen;
 164
 165         /* use scratch buffer only when rx or tx data is unspecified */
 166         if (xfer->rx_buf)
 167                 *rx_dma = xfer->rx_dma + xfer->len - len;
 168         else {
 169                 *rx_dma = as->buffer_dma;
 170                 if (len > BUFFER_SIZE)
 171                         len = BUFFER_SIZE;
 172         }
 173         if (xfer->tx_buf)
 174                 *tx_dma = xfer->tx_dma + xfer->len - len;
 175         else {
 176                 *tx_dma = as->buffer_dma;
 177                 if (len > BUFFER_SIZE)
 178                         len = BUFFER_SIZE;
 179                 memset(as->buffer, 0, len);
 180                 dma_sync_single_for_device(&as->pdev->dev,
 181                                 as->buffer_dma, len, DMA_TO_DEVICE);
 182         }
 183
 184         *plen = len;
 185 }
 186
 187 /*
 188  * Submit next transfer for DMA.
 189  * lock is held, spi irq is blocked
 190  */
 191 static void atmel_spi_next_xfer(struct spi_master *master,
 192                                 struct spi_message *msg)
 193 {
 194         struct atmel_spi        *as = spi_master_get_devdata(master);
 195         struct spi_transfer     *xfer;
 196         u32                     len, remaining;
 197         u32                     ieval;
 198         dma_addr_t              tx_dma, rx_dma;
 199
 200         if (!as->current_transfer)
 201                 xfer = list_entry(msg->transfers.next,
 202                                 struct spi_transfer, transfer_list);
 203         else if (!as->next_transfer)
 204                 xfer = list_entry(as->current_transfer->transfer_list.next,
 205                                 struct spi_transfer, transfer_list);
 206         else
 207                 xfer = NULL;
 208
 209         if (xfer) {
 210                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 211
 212                 len = xfer->len;
 213                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 214                 remaining = xfer->len - len;
 215
 216                 spi_writel(as, RPR, rx_dma);
 217                 spi_writel(as, TPR, tx_dma);
 218
 219                 if (msg->spi->bits_per_word > 8)
 220                         len >>= 1;
 221                 spi_writel(as, RCR, len);
 222                 spi_writel(as, TCR, len);
 223
 224                 dev_dbg(&msg->spi->dev,
 225                         "  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 226                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 227                         xfer->rx_buf, xfer->rx_dma);
 228         } else {
 229                 xfer = as->next_transfer;
 230                 remaining = as->next_remaining_bytes;
 231         }
 232
 233         as->current_transfer = xfer;
 234         as->current_remaining_bytes = remaining;
 235
 236         if (remaining > 0)
 237                 len = remaining;
 238         else if (!atmel_spi_xfer_is_last(msg, xfer)
 239                         && atmel_spi_xfer_can_be_chained(xfer)) {
 240                 xfer = list_entry(xfer->transfer_list.next,
 241                                 struct spi_transfer, transfer_list);
 242                 len = xfer->len;
 243         } else
 244                 xfer = NULL;
 245
 246         as->next_transfer = xfer;
 247
 248         if (xfer) {
 249                 u32     total;
 250
 251                 total = len;
 252                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 253                 as->next_remaining_bytes = total - len;
 254
 255                 spi_writel(as, RNPR, rx_dma);
 256                 spi_writel(as, TNPR, tx_dma);
 257
 258                 if (msg->spi->bits_per_word > 8)
 259                         len >>= 1;
 260                 spi_writel(as, RNCR, len);
 261                 spi_writel(as, TNCR, len);
 262
 263                 dev_dbg(&msg->spi->dev,
 264                         "  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 265                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 266                         xfer->rx_buf, xfer->rx_dma);
 267                 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 268         } else {
 269                 spi_writel(as, RNCR, 0);
 270                 spi_writel(as, TNCR, 0);
 271                 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 272         }
 273
 274         /* REVISIT: We're waiting for ENDRX before we start the next
 275          * transfer because we need to handle some difficult timing
 276          * issues otherwise. If we wait for ENDTX in one transfer and
 277          * then starts waiting for ENDRX in the next, it's difficult
 278          * to tell the difference between the ENDRX interrupt we're
 279          * actually waiting for and the ENDRX interrupt of the
 280          * previous transfer.
 281          *
 282          * It should be doable, though. Just not now...
 283          */
 284         spi_writel(as, IER, ieval);
 285         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 286 }
 287
 288 static void atmel_spi_next_message(struct spi_master *master)
 289 {
 290         struct atmel_spi        *as = spi_master_get_devdata(master);
 291         struct spi_message      *msg;
 292         struct spi_device       *spi;
 293
 294         BUG_ON(as->current_transfer);
 295
 296         msg = list_entry(as->queue.next, struct spi_message, queue);
 297         spi = msg->spi;
 298
 299         dev_dbg(master->dev.parent, "start message %p for %s\n",
 300                         msg, spi->dev.bus_id);
 301
 302         /* select chip if it's not still active */
 303         if (as->stay) {
 304                 if (as->stay != spi) {
 305                         cs_deactivate(as, as->stay);
 306                         cs_activate(as, spi);
 307                 }
 308                 as->stay = NULL;
 309         } else
 310                 cs_activate(as, spi);
 311
 312         atmel_spi_next_xfer(master, msg);
 313 }
 314
 315 /*
 316  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 317  *  - The buffer is either valid for CPU access, else NULL
 318  *  - If the buffer is valid, so is its DMA addresss
 319  *
 320  * This driver manages the dma addresss unless message->is_dma_mapped.
 321  */
 322 static int
 323 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 324 {
 325         struct device   *dev = &as->pdev->dev;
 326
 327         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 328         if (xfer->tx_buf) {
 329                 xfer->tx_dma = dma_map_single(dev,
 330                                 (void *) xfer->tx_buf, xfer->len,
 331                                 DMA_TO_DEVICE);
 332                 if (dma_mapping_error(dev, xfer->tx_dma))
 333                         return -ENOMEM;
 334         }
 335         if (xfer->rx_buf) {
 336                 xfer->rx_dma = dma_map_single(dev,
 337                                 xfer->rx_buf, xfer->len,
 338                                 DMA_FROM_DEVICE);
 339                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 340                         if (xfer->tx_buf)
 341                                 dma_unmap_single(dev,
 342                                                 xfer->tx_dma, xfer->len,
 343                                                 DMA_TO_DEVICE);
 344                         return -ENOMEM;
 345                 }
 346         }
 347         return 0;
 348 }
 349
 350 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 351                                      struct spi_transfer *xfer)
 352 {
 353         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 354                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 355                                  xfer->len, DMA_TO_DEVICE);
 356         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 357                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 358                                  xfer->len, DMA_FROM_DEVICE);
 359 }
 360
 361 static void
 362 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 363                 struct spi_message *msg, int status, int stay)
 364 {
 365         if (!stay || status < 0)
 366                 cs_deactivate(as, msg->spi);
 367         else
 368                 as->stay = msg->spi;
 369
 370         list_del(&msg->queue);
 371         msg->status = status;
 372
 373         dev_dbg(master->dev.parent,
 374                 "xfer complete: %u bytes transferred\n",
 375                 msg->actual_length);
 376
 377         spin_unlock(&as->lock);
 378         msg->complete(msg->context);
 379         spin_lock(&as->lock);
 380
 381         as->current_transfer = NULL;
 382         as->next_transfer = NULL;
 383
 384         /* continue if needed */
 385         if (list_empty(&as->queue) || as->stopping)
 386                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 387         else
 388                 atmel_spi_next_message(master);
 389 }
 390
 391 static irqreturn_t
 392 atmel_spi_interrupt(int irq, void *dev_id)
 393 {
 394         struct spi_master       *master = dev_id;
 395         struct atmel_spi        *as = spi_master_get_devdata(master);
 396         struct spi_message      *msg;
 397         struct spi_transfer     *xfer;
 398         u32                     status, pending, imr;
 399         int                     ret = IRQ_NONE;
 400
 401         spin_lock(&as->lock);
 402
 403         xfer = as->current_transfer;
 404         msg = list_entry(as->queue.next, struct spi_message, queue);
 405
 406         imr = spi_readl(as, IMR);
 407         status = spi_readl(as, SR);
 408         pending = status & imr;
 409
 410         if (pending & SPI_BIT(OVRES)) {
 411                 int timeout;
 412
 413                 ret = IRQ_HANDLED;
 414
 415                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 416                                      | SPI_BIT(OVRES)));
 417
 418                 /*
 419                  * When we get an overrun, we disregard the current
 420                  * transfer. Data will not be copied back from any
 421                  * bounce buffer and msg->actual_len will not be
 422                  * updated with the last xfer.
 423                  *
 424                  * We will also not process any remaning transfers in
 425                  * the message.
 426                  *
 427                  * First, stop the transfer and unmap the DMA buffers.
 428                  */
 429                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 430                 if (!msg->is_dma_mapped)
 431                         atmel_spi_dma_unmap_xfer(master, xfer);
 432
 433                 /* REVISIT: udelay in irq is unfriendly */
 434                 if (xfer->delay_usecs)
 435                         udelay(xfer->delay_usecs);
 436
 437                 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
 438                          spi_readl(as, TCR), spi_readl(as, RCR));
 439
 440                 /*
 441                  * Clean up DMA registers and make sure the data
 442                  * registers are empty.
 443                  */
 444                 spi_writel(as, RNCR, 0);
 445                 spi_writel(as, TNCR, 0);
 446                 spi_writel(as, RCR, 0);
 447                 spi_writel(as, TCR, 0);
 448                 for (timeout = 1000; timeout; timeout--)
 449                         if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
 450                                 break;
 451                 if (!timeout)
 452                         dev_warn(master->dev.parent,
 453                                  "timeout waiting for TXEMPTY");
 454                 while (spi_readl(as, SR) & SPI_BIT(RDRF))
 455                         spi_readl(as, RDR);
 456
 457                 /* Clear any overrun happening while cleaning up */
 458                 spi_readl(as, SR);
 459
 460                 atmel_spi_msg_done(master, as, msg, -EIO, 0);
 461         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 462                 ret = IRQ_HANDLED;
 463
 464                 spi_writel(as, IDR, pending);
 465
 466                 if (as->current_remaining_bytes == 0) {
 467                         msg->actual_length += xfer->len;
 468
 469                         if (!msg->is_dma_mapped)
 470                                 atmel_spi_dma_unmap_xfer(master, xfer);
 471
 472                         /* REVISIT: udelay in irq is unfriendly */
 473                         if (xfer->delay_usecs)
 474                                 udelay(xfer->delay_usecs);
 475
 476                         if (atmel_spi_xfer_is_last(msg, xfer)) {
 477                                 /* report completed message */
 478                                 atmel_spi_msg_done(master, as, msg, 0,
 479                                                 xfer->cs_change);
 480                         } else {
 481                                 if (xfer->cs_change) {
 482                                         cs_deactivate(as, msg->spi);
 483                                         udelay(1);
 484                                         cs_activate(as, msg->spi);
 485                                 }
 486
 487                                 /*
 488                                  * Not done yet. Submit the next transfer.
 489                                  *
 490                                  * FIXME handle protocol options for xfer
 491                                  */
 492                                 atmel_spi_next_xfer(master, msg);
 493                         }
 494                 } else {
 495                         /*
 496                          * Keep going, we still have data to send in
 497                          * the current transfer.
 498                          */
 499                         atmel_spi_next_xfer(master, msg);
 500                 }
 501         }
 502
 503         spin_unlock(&as->lock);
 504
 505         return ret;
 506 }
 507
 508 /* the spi->mode bits understood by this driver: */
 509 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 510
 511 static int atmel_spi_setup(struct spi_device *spi)
 512 {
 513         struct atmel_spi        *as;
 514         u32                     scbr, csr;
 515         unsigned int            bits = spi->bits_per_word;
 516         unsigned long           bus_hz;
 517         unsigned int            npcs_pin;
 518         int                     ret;
 519
 520         as = spi_master_get_devdata(spi->master);
 521
 522         if (as->stopping)
 523                 return -ESHUTDOWN;
 524
 525         if (spi->chip_select > spi->master->num_chipselect) {
 526                 dev_dbg(&spi->dev,
 527                                 "setup: invalid chipselect %u (%u defined)\n",
 528                                 spi->chip_select, spi->master->num_chipselect);
 529                 return -EINVAL;
 530         }
 531
 532         if (bits == 0)
 533                 bits = 8;
 534         if (bits < 8 || bits > 16) {
 535                 dev_dbg(&spi->dev,
 536                                 "setup: invalid bits_per_word %u (8 to 16)\n",
 537                                 bits);
 538                 return -EINVAL;
 539         }
 540
 541         if (spi->mode & ~MODEBITS) {
 542                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 543                         spi->mode & ~MODEBITS);
 544                 return -EINVAL;
 545         }
 546
 547         /* see notes above re chipselect */
 548         if (!atmel_spi_is_v2()
 549                         && spi->chip_select == 0
 550                         && (spi->mode & SPI_CS_HIGH)) {
 551                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 552                 return -EINVAL;
 553         }
 554
 555         /* v1 chips start out at half the peripheral bus speed. */
 556         bus_hz = clk_get_rate(as->clk);
 557         if (!atmel_spi_is_v2())
 558                 bus_hz /= 2;
 559
 560         if (spi->max_speed_hz) {
 561                 /*
 562                  * Calculate the lowest divider that satisfies the
 563                  * constraint, assuming div32/fdiv/mbz == 0.
 564                  */
 565                 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
 566
 567                 /*
 568                  * If the resulting divider doesn't fit into the
 569                  * register bitfield, we can't satisfy the constraint.
 570                  */
 571                 if (scbr >= (1 << SPI_SCBR_SIZE)) {
 572                         dev_dbg(&spi->dev,
 573                                 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 574                                 spi->max_speed_hz, scbr, bus_hz/255);
 575                         return -EINVAL;
 576                 }
 577         } else
 578                 /* speed zero means "as slow as possible" */
 579                 scbr = 0xff;
 580
 581         csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
 582         if (spi->mode & SPI_CPOL)
 583                 csr |= SPI_BIT(CPOL);
 584         if (!(spi->mode & SPI_CPHA))
 585                 csr |= SPI_BIT(NCPHA);
 586
 587         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
 588          *
 589          * DLYBCT would add delays between words, slowing down transfers.
 590          * It could potentially be useful to cope with DMA bottlenecks, but
 591          * in those cases it's probably best to just use a lower bitrate.
 592          */
 593         csr |= SPI_BF(DLYBS, 0);
 594         csr |= SPI_BF(DLYBCT, 0);
 595
 596         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
 597         npcs_pin = (unsigned int)spi->controller_data;
 598         if (!spi->controller_state) {
 599                 ret = gpio_request(npcs_pin, spi->dev.bus_id);
 600                 if (ret)
 601                         return ret;
 602                 spi->controller_state = (void *)npcs_pin;
 603                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 604         } else {
 605                 unsigned long           flags;
 606
 607                 spin_lock_irqsave(&as->lock, flags);
 608                 if (as->stay == spi)
 609                         as->stay = NULL;
 610                 cs_deactivate(as, spi);
 611                 spin_unlock_irqrestore(&as->lock, flags);
 612         }
 613
 614         dev_dbg(&spi->dev,
 615                 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 616                 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
 617
 618         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 619
 620         return 0;
 621 }
 622
 623 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 624 {
 625         struct atmel_spi        *as;
 626         struct spi_transfer     *xfer;
 627         unsigned long           flags;
 628         struct device           *controller = spi->master->dev.parent;
 629
 630         as = spi_master_get_devdata(spi->master);
 631
 632         dev_dbg(controller, "new message %p submitted for %s\n",
 633                         msg, spi->dev.bus_id);
 634
 635         if (unlikely(list_empty(&msg->transfers)
 636                         || !spi->max_speed_hz))
 637                 return -EINVAL;
 638
 639         if (as->stopping)
 640                 return -ESHUTDOWN;
 641
 642         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 643                 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
 644                         dev_dbg(&spi->dev, "missing rx or tx buf\n");
 645                         return -EINVAL;
 646                 }
 647
 648                 /* FIXME implement these protocol options!! */
 649                 if (xfer->bits_per_word || xfer->speed_hz) {
 650                         dev_dbg(&spi->dev, "no protocol options yet\n");
 651                         return -ENOPROTOOPT;
 652                 }
 653
 654                 /*
 655                  * DMA map early, for performance (empties dcache ASAP) and
 656                  * better fault reporting.  This is a DMA-only driver.
 657                  *
 658                  * NOTE that if dma_unmap_single() ever starts to do work on
 659                  * platforms supported by this driver, we would need to clean
 660                  * up mappings for previously-mapped transfers.
 661                  */
 662                 if (!msg->is_dma_mapped) {
 663                         if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 664                                 return -ENOMEM;
 665                 }
 666         }
 667
 668 #ifdef VERBOSE
 669         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 670                 dev_dbg(controller,
 671                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 672                         xfer, xfer->len,
 673                         xfer->tx_buf, xfer->tx_dma,
 674                         xfer->rx_buf, xfer->rx_dma);
 675         }
 676 #endif
 677
 678         msg->status = -EINPROGRESS;
 679         msg->actual_length = 0;
 680
 681         spin_lock_irqsave(&as->lock, flags);
 682         list_add_tail(&msg->queue, &as->queue);
 683         if (!as->current_transfer)
 684                 atmel_spi_next_message(spi->master);
 685         spin_unlock_irqrestore(&as->lock, flags);
 686
 687         return 0;
 688 }
 689
 690 static void atmel_spi_cleanup(struct spi_device *spi)
 691 {
 692         struct atmel_spi        *as = spi_master_get_devdata(spi->master);
 693         unsigned                gpio = (unsigned) spi->controller_data;
 694         unsigned long           flags;
 695
 696         if (!spi->controller_state)
 697                 return;
 698
 699         spin_lock_irqsave(&as->lock, flags);
 700         if (as->stay == spi) {
 701                 as->stay = NULL;
 702                 cs_deactivate(as, spi);
 703         }
 704         spin_unlock_irqrestore(&as->lock, flags);
 705
 706         gpio_free(gpio);
 707 }
 708
 709 /*-------------------------------------------------------------------------*/
 710
 711 static int __init atmel_spi_probe(struct platform_device *pdev)
 712 {
 713         struct resource         *regs;
 714         int                     irq;
 715         struct clk              *clk;
 716         int                     ret;
 717         struct spi_master       *master;
 718         struct atmel_spi        *as;
 719
 720         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 721         if (!regs)
 722                 return -ENXIO;
 723
 724         irq = platform_get_irq(pdev, 0);
 725         if (irq < 0)
 726                 return irq;
 727
 728         clk = clk_get(&pdev->dev, "spi_clk");
 729         if (IS_ERR(clk))
 730                 return PTR_ERR(clk);
 731
 732         /* setup spi core then atmel-specific driver state */
 733         ret = -ENOMEM;
 734         master = spi_alloc_master(&pdev->dev, sizeof *as);
 735         if (!master)
 736                 goto out_free;
 737
 738         master->bus_num = pdev->id;
 739         master->num_chipselect = 4;
 740         master->setup = atmel_spi_setup;
 741         master->transfer = atmel_spi_transfer;
 742         master->cleanup = atmel_spi_cleanup;
 743         platform_set_drvdata(pdev, master);
 744
 745         as = spi_master_get_devdata(master);
 746
 747         /*
 748          * Scratch buffer is used for throwaway rx and tx data.
 749          * It's coherent to minimize dcache pollution.
 750          */
 751         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 752                                         &as->buffer_dma, GFP_KERNEL);
 753         if (!as->buffer)
 754                 goto out_free;
 755
 756         spin_lock_init(&as->lock);
 757         INIT_LIST_HEAD(&as->queue);
 758         as->pdev = pdev;
 759         as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 760         if (!as->regs)
 761                 goto out_free_buffer;
 762         as->irq = irq;
 763         as->clk = clk;
 764
 765         ret = request_irq(irq, atmel_spi_interrupt, 0,
 766                         pdev->dev.bus_id, master);
 767         if (ret)
 768                 goto out_unmap_regs;
 769
 770         /* Initialize the hardware */
 771         clk_enable(clk);
 772         spi_writel(as, CR, SPI_BIT(SWRST));
 773         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 774         spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 775         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 776         spi_writel(as, CR, SPI_BIT(SPIEN));
 777
 778         /* go! */
 779         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 780                         (unsigned long)regs->start, irq);
 781
 782         ret = spi_register_master(master);
 783         if (ret)
 784                 goto out_reset_hw;
 785
 786         return 0;
 787
 788 out_reset_hw:
 789         spi_writel(as, CR, SPI_BIT(SWRST));
 790         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 791         clk_disable(clk);
 792         free_irq(irq, master);
 793 out_unmap_regs:
 794         iounmap(as->regs);
 795 out_free_buffer:
 796         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 797                         as->buffer_dma);
 798 out_free:
 799         clk_put(clk);
 800         spi_master_put(master);
 801         return ret;
 802 }
 803
 804 static int __exit atmel_spi_remove(struct platform_device *pdev)
 805 {
 806         struct spi_master       *master = platform_get_drvdata(pdev);
 807         struct atmel_spi        *as = spi_master_get_devdata(master);
 808         struct spi_message      *msg;
 809
 810         /* reset the hardware and block queue progress */
 811         spin_lock_irq(&as->lock);
 812         as->stopping = 1;
 813         spi_writel(as, CR, SPI_BIT(SWRST));
 814         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 815         spi_readl(as, SR);
 816         spin_unlock_irq(&as->lock);
 817
 818         /* Terminate remaining queued transfers */
 819         list_for_each_entry(msg, &as->queue, queue) {
 820                 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
 821                  * but we shouldn't depend on that...
 822                  */
 823                 msg->status = -ESHUTDOWN;
 824                 msg->complete(msg->context);
 825         }
 826
 827         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 828                         as->buffer_dma);
 829
 830         clk_disable(as->clk);
 831         clk_put(as->clk);
 832         free_irq(as->irq, master);
 833         iounmap(as->regs);
 834
 835         spi_unregister_master(master);
 836
 837         return 0;
 838 }
 839
 840 #ifdef  CONFIG_PM
 841
 842 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 843 {
 844         struct spi_master       *master = platform_get_drvdata(pdev);
 845         struct atmel_spi        *as = spi_master_get_devdata(master);
 846
 847         clk_disable(as->clk);
 848         return 0;
 849 }
 850
 851 static int atmel_spi_resume(struct platform_device *pdev)
 852 {
 853         struct spi_master       *master = platform_get_drvdata(pdev);
 854         struct atmel_spi        *as = spi_master_get_devdata(master);
 855
 856         clk_enable(as->clk);
 857         return 0;
 858 }
 859
 860 #else
 861 #define atmel_spi_suspend       NULL
 862 #define atmel_spi_resume        NULL
 863 #endif
 864
 865
 866 static struct platform_driver atmel_spi_driver = {
 867         .driver         = {
 868                 .name   = "atmel_spi",
 869                 .owner  = THIS_MODULE,
 870         },
 871         .suspend        = atmel_spi_suspend,
 872         .resume         = atmel_spi_resume,
 873         .remove         = __exit_p(atmel_spi_remove),
 874 };
 875
 876 static int __init atmel_spi_init(void)
 877 {
 878         return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
 879 }
 880 module_init(atmel_spi_init);
 881
 882 static void __exit atmel_spi_exit(void)
 883 {
 884         platform_driver_unregister(&atmel_spi_driver);
 885 }
 886 module_exit(atmel_spi_exit);
 887
 888 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
 889 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 890 MODULE_LICENSE("GPL");
 891 MODULE_ALIAS("platform:atmel_spi");