2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/errno.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/resource.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/completion.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #include <asm/mach-au1x00/au1xxx_psc.h>
36 #include <asm/mach-au1x00/au1xxx_dbdma.h>
38 #include <asm/mach-au1x00/au1550_spi.h>
40 static unsigned usedma = 1;
41 module_param(usedma, uint, 0644);
44 #define AU1550_SPI_DEBUG_LOOPBACK
48 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
49 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
52 struct spi_bitbang bitbang;
54 volatile psc_spi_t __iomem *regs;
65 void (*rx_word)(struct au1550_spi *hw);
66 void (*tx_word)(struct au1550_spi *hw);
67 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
68 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
70 struct completion master_done;
79 unsigned dma_rx_tmpbuf_size;
80 u32 dma_rx_tmpbuf_addr;
82 struct spi_master *master;
84 struct au1550_spi_info *pdata;
85 struct resource *ioarea;
89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
90 static dbdev_tab_t au1550_spi_mem_dbdev =
92 .dev_id = DBDMA_MEM_CHAN,
93 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
96 .dev_physaddr = 0x00000000,
101 static int ddma_memid; /* id to above mem dma device */
103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
107 * compute BRG and DIV bits to setup spi clock based on main input clock rate
108 * that was specified in platform data structure
109 * according to au1550 datasheet:
110 * psc_tempclk = psc_mainclk / (2 << DIV)
111 * spiclk = psc_tempclk / (2 * (BRG + 1))
112 * BRG valid range is 4..63
113 * DIV valid range is 0..3
115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
117 u32 mainclk_hz = hw->pdata->mainclk_hz;
120 for (div = 0; div < 4; div++) {
121 brg = mainclk_hz / speed_hz / (4 << div);
122 /* now we have BRG+1 in brg, so count with that */
124 brg = (4 + 1); /* speed_hz too big */
125 break; /* set lowest brg (div is == 0) */
128 break; /* we have valid brg and div */
131 div = 3; /* speed_hz too small */
132 brg = (63 + 1); /* set highest brg and div */
135 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
140 hw->regs->psc_spimsk =
141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
146 hw->regs->psc_spievent =
147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
160 pcr = hw->regs->psc_spipcr;
166 * dma transfers are used for the most common spi word size of 8-bits
167 * we cannot easily change already set up dma channels' width, so if we wanted
168 * dma support for more than 8-bit words (up to 24 bits), we would need to
169 * setup dma channels from scratch on each spi transfer, based on bits_per_word
170 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
176 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
181 case BITBANG_CS_INACTIVE:
182 if (hw->pdata->deactivate_cs)
183 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
187 case BITBANG_CS_ACTIVE:
188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
190 cfg = hw->regs->psc_spicfg;
192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
195 if (spi->mode & SPI_CPOL)
196 cfg |= PSC_SPICFG_BI;
198 cfg &= ~PSC_SPICFG_BI;
199 if (spi->mode & SPI_CPHA)
200 cfg &= ~PSC_SPICFG_CDE;
202 cfg |= PSC_SPICFG_CDE;
204 if (spi->mode & SPI_LSB_FIRST)
205 cfg |= PSC_SPICFG_MLF;
207 cfg &= ~PSC_SPICFG_MLF;
209 if (hw->usedma && spi->bits_per_word <= 8)
210 cfg &= ~PSC_SPICFG_DD_DISABLE;
212 cfg |= PSC_SPICFG_DD_DISABLE;
213 cfg = PSC_SPICFG_CLR_LEN(cfg);
214 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
216 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217 cfg &= ~PSC_SPICFG_SET_DIV(3);
218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
223 stat = hw->regs->psc_spistat;
225 } while ((stat & PSC_SPISTAT_DR) == 0);
227 if (hw->pdata->activate_cs)
228 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
236 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
240 bpw = t ? t->bits_per_word : spi->bits_per_word;
241 hz = t ? t->speed_hz : spi->max_speed_hz;
243 if (bpw < 4 || bpw > 24) {
244 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
248 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
249 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
254 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
256 cfg = hw->regs->psc_spicfg;
258 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
261 if (hw->usedma && bpw <= 8)
262 cfg &= ~PSC_SPICFG_DD_DISABLE;
264 cfg |= PSC_SPICFG_DD_DISABLE;
265 cfg = PSC_SPICFG_CLR_LEN(cfg);
266 cfg |= PSC_SPICFG_SET_LEN(bpw);
268 cfg = PSC_SPICFG_CLR_BAUD(cfg);
269 cfg &= ~PSC_SPICFG_SET_DIV(3);
270 cfg |= au1550_spi_baudcfg(hw, hz);
272 hw->regs->psc_spicfg = cfg;
275 if (cfg & PSC_SPICFG_DE_ENABLE) {
277 stat = hw->regs->psc_spistat;
279 } while ((stat & PSC_SPISTAT_DR) == 0);
282 au1550_spi_reset_fifos(hw);
283 au1550_spi_mask_ack_all(hw);
287 /* the spi->mode bits understood by this driver: */
288 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
290 static int au1550_spi_setup(struct spi_device *spi)
292 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
294 if (spi->bits_per_word == 0)
295 spi->bits_per_word = 8;
296 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
297 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
302 if (spi->mode & ~MODEBITS) {
303 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
304 spi->mode & ~MODEBITS);
308 if (spi->max_speed_hz == 0)
309 spi->max_speed_hz = hw->freq_max;
310 if (spi->max_speed_hz > hw->freq_max
311 || spi->max_speed_hz < hw->freq_min)
314 * NOTE: cannot change speed and other hw settings immediately,
315 * otherwise sharing of spi bus is not possible,
316 * so do not call setupxfer(spi, NULL) here
322 * for dma spi transfers, we have to setup rx channel, otherwise there is
323 * no reliable way how to recognize that spi transfer is done
324 * dma complete callbacks are called before real spi transfer is finished
325 * and if only tx dma channel is set up (and rx fifo overflow event masked)
326 * spi master done event irq is not generated unless rx fifo is empty (emptied)
327 * so we need rx tmp buffer to use for rx dma if user does not provide one
329 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
331 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
332 if (!hw->dma_rx_tmpbuf)
334 hw->dma_rx_tmpbuf_size = size;
335 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
336 size, DMA_FROM_DEVICE);
337 if (dma_mapping_error(hw->dma_rx_tmpbuf_addr)) {
338 kfree(hw->dma_rx_tmpbuf);
339 hw->dma_rx_tmpbuf = 0;
340 hw->dma_rx_tmpbuf_size = 0;
346 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
348 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
349 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
350 kfree(hw->dma_rx_tmpbuf);
351 hw->dma_rx_tmpbuf = 0;
352 hw->dma_rx_tmpbuf_size = 0;
355 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
357 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
358 dma_addr_t dma_tx_addr;
359 dma_addr_t dma_rx_addr;
368 dma_tx_addr = t->tx_dma;
369 dma_rx_addr = t->rx_dma;
372 * check if buffers are already dma mapped, map them otherwise
373 * use rx buffer in place of tx if tx buffer was not provided
374 * use temp rx buffer (preallocated or realloc to fit) for rx dma
377 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
378 dma_rx_addr = dma_map_single(hw->dev,
380 t->len, DMA_FROM_DEVICE);
381 if (dma_mapping_error(dma_rx_addr))
382 dev_err(hw->dev, "rx dma map error\n");
385 if (t->len > hw->dma_rx_tmpbuf_size) {
388 au1550_spi_dma_rxtmp_free(hw);
389 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
390 AU1550_SPI_DMA_RXTMP_MINSIZE));
394 hw->rx = hw->dma_rx_tmpbuf;
395 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
396 dma_sync_single_for_device(hw->dev, dma_rx_addr,
397 t->len, DMA_FROM_DEVICE);
400 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
401 dma_tx_addr = dma_map_single(hw->dev,
403 t->len, DMA_TO_DEVICE);
404 if (dma_mapping_error(dma_tx_addr))
405 dev_err(hw->dev, "tx dma map error\n");
408 dma_sync_single_for_device(hw->dev, dma_rx_addr,
409 t->len, DMA_BIDIRECTIONAL);
413 /* put buffers on the ring */
414 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
416 dev_err(hw->dev, "rx dma put dest error\n");
418 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
420 dev_err(hw->dev, "tx dma put source error\n");
422 au1xxx_dbdma_start(hw->dma_rx_ch);
423 au1xxx_dbdma_start(hw->dma_tx_ch);
425 /* by default enable nearly all events interrupt */
426 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
429 /* start the transfer */
430 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
433 wait_for_completion(&hw->master_done);
435 au1xxx_dbdma_stop(hw->dma_tx_ch);
436 au1xxx_dbdma_stop(hw->dma_rx_ch);
439 /* using the temporal preallocated and premapped buffer */
440 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
443 /* unmap buffers if mapped above */
444 if (t->rx_buf && t->rx_dma == 0 )
445 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
447 if (t->tx_buf && t->tx_dma == 0 )
448 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
451 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
454 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
458 stat = hw->regs->psc_spistat;
459 evnt = hw->regs->psc_spievent;
461 if ((stat & PSC_SPISTAT_DI) == 0) {
462 dev_err(hw->dev, "Unexpected IRQ!\n");
466 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
467 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
468 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
471 * due to an spi error we consider transfer as done,
472 * so mask all events until before next transfer start
473 * and stop the possibly running dma immediatelly
475 au1550_spi_mask_ack_all(hw);
476 au1xxx_dbdma_stop(hw->dma_rx_ch);
477 au1xxx_dbdma_stop(hw->dma_tx_ch);
479 /* get number of transfered bytes */
480 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
481 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
483 au1xxx_dbdma_reset(hw->dma_rx_ch);
484 au1xxx_dbdma_reset(hw->dma_tx_ch);
485 au1550_spi_reset_fifos(hw);
488 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
491 complete(&hw->master_done);
495 if ((evnt & PSC_SPIEVNT_MD) != 0) {
496 /* transfer completed successfully */
497 au1550_spi_mask_ack_all(hw);
498 hw->rx_count = hw->len;
499 hw->tx_count = hw->len;
500 complete(&hw->master_done);
506 /* routines to handle different word sizes in pio mode */
507 #define AU1550_SPI_RX_WORD(size, mask) \
508 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
510 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
513 *(u##size *)hw->rx = (u##size)fifoword; \
514 hw->rx += (size) / 8; \
516 hw->rx_count += (size) / 8; \
519 #define AU1550_SPI_TX_WORD(size, mask) \
520 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
524 fifoword = *(u##size *)hw->tx & (u32)(mask); \
525 hw->tx += (size) / 8; \
527 hw->tx_count += (size) / 8; \
528 if (hw->tx_count >= hw->len) \
529 fifoword |= PSC_SPITXRX_LC; \
530 hw->regs->psc_spitxrx = fifoword; \
534 AU1550_SPI_RX_WORD(8,0xff)
535 AU1550_SPI_RX_WORD(16,0xffff)
536 AU1550_SPI_RX_WORD(32,0xffffff)
537 AU1550_SPI_TX_WORD(8,0xff)
538 AU1550_SPI_TX_WORD(16,0xffff)
539 AU1550_SPI_TX_WORD(32,0xffffff)
541 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
544 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
552 /* by default enable nearly all events after filling tx fifo */
553 mask = PSC_SPIMSK_SD;
555 /* fill the transmit FIFO */
556 while (hw->tx_count < hw->len) {
560 if (hw->tx_count >= hw->len) {
561 /* mask tx fifo request interrupt as we are done */
562 mask |= PSC_SPIMSK_TR;
565 stat = hw->regs->psc_spistat;
567 if (stat & PSC_SPISTAT_TF)
571 /* enable event interrupts */
572 hw->regs->psc_spimsk = mask;
575 /* start the transfer */
576 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
579 wait_for_completion(&hw->master_done);
581 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
584 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
589 stat = hw->regs->psc_spistat;
590 evnt = hw->regs->psc_spievent;
592 if ((stat & PSC_SPISTAT_DI) == 0) {
593 dev_err(hw->dev, "Unexpected IRQ!\n");
597 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
598 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
599 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
602 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
605 * due to an error we consider transfer as done,
606 * so mask all events until before next transfer start
608 au1550_spi_mask_ack_all(hw);
609 au1550_spi_reset_fifos(hw);
610 complete(&hw->master_done);
615 * while there is something to read from rx fifo
616 * or there is a space to write to tx fifo:
620 stat = hw->regs->psc_spistat;
623 if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) {
625 /* ack the receive request event */
626 hw->regs->psc_spievent = PSC_SPIEVNT_RR;
631 if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) {
633 /* ack the transmit request event */
634 hw->regs->psc_spievent = PSC_SPIEVNT_TR;
640 evnt = hw->regs->psc_spievent;
643 if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) {
644 /* transfer completed successfully */
645 au1550_spi_mask_ack_all(hw);
646 complete(&hw->master_done);
651 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
653 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
654 return hw->txrx_bufs(spi, t);
657 static irqreturn_t au1550_spi_irq(int irq, void *dev)
659 struct au1550_spi *hw = dev;
660 return hw->irq_callback(hw);
663 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
667 hw->txrx_bufs = &au1550_spi_dma_txrxb;
668 hw->irq_callback = &au1550_spi_dma_irq_callback;
670 hw->rx_word = &au1550_spi_rx_word_8;
671 hw->tx_word = &au1550_spi_tx_word_8;
672 hw->txrx_bufs = &au1550_spi_pio_txrxb;
673 hw->irq_callback = &au1550_spi_pio_irq_callback;
675 } else if (bpw <= 16) {
676 hw->rx_word = &au1550_spi_rx_word_16;
677 hw->tx_word = &au1550_spi_tx_word_16;
678 hw->txrx_bufs = &au1550_spi_pio_txrxb;
679 hw->irq_callback = &au1550_spi_pio_irq_callback;
681 hw->rx_word = &au1550_spi_rx_word_32;
682 hw->tx_word = &au1550_spi_tx_word_32;
683 hw->txrx_bufs = &au1550_spi_pio_txrxb;
684 hw->irq_callback = &au1550_spi_pio_irq_callback;
688 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
692 /* set up the PSC for SPI mode */
693 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
695 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
698 hw->regs->psc_spicfg = 0;
701 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
705 stat = hw->regs->psc_spistat;
707 } while ((stat & PSC_SPISTAT_SR) == 0);
710 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
711 cfg |= PSC_SPICFG_SET_LEN(8);
712 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
713 /* use minimal allowed brg and div values as initial setting: */
714 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
716 #ifdef AU1550_SPI_DEBUG_LOOPBACK
717 cfg |= PSC_SPICFG_LB;
720 hw->regs->psc_spicfg = cfg;
723 au1550_spi_mask_ack_all(hw);
725 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
729 stat = hw->regs->psc_spistat;
731 } while ((stat & PSC_SPISTAT_DR) == 0);
735 static int __init au1550_spi_probe(struct platform_device *pdev)
737 struct au1550_spi *hw;
738 struct spi_master *master;
742 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
743 if (master == NULL) {
744 dev_err(&pdev->dev, "No memory for spi_master\n");
749 hw = spi_master_get_devdata(master);
751 hw->master = spi_master_get(master);
752 hw->pdata = pdev->dev.platform_data;
753 hw->dev = &pdev->dev;
755 if (hw->pdata == NULL) {
756 dev_err(&pdev->dev, "No platform data supplied\n");
761 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
763 dev_err(&pdev->dev, "no IRQ\n");
770 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
772 hw->dma_tx_id = r->start;
773 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
775 hw->dma_rx_id = r->start;
776 if (usedma && ddma_memid) {
777 if (pdev->dev.dma_mask == NULL)
778 dev_warn(&pdev->dev, "no dma mask\n");
785 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
787 dev_err(&pdev->dev, "no mmio resource\n");
792 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
795 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
800 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
802 dev_err(&pdev->dev, "cannot ioremap\n");
807 platform_set_drvdata(pdev, hw);
809 init_completion(&hw->master_done);
811 hw->bitbang.master = hw->master;
812 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
813 hw->bitbang.chipselect = au1550_spi_chipsel;
814 hw->bitbang.master->setup = au1550_spi_setup;
815 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
818 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
819 hw->dma_tx_id, NULL, (void *)hw);
820 if (hw->dma_tx_ch == 0) {
822 "Cannot allocate tx dma channel\n");
826 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
827 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
828 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
830 "Cannot allocate tx dma descriptors\n");
832 goto err_no_txdma_descr;
836 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
837 ddma_memid, NULL, (void *)hw);
838 if (hw->dma_rx_ch == 0) {
840 "Cannot allocate rx dma channel\n");
844 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
845 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
846 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
848 "Cannot allocate rx dma descriptors\n");
850 goto err_no_rxdma_descr;
853 err = au1550_spi_dma_rxtmp_alloc(hw,
854 AU1550_SPI_DMA_RXTMP_MINSIZE);
857 "Cannot allocate initial rx dma tmp buffer\n");
858 goto err_dma_rxtmp_alloc;
862 au1550_spi_bits_handlers_set(hw, 8);
864 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
866 dev_err(&pdev->dev, "Cannot claim IRQ\n");
870 master->bus_num = pdev->id;
871 master->num_chipselect = hw->pdata->num_chipselect;
874 * precompute valid range for spi freq - from au1550 datasheet:
875 * psc_tempclk = psc_mainclk / (2 << DIV)
876 * spiclk = psc_tempclk / (2 * (BRG + 1))
877 * BRG valid range is 4..63
878 * DIV valid range is 0..3
879 * round the min and max frequencies to values that would still
880 * produce valid brg and div
883 int min_div = (2 << 0) * (2 * (4 + 1));
884 int max_div = (2 << 3) * (2 * (63 + 1));
885 hw->freq_max = hw->pdata->mainclk_hz / min_div;
886 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
889 au1550_spi_setup_psc_as_spi(hw);
891 err = spi_bitbang_start(&hw->bitbang);
893 dev_err(&pdev->dev, "Failed to register SPI master\n");
898 "spi master registered: bus_num=%d num_chipselect=%d\n",
899 master->bus_num, master->num_chipselect);
904 free_irq(hw->irq, hw);
907 au1550_spi_dma_rxtmp_free(hw);
912 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
917 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
920 iounmap((void __iomem *)hw->regs);
923 release_resource(hw->ioarea);
928 spi_master_put(hw->master);
934 static int __exit au1550_spi_remove(struct platform_device *pdev)
936 struct au1550_spi *hw = platform_get_drvdata(pdev);
938 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
939 hw->master->bus_num);
941 spi_bitbang_stop(&hw->bitbang);
942 free_irq(hw->irq, hw);
943 iounmap((void __iomem *)hw->regs);
944 release_resource(hw->ioarea);
948 au1550_spi_dma_rxtmp_free(hw);
949 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
950 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
953 platform_set_drvdata(pdev, NULL);
955 spi_master_put(hw->master);
959 /* work with hotplug and coldplug */
960 MODULE_ALIAS("platform:au1550-spi");
962 static struct platform_driver au1550_spi_drv = {
963 .remove = __exit_p(au1550_spi_remove),
965 .name = "au1550-spi",
966 .owner = THIS_MODULE,
970 static int __init au1550_spi_init(void)
973 * create memory device with 8 bits dev_devwidth
974 * needed for proper byte ordering to spi fifo
977 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
979 printk(KERN_ERR "au1550-spi: cannot add memory"
982 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
984 module_init(au1550_spi_init);
986 static void __exit au1550_spi_exit(void)
988 if (usedma && ddma_memid)
989 au1xxx_ddma_del_device(ddma_memid);
990 platform_driver_unregister(&au1550_spi_drv);
992 module_exit(au1550_spi_exit);
994 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
995 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
996 MODULE_LICENSE("GPL");