2 * Driver for Blackfin On-Chip SPI device
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/spi.h>
18 struct bfin_spi_slave {
19 struct spi_slave slave;
24 #define MAKE_SPI_FUNC(mmr, off) \
25 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
26 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
27 MAKE_SPI_FUNC(SPI_CTL, 0x00)
28 MAKE_SPI_FUNC(SPI_FLG, 0x04)
29 MAKE_SPI_FUNC(SPI_STAT, 0x08)
30 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
31 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
32 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
34 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
37 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
39 #if defined(__ADSPBF538__) || defined(__ADSPBF539__)
40 /* The SPI1/SPI2 buses are weird ... only 1 CS */
41 if (bus > 0 && cs != 1)
44 return (cs >= 1 && cs <= 7);
48 void spi_cs_activate(struct spi_slave *slave)
50 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
53 ~((!bss->flg << 8) << slave->cs)) |
55 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
59 void spi_cs_deactivate(struct spi_slave *slave)
61 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
62 write_SPI_FLG(bss, read_SPI_FLG(bss) & ~(1 << slave->cs));
63 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
70 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
71 unsigned int max_hz, unsigned int mode)
73 struct bfin_spi_slave *bss;
77 if (!spi_cs_is_valid(bus, cs))
82 # define SPI0_CTL SPI_CTL
84 case 0: mmr_base = SPI0_CTL; break;
86 case 1: mmr_base = SPI1_CTL; break;
89 case 2: mmr_base = SPI2_CTL; break;
94 baud = get_sclk() / (2 * max_hz);
97 else if (baud > (u16)-1)
100 bss = malloc(sizeof(*bss));
104 bss->slave.bus = bus;
106 bss->mmr_base = (void *)mmr_base;
107 bss->ctl = SPE | MSTR | TDBR_CORE;
108 if (mode & SPI_CPHA) bss->ctl |= CPHA;
109 if (mode & SPI_CPOL) bss->ctl |= CPOL;
110 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
112 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
114 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
115 bus, cs, mmr_base, bss->ctl, baud, bss->flg);
120 void spi_free_slave(struct spi_slave *slave)
122 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
126 static void spi_portmux(struct spi_slave *slave)
128 #if defined(__ADSPBF51x__)
129 #define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
130 u16 f_mux = bfin_read_PORTF_MUX();
131 u16 f_fer = bfin_read_PORTF_FER();
132 u16 g_mux = bfin_read_PORTG_MUX();
133 u16 g_fer = bfin_read_PORTG_FER();
134 u16 h_mux = bfin_read_PORTH_MUX();
135 u16 h_fer = bfin_read_PORTH_FER();
136 switch (slave->bus) {
138 /* set SCK/MISO/MOSI */
140 g_fer |= PG12 | PG13 | PG14;
142 case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
143 case 2: /* see G above */ g_fer |= PG15; break;
144 case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
145 case 4: /* no muxing */ break;
146 case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
147 case 6: /* no muxing */ break;
148 case 7: /* no muxing */ break;
151 /* set SCK/MISO/MOSI */
153 h_fer |= PH1 | PH2 | PH3;
155 case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break;
156 case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break;
157 case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break;
158 case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break;
159 case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
160 case 6: /* no muxing */ break;
161 case 7: /* no muxing */ break;
164 bfin_write_PORTF_MUX(f_mux);
165 bfin_write_PORTF_FER(f_fer);
166 bfin_write_PORTG_MUX(g_mux);
167 bfin_write_PORTG_FER(g_fer);
168 bfin_write_PORTH_MUX(h_mux);
169 bfin_write_PORTH_FER(h_fer);
170 #elif defined(__ADSPBF52x__)
171 #define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
172 u16 f_mux = bfin_read_PORTF_MUX();
173 u16 f_fer = bfin_read_PORTF_FER();
174 u16 g_mux = bfin_read_PORTG_MUX();
175 u16 g_fer = bfin_read_PORTG_FER();
176 u16 h_mux = bfin_read_PORTH_MUX();
177 u16 h_fer = bfin_read_PORTH_FER();
178 /* set SCK/MISO/MOSI */
180 g_fer |= PG2 | PG3 | PG4;
182 case 1: /* see G above */ g_fer |= PG1; break;
183 case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
184 case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
185 case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break;
186 case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break;
187 case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break;
188 case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
190 bfin_write_PORTF_MUX(f_mux);
191 bfin_write_PORTF_FER(f_fer);
192 bfin_write_PORTG_MUX(g_mux);
193 bfin_write_PORTG_FER(g_fer);
194 bfin_write_PORTH_MUX(h_mux);
195 bfin_write_PORTH_FER(h_fer);
196 #elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
197 u16 mux = bfin_read_PORT_MUX();
198 u16 f_fer = bfin_read_PORTF_FER();
199 /* set SCK/MISO/MOSI */
200 f_fer |= PF11 | PF12 | PF13;
202 case 1: f_fer |= PF10; break;
203 case 2: mux |= PJSE; break;
204 case 3: mux |= PJSE; break;
205 case 4: mux |= PFS4E; f_fer |= PF6; break;
206 case 5: mux |= PFS5E; f_fer |= PF5; break;
207 case 6: mux |= PFS6E; f_fer |= PF4; break;
208 case 7: mux |= PJCE_SPI; break;
210 bfin_write_PORT_MUX(mux);
211 bfin_write_PORTF_FER(f_fer);
212 #elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
215 pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
216 else if (slave->bus == 2)
217 pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
221 fer = bfin_read_PORTDIO_FER();
223 bfin_write_PORTDIO_FER(fer);
225 #elif defined(__ADSPBF54x__)
226 #define DO_MUX(port, pin) \
227 mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
231 switch (slave->bus) {
233 mux = bfin_read_PORTE_MUX();
234 fer = bfin_read_PORTE_FER();
235 /* set SCK/MISO/MOSI */
240 case 1: DO_MUX(E, 4); break;
241 case 2: DO_MUX(E, 5); break;
242 case 3: DO_MUX(E, 6); break;
244 bfin_write_PORTE_MUX(mux);
245 bfin_write_PORTE_FER(fer);
248 mux = bfin_read_PORTG_MUX();
249 fer = bfin_read_PORTG_FER();
250 /* set SCK/MISO/MOSI */
255 case 1: DO_MUX(G, 5); break;
256 case 2: DO_MUX(G, 6); break;
257 case 3: DO_MUX(G, 7); break;
259 bfin_write_PORTG_MUX(mux);
260 bfin_write_PORTG_FER(fer);
263 mux = bfin_read_PORTB_MUX();
264 fer = bfin_read_PORTB_FER();
265 /* set SCK/MISO/MOSI */
270 case 1: DO_MUX(B, 9); break;
271 case 2: DO_MUX(B, 10); break;
272 case 3: DO_MUX(B, 11); break;
274 bfin_write_PORTB_MUX(mux);
275 bfin_write_PORTB_FER(fer);
281 int spi_claim_bus(struct spi_slave *slave)
283 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
285 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
288 write_SPI_CTL(bss, bss->ctl);
289 write_SPI_BAUD(bss, bss->baud);
295 void spi_release_bus(struct spi_slave *slave)
297 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
298 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
299 write_SPI_CTL(bss, 0);
303 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
304 void *din, unsigned long flags)
306 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
309 uint bytes = bitlen / 8;
312 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
313 slave->bus, slave->cs, bitlen, bytes, flags);
318 /* we can only do 8 bit transfers */
320 flags |= SPI_XFER_END;
324 if (flags & SPI_XFER_BEGIN)
325 spi_cs_activate(slave);
327 /* todo: take advantage of hardware fifos and setup RX dma */
329 u8 value = (tx ? *tx++ : 0);
330 debug("%s: tx:%x ", __func__, value);
331 write_SPI_TDBR(bss, value);
333 while ((read_SPI_STAT(bss) & TXS))
338 while (!(read_SPI_STAT(bss) & SPIF))
343 while (!(read_SPI_STAT(bss) & RXS))
348 value = read_SPI_RDBR(bss);
351 debug("rx:%x\n", value);
355 if (flags & SPI_XFER_END)
356 spi_cs_deactivate(slave);