drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/errno.h>
  31 #include "cadence_qspi.h"
  32
  33 #define CQSPI_REG_POLL_US                       (1) /* 1us */
  34 #define CQSPI_REG_RETRY                         (10000)
  35 #define CQSPI_POLL_IDLE_RETRY                   (3)
  36
  37 #define CQSPI_FIFO_WIDTH                        (4)
  38
  39 /* Controller sram size in word */
  40 #define CQSPI_REG_SRAM_SIZE_WORD                (128)
  41 #define CQSPI_REG_SRAM_RESV_WORDS               (2)
  42 #define CQSPI_REG_SRAM_PARTITION_WR             (1)
  43 #define CQSPI_REG_SRAM_PARTITION_RD             \
  44         (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
  45 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          (50)
  46
  47 /* Transfer mode */
  48 #define CQSPI_INST_TYPE_SINGLE                  (0)
  49 #define CQSPI_INST_TYPE_DUAL                    (1)
  50 #define CQSPI_INST_TYPE_QUAD                    (2)
  51
  52 #define CQSPI_STIG_DATA_LEN_MAX                 (8)
  53 #define CQSPI_INDIRECTTRIGGER_ADDR_MASK         (0xFFFFF)
  54
  55 #define CQSPI_DUMMY_CLKS_PER_BYTE               (8)
  56 #define CQSPI_DUMMY_BYTES_MAX                   (4)
  57
  58
  59 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  60         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  61 /****************************************************************************
  62  * Controller's configuration and status register (offset from QSPI_BASE)
  63  ****************************************************************************/
  64 #define CQSPI_REG_CONFIG                        0x00
  65 #define CQSPI_REG_CONFIG_CLK_POL_LSB            1
  66 #define CQSPI_REG_CONFIG_CLK_PHA_LSB            2
  67 #define CQSPI_REG_CONFIG_ENABLE_MASK            (1 << 0)
  68 #define CQSPI_REG_CONFIG_DIRECT_MASK            (1 << 7)
  69 #define CQSPI_REG_CONFIG_DECODE_MASK            (1 << 9)
  70 #define CQSPI_REG_CONFIG_XIP_IMM_MASK           (1 << 18)
  71 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  72 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  73 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  74 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  75 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  76
  77 #define CQSPI_REG_RD_INSTR                      0x04
  78 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  82 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  83 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  84 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  85 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  86 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  87 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  88
  89 #define CQSPI_REG_WR_INSTR                      0x08
  90 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  91
  92 #define CQSPI_REG_DELAY                         0x0C
  93 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  94 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  95 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  96 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  97 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  98 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  99 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 100 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 101
 102 #define CQSPI_READLCAPTURE                      0x10
 103 #define CQSPI_READLCAPTURE_BYPASS_LSB           0
 104 #define CQSPI_READLCAPTURE_DELAY_LSB            1
 105 #define CQSPI_READLCAPTURE_DELAY_MASK           0xF
 106
 107 #define CQSPI_REG_SIZE                          0x14
 108 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 109 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 110 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 111 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 112 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 113 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 114
 115 #define CQSPI_REG_SRAMPARTITION                 0x18
 116 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 117
 118 #define CQSPI_REG_REMAP                         0x24
 119 #define CQSPI_REG_MODE_BIT                      0x28
 120
 121 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 122 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 123 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 124 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 125 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 126
 127 #define CQSPI_REG_IRQSTATUS                     0x40
 128 #define CQSPI_REG_IRQMASK                       0x44
 129
 130 #define CQSPI_REG_INDIRECTRD                    0x60
 131 #define CQSPI_REG_INDIRECTRD_START_MASK         (1 << 0)
 132 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        (1 << 1)
 133 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK    (1 << 2)
 134 #define CQSPI_REG_INDIRECTRD_DONE_MASK          (1 << 5)
 135
 136 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 137 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 138 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 139
 140 #define CQSPI_REG_CMDCTRL                       0x90
 141 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          (1 << 0)
 142 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       (1 << 1)
 143 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 144 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 145 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 146 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 147 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 148 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 149 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 150 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 151 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 152 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 153 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 154 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 155 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 156
 157 #define CQSPI_REG_INDIRECTWR                    0x70
 158 #define CQSPI_REG_INDIRECTWR_START_MASK         (1 << 0)
 159 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        (1 << 1)
 160 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK    (1 << 2)
 161 #define CQSPI_REG_INDIRECTWR_DONE_MASK          (1 << 5)
 162
 163 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 164 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 165 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 166
 167 #define CQSPI_REG_CMDADDRESS                    0x94
 168 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 169 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 170 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 171 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 172
 173 #define CQSPI_REG_IS_IDLE(base)                                 \
 174         ((readl(base + CQSPI_REG_CONFIG) >>             \
 175                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 176
 177 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 178         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 179
 180 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 181         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 182         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 183
 184 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 185         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 186         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 187
 188 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 189         unsigned int addr_width)
 190 {
 191         unsigned int addr;
 192
 193         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 194
 195         if (addr_width == 4)
 196                 addr = (addr << 8) | addr_buf[3];
 197
 198         return addr;
 199 }
 200
 201 static void cadence_qspi_apb_read_fifo_data(void *dest,
 202         const void *src_ahb_addr, unsigned int bytes)
 203 {
 204         unsigned int temp;
 205         int remaining = bytes;
 206         unsigned int *dest_ptr = (unsigned int *)dest;
 207         unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 208
 209         while (remaining > 0) {
 210                 if (remaining >= CQSPI_FIFO_WIDTH) {
 211                         *dest_ptr = readl(src_ptr);
 212                         remaining -= CQSPI_FIFO_WIDTH;
 213                 } else {
 214                         /* dangling bytes */
 215                         temp = readl(src_ptr);
 216                         memcpy(dest_ptr, &temp, remaining);
 217                         break;
 218                 }
 219                 dest_ptr++;
 220         }
 221
 222         return;
 223 }
 224
 225 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 226         const void *src, unsigned int bytes)
 227 {
 228         unsigned int temp;
 229         int remaining = bytes;
 230         unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
 231         unsigned int *src_ptr = (unsigned int *)src;
 232
 233         while (remaining > 0) {
 234                 if (remaining >= CQSPI_FIFO_WIDTH) {
 235                         writel(*src_ptr, dest_ptr);
 236                         remaining -= sizeof(unsigned int);
 237                 } else {
 238                         /* dangling bytes */
 239                         memcpy(&temp, src_ptr, remaining);
 240                         writel(temp, dest_ptr);
 241                         break;
 242                 }
 243                 src_ptr++;
 244         }
 245
 246         return;
 247 }
 248
 249 /* Read from SRAM FIFO with polling SRAM fill level. */
 250 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
 251                         const void *src_addr,  unsigned int num_bytes)
 252 {
 253         unsigned int remaining = num_bytes;
 254         unsigned int retry;
 255         unsigned int sram_level = 0;
 256         unsigned char *dest = (unsigned char *)dest_addr;
 257
 258         while (remaining > 0) {
 259                 retry = CQSPI_REG_RETRY;
 260                 while (retry--) {
 261                         sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
 262                         if (sram_level)
 263                                 break;
 264                         udelay(1);
 265                 }
 266
 267                 if (!retry) {
 268                         printf("QSPI: No receive data after polling for %d times\n",
 269                                CQSPI_REG_RETRY);
 270                         return -1;
 271                 }
 272
 273                 sram_level *= CQSPI_FIFO_WIDTH;
 274                 sram_level = sram_level > remaining ? remaining : sram_level;
 275
 276                 /* Read data from FIFO. */
 277                 cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
 278                 dest += sram_level;
 279                 remaining -= sram_level;
 280                 udelay(1);
 281         }
 282         return 0;
 283 }
 284
 285 /* Write to SRAM FIFO with polling SRAM fill level. */
 286 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 287                                 const void *src_addr, unsigned int num_bytes)
 288 {
 289         const void *reg_base = plat->regbase;
 290         void *dest_addr = plat->ahbbase;
 291         unsigned int retry = CQSPI_REG_RETRY;
 292         unsigned int sram_level;
 293         unsigned int wr_bytes;
 294         unsigned char *src = (unsigned char *)src_addr;
 295         int remaining = num_bytes;
 296         unsigned int page_size = plat->page_size;
 297         unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
 298
 299         while (remaining > 0) {
 300                 retry = CQSPI_REG_RETRY;
 301                 while (retry--) {
 302                         sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
 303                         if (sram_level <= sram_threshold_words)
 304                                 break;
 305                 }
 306                 if (!retry) {
 307                         printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
 308                                sram_level, sram_threshold_words);
 309                         return -1;
 310                 }
 311                 /* Write a page or remaining bytes. */
 312                 wr_bytes = (remaining > page_size) ?
 313                                         page_size : remaining;
 314
 315                 cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
 316                 src += wr_bytes;
 317                 remaining -= wr_bytes;
 318         }
 319
 320         return 0;
 321 }
 322
 323 void cadence_qspi_apb_controller_enable(void *reg_base)
 324 {
 325         unsigned int reg;
 326         reg = readl(reg_base + CQSPI_REG_CONFIG);
 327         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 328         writel(reg, reg_base + CQSPI_REG_CONFIG);
 329         return;
 330 }
 331
 332 void cadence_qspi_apb_controller_disable(void *reg_base)
 333 {
 334         unsigned int reg;
 335         reg = readl(reg_base + CQSPI_REG_CONFIG);
 336         reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 337         writel(reg, reg_base + CQSPI_REG_CONFIG);
 338         return;
 339 }
 340
 341 /* Return 1 if idle, otherwise return 0 (busy). */
 342 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 343 {
 344         unsigned int start, count = 0;
 345         /* timeout in unit of ms */
 346         unsigned int timeout = 5000;
 347
 348         start = get_timer(0);
 349         for ( ; get_timer(start) < timeout ; ) {
 350                 if (CQSPI_REG_IS_IDLE(reg_base))
 351                         count++;
 352                 else
 353                         count = 0;
 354                 /*
 355                  * Ensure the QSPI controller is in true idle state after
 356                  * reading back the same idle status consecutively
 357                  */
 358                 if (count >= CQSPI_POLL_IDLE_RETRY)
 359                         return 1;
 360         }
 361
 362         /* Timeout, still in busy mode. */
 363         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 364                CQSPI_REG_RETRY);
 365         return 0;
 366 }
 367
 368 void cadence_qspi_apb_readdata_capture(void *reg_base,
 369                                 unsigned int bypass, unsigned int delay)
 370 {
 371         unsigned int reg;
 372         cadence_qspi_apb_controller_disable(reg_base);
 373
 374         reg = readl(reg_base + CQSPI_READLCAPTURE);
 375
 376         if (bypass)
 377                 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 378         else
 379                 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 380
 381         reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
 382                 << CQSPI_READLCAPTURE_DELAY_LSB);
 383
 384         reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
 385                 << CQSPI_READLCAPTURE_DELAY_LSB);
 386
 387         writel(reg, reg_base + CQSPI_READLCAPTURE);
 388
 389         cadence_qspi_apb_controller_enable(reg_base);
 390         return;
 391 }
 392
 393 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 394         unsigned int ref_clk_hz, unsigned int sclk_hz)
 395 {
 396         unsigned int reg;
 397         unsigned int div;
 398
 399         cadence_qspi_apb_controller_disable(reg_base);
 400         reg = readl(reg_base + CQSPI_REG_CONFIG);
 401         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 402
 403         div = ref_clk_hz / sclk_hz;
 404
 405         if (div > 32)
 406                 div = 32;
 407
 408         /* Check if even number. */
 409         if ((div & 1)) {
 410                 div = (div / 2);
 411         } else {
 412                 if (ref_clk_hz % sclk_hz)
 413                         /* ensure generated SCLK doesn't exceed user
 414                         specified sclk_hz */
 415                         div = (div / 2);
 416                 else
 417                         div = (div / 2) - 1;
 418         }
 419
 420         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
 421               ref_clk_hz, sclk_hz, div);
 422
 423         div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 424         reg |= div;
 425         writel(reg, reg_base + CQSPI_REG_CONFIG);
 426
 427         cadence_qspi_apb_controller_enable(reg_base);
 428         return;
 429 }
 430
 431 void cadence_qspi_apb_set_clk_mode(void *reg_base,
 432         unsigned int clk_pol, unsigned int clk_pha)
 433 {
 434         unsigned int reg;
 435
 436         cadence_qspi_apb_controller_disable(reg_base);
 437         reg = readl(reg_base + CQSPI_REG_CONFIG);
 438         reg &= ~(1 <<
 439                 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
 440
 441         reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
 442         reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
 443
 444         writel(reg, reg_base + CQSPI_REG_CONFIG);
 445
 446         cadence_qspi_apb_controller_enable(reg_base);
 447         return;
 448 }
 449
 450 void cadence_qspi_apb_chipselect(void *reg_base,
 451         unsigned int chip_select, unsigned int decoder_enable)
 452 {
 453         unsigned int reg;
 454
 455         cadence_qspi_apb_controller_disable(reg_base);
 456
 457         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 458               decoder_enable);
 459
 460         reg = readl(reg_base + CQSPI_REG_CONFIG);
 461         /* docoder */
 462         if (decoder_enable) {
 463                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 464         } else {
 465                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 466                 /* Convert CS if without decoder.
 467                  * CS0 to 4b'1110
 468                  * CS1 to 4b'1101
 469                  * CS2 to 4b'1011
 470                  * CS3 to 4b'0111
 471                  */
 472                 chip_select = 0xF & ~(1 << chip_select);
 473         }
 474
 475         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 476                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 477         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 478                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 479         writel(reg, reg_base + CQSPI_REG_CONFIG);
 480
 481         cadence_qspi_apb_controller_enable(reg_base);
 482         return;
 483 }
 484
 485 void cadence_qspi_apb_delay(void *reg_base,
 486         unsigned int ref_clk, unsigned int sclk_hz,
 487         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 488         unsigned int tchsh_ns, unsigned int tslch_ns)
 489 {
 490         unsigned int ref_clk_ns;
 491         unsigned int sclk_ns;
 492         unsigned int tshsl, tchsh, tslch, tsd2d;
 493         unsigned int reg;
 494
 495         cadence_qspi_apb_controller_disable(reg_base);
 496
 497         /* Convert to ns. */
 498         ref_clk_ns = (1000000000) / ref_clk;
 499
 500         /* Convert to ns. */
 501         sclk_ns = (1000000000) / sclk_hz;
 502
 503         /* Plus 1 to round up 1 clock cycle. */
 504         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 505         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 506         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 507         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 508
 509         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 510                         << CQSPI_REG_DELAY_TSHSL_LSB);
 511         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 512                         << CQSPI_REG_DELAY_TCHSH_LSB);
 513         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 514                         << CQSPI_REG_DELAY_TSLCH_LSB);
 515         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 516                         << CQSPI_REG_DELAY_TSD2D_LSB);
 517         writel(reg, reg_base + CQSPI_REG_DELAY);
 518
 519         cadence_qspi_apb_controller_enable(reg_base);
 520         return;
 521 }
 522
 523 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 524 {
 525         unsigned reg;
 526
 527         cadence_qspi_apb_controller_disable(plat->regbase);
 528
 529         /* Configure the device size and address bytes */
 530         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 531         /* Clear the previous value */
 532         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 533         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 534         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 535         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 536         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 537
 538         /* Configure the remap address register, no remap */
 539         writel(0, plat->regbase + CQSPI_REG_REMAP);
 540
 541         /* Disable all interrupts */
 542         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 543
 544         cadence_qspi_apb_controller_enable(plat->regbase);
 545         return;
 546 }
 547
 548 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 549         unsigned int reg)
 550 {
 551         unsigned int retry = CQSPI_REG_RETRY;
 552
 553         /* Write the CMDCTRL without start execution. */
 554         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 555         /* Start execute */
 556         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 557         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 558
 559         while (retry--) {
 560                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 561                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
 562                         break;
 563                 udelay(1);
 564         }
 565
 566         if (!retry) {
 567                 printf("QSPI: flash command execution timeout\n");
 568                 return -EIO;
 569         }
 570
 571         /* Polling QSPI idle status. */
 572         if (!cadence_qspi_wait_idle(reg_base))
 573                 return -EIO;
 574
 575         return 0;
 576 }
 577
 578 /* For command RDID, RDSR. */
 579 int cadence_qspi_apb_command_read(void *reg_base,
 580         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 581         u8 *rxbuf)
 582 {
 583         unsigned int reg;
 584         unsigned int read_len;
 585         int status;
 586
 587         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 588                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 589                        cmdlen, rxlen);
 590                 return -EINVAL;
 591         }
 592
 593         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 594
 595         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 596
 597         /* 0 means 1 byte. */
 598         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 599                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 600         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 601         if (status != 0)
 602                 return status;
 603
 604         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 605
 606         /* Put the read value into rx_buf */
 607         read_len = (rxlen > 4) ? 4 : rxlen;
 608         memcpy(rxbuf, &reg, read_len);
 609         rxbuf += read_len;
 610
 611         if (rxlen > 4) {
 612                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 613
 614                 read_len = rxlen - read_len;
 615                 memcpy(rxbuf, &reg, read_len);
 616         }
 617         return 0;
 618 }
 619
 620 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 621 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 622         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 623 {
 624         unsigned int reg = 0;
 625         unsigned int addr_value;
 626         unsigned int wr_data;
 627         unsigned int wr_len;
 628
 629         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 630                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 631                        cmdlen, txlen);
 632                 return -EINVAL;
 633         }
 634
 635         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 636
 637         if (cmdlen == 4 || cmdlen == 5) {
 638                 /* Command with address */
 639                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 640                 /* Number of bytes to write. */
 641                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 642                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 643                 /* Get address */
 644                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 645                         cmdlen >= 5 ? 4 : 3);
 646
 647                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 648         }
 649
 650         if (txlen) {
 651                 /* writing data = yes */
 652                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 653                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 654                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 655
 656                 wr_len = txlen > 4 ? 4 : txlen;
 657                 memcpy(&wr_data, txbuf, wr_len);
 658                 writel(wr_data, reg_base +
 659                         CQSPI_REG_CMDWRITEDATALOWER);
 660
 661                 if (txlen > 4) {
 662                         txbuf += wr_len;
 663                         wr_len = txlen - wr_len;
 664                         memcpy(&wr_data, txbuf, wr_len);
 665                         writel(wr_data, reg_base +
 666                                 CQSPI_REG_CMDWRITEDATAUPPER);
 667                 }
 668         }
 669
 670         /* Execute the command */
 671         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 672 }
 673
 674 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 675 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 676         unsigned int cmdlen, const u8 *cmdbuf)
 677 {
 678         unsigned int reg;
 679         unsigned int rd_reg;
 680         unsigned int addr_value;
 681         unsigned int dummy_clk;
 682         unsigned int dummy_bytes;
 683         unsigned int addr_bytes;
 684
 685         /*
 686          * Identify addr_byte. All NOR flash device drivers are using fast read
 687          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 688          * With that, the length is in value of 5 or 6. Only FRAM chip from
 689          * ramtron using normal read (which won't need dummy byte).
 690          * Unlikely NOR flash using normal read due to performance issue.
 691          */
 692         if (cmdlen >= 5)
 693                 /* to cater fast read where cmd + addr + dummy */
 694                 addr_bytes = cmdlen - 2;
 695         else
 696                 /* for normal read (only ramtron as of now) */
 697                 addr_bytes = cmdlen - 1;
 698
 699         /* Setup the indirect trigger address */
 700         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 701                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 702
 703         /* Configure SRAM partition for read. */
 704         writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
 705                CQSPI_REG_SRAMPARTITION);
 706
 707         /* Configure the opcode */
 708         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 709
 710 #if (CONFIG_SPI_FLASH_QUAD == 1)
 711         /* Instruction and address at DQ0, data at DQ0-3. */
 712         rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 713 #endif
 714
 715         /* Get address */
 716         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 717         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 718
 719         /* The remaining lenght is dummy bytes. */
 720         dummy_bytes = cmdlen - addr_bytes - 1;
 721         if (dummy_bytes) {
 722                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 723                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 724
 725                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 726 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 727                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 728 #else
 729                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 730 #endif
 731
 732                 /* Convert to clock cycles. */
 733                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 734                 /* Need to minus the mode byte (8 clocks). */
 735                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 736
 737                 if (dummy_clk)
 738                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 739                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 740         }
 741
 742         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 743
 744         /* set device size */
 745         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 746         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 747         reg |= (addr_bytes - 1);
 748         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 749         return 0;
 750 }
 751
 752 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 753         unsigned int rxlen, u8 *rxbuf)
 754 {
 755         unsigned int reg;
 756
 757         writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 758
 759         /* Start the indirect read transfer */
 760         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 761                plat->regbase + CQSPI_REG_INDIRECTRD);
 762
 763         if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
 764                                      (const void *)plat->ahbbase, rxlen))
 765                 goto failrd;
 766
 767         /* Check flash indirect controller */
 768         reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 769         if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
 770                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 771                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 772                        reg);
 773                 goto failrd;
 774         }
 775
 776         /* Clear indirect completion status */
 777         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 778                plat->regbase + CQSPI_REG_INDIRECTRD);
 779         return 0;
 780
 781 failrd:
 782         /* Cancel the indirect read */
 783         writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 784                plat->regbase + CQSPI_REG_INDIRECTRD);
 785         return -1;
 786 }
 787
 788 /* Opcode + Address (3/4 bytes) */
 789 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 790         unsigned int cmdlen, const u8 *cmdbuf)
 791 {
 792         unsigned int reg;
 793         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 794
 795         if (cmdlen < 4 || cmdbuf == NULL) {
 796                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 797                        cmdlen, (unsigned int)cmdbuf);
 798                 return -EINVAL;
 799         }
 800         /* Setup the indirect trigger address */
 801         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 802                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 803
 804         writel(CQSPI_REG_SRAM_PARTITION_WR,
 805                plat->regbase + CQSPI_REG_SRAMPARTITION);
 806
 807         /* Configure the opcode */
 808         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 809         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 810
 811         /* Setup write address. */
 812         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 813         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 814
 815         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 816         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 817         reg |= (addr_bytes - 1);
 818         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 819         return 0;
 820 }
 821
 822 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 823         unsigned int txlen, const u8 *txbuf)
 824 {
 825         unsigned int reg = 0;
 826         unsigned int retry;
 827
 828         /* Configure the indirect read transfer bytes */
 829         writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 830
 831         /* Start the indirect write transfer */
 832         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 833                plat->regbase + CQSPI_REG_INDIRECTWR);
 834
 835         if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
 836                 goto failwr;
 837
 838         /* Wait until last write is completed (FIFO empty) */
 839         retry = CQSPI_REG_RETRY;
 840         while (retry--) {
 841                 reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
 842                 if (reg == 0)
 843                         break;
 844
 845                 udelay(1);
 846         }
 847
 848         if (reg != 0) {
 849                 printf("QSPI: timeout for indirect write\n");
 850                 goto failwr;
 851         }
 852
 853         /* Check flash indirect controller status */
 854         retry = CQSPI_REG_RETRY;
 855         while (retry--) {
 856                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
 857                 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
 858                         break;
 859                 udelay(1);
 860         }
 861
 862         if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
 863                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 864                        reg);
 865                 goto failwr;
 866         }
 867
 868         /* Clear indirect completion status */
 869         writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
 870                plat->regbase + CQSPI_REG_INDIRECTWR);
 871         return 0;
 872
 873 failwr:
 874         /* Cancel the indirect write */
 875         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 876                plat->regbase + CQSPI_REG_INDIRECTWR);
 877         return -1;
 878 }
 879
 880 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 881 {
 882         unsigned int reg;
 883
 884         /* enter XiP mode immediately and enable direct mode */
 885         reg = readl(reg_base + CQSPI_REG_CONFIG);
 886         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 887         reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 888         reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
 889         writel(reg, reg_base + CQSPI_REG_CONFIG);
 890
 891         /* keep the XiP mode */
 892         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 893
 894         /* Enable mode bit at devrd */
 895         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 896         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 897         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 898 }