3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/immap.h>
18 struct spi_slave slave;
23 int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
24 void *din, ulong flags);
25 struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode);
26 void cfspi_init(void);
27 void cfspi_tx(u32 ctrl, u16 data);
30 extern void cfspi_port_conf(void);
31 extern int cfspi_claim_bus(uint bus, uint cs);
32 extern void cfspi_release_bus(uint bus, uint cs);
34 DECLARE_GLOBAL_DATA_PTR;
36 #ifndef CONFIG_SPI_IDLE_VAL
37 #if defined(CONFIG_SPI_MMC)
38 #define CONFIG_SPI_IDLE_VAL 0xFFFF
40 #define CONFIG_SPI_IDLE_VAL 0x0
44 #if defined(CONFIG_CF_DSPI)
45 /* DSPI specific mode */
46 #define SPI_MODE_MOD 0x00200000
47 #define SPI_DBLRATE 0x00100000
49 static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
51 return container_of(slave, struct cf_spi_slave, slave);
56 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
58 cfspi_port_conf(); /* port configuration */
60 dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
61 DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
62 DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
63 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
65 /* Default setting in platform configuration */
66 #ifdef CONFIG_SYS_DSPI_CTAR0
67 dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
69 #ifdef CONFIG_SYS_DSPI_CTAR1
70 dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
72 #ifdef CONFIG_SYS_DSPI_CTAR2
73 dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
75 #ifdef CONFIG_SYS_DSPI_CTAR3
76 dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
78 #ifdef CONFIG_SYS_DSPI_CTAR4
79 dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
81 #ifdef CONFIG_SYS_DSPI_CTAR5
82 dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
84 #ifdef CONFIG_SYS_DSPI_CTAR6
85 dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
87 #ifdef CONFIG_SYS_DSPI_CTAR7
88 dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
92 void cfspi_tx(u32 ctrl, u16 data)
94 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
96 while ((dspi->sr & 0x0000F000) >= 4) ;
98 dspi->tfr = (ctrl | data);
103 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
105 while ((dspi->sr & 0x000000F0) == 0) ;
107 return (dspi->rfr & 0xFFFF);
110 int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
111 void *din, ulong flags)
113 struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
114 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
115 u8 *spi_rd = NULL, *spi_wr = NULL;
117 uint len = bitlen >> 3;
119 if (cfslave->charbit == 16) {
121 spi_wr16 = (u16 *) dout;
122 spi_rd16 = (u16 *) din;
124 spi_wr = (u8 *) dout;
128 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
129 ctrl |= DSPI_TFR_CONT;
131 ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
134 int tmp_len = len - 1;
137 if (cfslave->charbit == 16)
138 cfspi_tx(ctrl, *spi_wr16++);
140 cfspi_tx(ctrl, *spi_wr++);
145 cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
146 if (cfslave->charbit == 16)
147 *spi_rd16++ = cfspi_rx();
149 *spi_rd++ = cfspi_rx();
153 len = 1; /* remaining byte */
156 if ((flags & SPI_XFER_END) == SPI_XFER_END)
157 ctrl &= ~DSPI_TFR_CONT;
161 if (cfslave->charbit == 16)
162 cfspi_tx(ctrl, *spi_wr16);
164 cfspi_tx(ctrl, *spi_wr);
169 cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
170 if (cfslave->charbit == 16)
171 *spi_rd16 = cfspi_rx();
173 *spi_rd = cfspi_rx();
177 cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
184 struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode)
187 * bit definition for mode:
188 * bit 31 - 28: Transfer size 3 to 16 bits
189 * 27 - 26: PCS to SCK delay prescaler
190 * 25 - 24: After SCK delay prescaler
191 * 23 - 22: Delay after transfer prescaler
192 * 21 : Allow overwrite for bit 31-22 and bit 20-8
193 * 20 : Double baud rate
194 * 19 - 16: PCS to SCK delay scaler
195 * 15 - 12: After SCK delay scaler
196 * 11 - 8: Delay after transfer scaler
197 * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
199 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
200 int prescaler[] = { 2, 3, 5, 7 };
204 256, 512, 1024, 2048,
205 4096, 8192, 16384, 32768
207 int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
208 int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
211 tmp = (prescaler[3] * scaler[15]);
212 /* Maximum and minimum baudrate it can handle */
213 if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
214 (cfslave->baudrate < (gd->bus_clk / tmp))) {
215 printf("Exceed baudrate limitation: Max %d - Min %d\n",
216 (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
220 /* Activate Double Baud when it exceed 1/4 the bus clk */
221 if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
222 (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
223 bus_setup |= DSPI_CTAR_DBR;
228 bus_setup |= DSPI_CTAR_CPOL;
230 bus_setup |= DSPI_CTAR_CPHA;
231 if (mode & SPI_LSB_FIRST)
232 bus_setup |= DSPI_CTAR_LSBFE;
234 /* Overwrite default value set in platform configuration file */
235 if (mode & SPI_MODE_MOD) {
237 if ((mode & 0xF0000000) == 0)
239 dspi->ctar[cfslave->slave.bus] & 0x78000000;
241 bus_setup |= ((mode & 0xF0000000) >> 1);
244 * Check to see if it is enabled by default in platform
245 * config, or manual setting passed by mode parameter
247 if (mode & SPI_DBLRATE) {
248 bus_setup |= DSPI_CTAR_DBR;
251 bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
252 bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
254 bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
257 ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
258 0x78000000) ? 16 : 8;
260 pbrcnt = sizeof(prescaler) / sizeof(int);
261 brcnt = sizeof(scaler) / sizeof(int);
263 /* baudrate calculation - to closer value, may not be exact match */
264 for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
265 baud_speed = gd->bus_clk / prescaler[i];
266 for (j = 0; j < brcnt; j++) {
267 tmp = (baud_speed / scaler[j]) * (1 + dbr);
269 if (tmp > cfslave->baudrate)
270 diff = tmp - cfslave->baudrate;
272 diff = cfslave->baudrate - tmp;
274 if (diff < bestmatch) {
281 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
282 dspi->ctar[cfslave->slave.bus] = bus_setup;
284 return &cfslave->slave;
286 #endif /* CONFIG_CF_DSPI */
288 #ifdef CONFIG_CF_QSPI
290 #endif /* CONFIG_CF_QSPI */
292 #ifdef CONFIG_CMD_SPI
293 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
295 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
301 void spi_init_f(void)
305 void spi_init_r(void)
314 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
315 unsigned int max_hz, unsigned int mode)
317 struct cf_spi_slave *cfslave;
319 if (!spi_cs_is_valid(bus, cs))
322 cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
326 cfslave->baudrate = max_hz;
329 return cfspi_setup_slave(cfslave, mode);
332 void spi_free_slave(struct spi_slave *slave)
334 struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
339 int spi_claim_bus(struct spi_slave *slave)
341 return cfspi_claim_bus(slave->bus, slave->cs);
344 void spi_release_bus(struct spi_slave *slave)
346 cfspi_release_bus(slave->bus, slave->cs);
349 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
350 void *din, unsigned long flags)
352 return cfspi_xfer(slave, bitlen, dout, din, flags);
354 #endif /* CONFIG_CMD_SPI */