2 * Copyright (C) 2009 Texas Instruments.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/interrupt.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/slab.h>
33 #include <mach/edma.h>
35 #define SPI_NO_RESOURCE ((resource_size_t)-1)
37 #define SPI_MAX_CHIPSELECT 2
39 #define CS_DEFAULT 0xFF
41 #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42 #define DAVINCI_DMA_DATA_TYPE_S8 0x01
43 #define DAVINCI_DMA_DATA_TYPE_S16 0x02
44 #define DAVINCI_DMA_DATA_TYPE_S32 0x04
46 #define SPIFMT_PHASE_MASK BIT(16)
47 #define SPIFMT_POLARITY_MASK BIT(17)
48 #define SPIFMT_DISTIMER_MASK BIT(18)
49 #define SPIFMT_SHIFTDIR_MASK BIT(20)
50 #define SPIFMT_WAITENA_MASK BIT(21)
51 #define SPIFMT_PARITYENA_MASK BIT(22)
52 #define SPIFMT_ODD_PARITY_MASK BIT(23)
53 #define SPIFMT_WDELAY_MASK 0x3f000000u
54 #define SPIFMT_WDELAY_SHIFT 24
55 #define SPIFMT_CHARLEN_MASK 0x0000001Fu
58 #define SPIGCR1_SPIENA_MASK 0x01000000u
61 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
62 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
63 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
64 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
65 #define SPIPC0_EN1FUN_MASK BIT(1)
66 #define SPIPC0_EN0FUN_MASK BIT(0)
68 #define SPIINT_MASKALL 0x0101035F
69 #define SPI_INTLVL_1 0x000001FFu
70 #define SPI_INTLVL_0 0x00000000u
73 #define SPIDAT1_CSHOLD_SHIFT 28
74 #define SPIDAT1_CSNR_SHIFT 16
75 #define SPIGCR1_CLKMOD_MASK BIT(1)
76 #define SPIGCR1_MASTER_MASK BIT(0)
77 #define SPIGCR1_LOOPBACK_MASK BIT(16)
80 #define SPIBUF_TXFULL_MASK BIT(29)
81 #define SPIBUF_RXEMPTY_MASK BIT(31)
84 #define SPIFLG_DLEN_ERR_MASK BIT(0)
85 #define SPIFLG_TIMEOUT_MASK BIT(1)
86 #define SPIFLG_PARERR_MASK BIT(2)
87 #define SPIFLG_DESYNC_MASK BIT(3)
88 #define SPIFLG_BITERR_MASK BIT(4)
89 #define SPIFLG_OVRRUN_MASK BIT(6)
90 #define SPIFLG_RX_INTR_MASK BIT(8)
91 #define SPIFLG_TX_INTR_MASK BIT(9)
92 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
93 #define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
94 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
95 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
96 | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
97 | SPIFLG_TX_INTR_MASK \
98 | SPIFLG_BUF_INIT_ACTIVE_MASK)
100 #define SPIINT_DLEN_ERR_INTR BIT(0)
101 #define SPIINT_TIMEOUT_INTR BIT(1)
102 #define SPIINT_PARERR_INTR BIT(2)
103 #define SPIINT_DESYNC_INTR BIT(3)
104 #define SPIINT_BITERR_INTR BIT(4)
105 #define SPIINT_OVRRUN_INTR BIT(6)
106 #define SPIINT_RX_INTR BIT(8)
107 #define SPIINT_TX_INTR BIT(9)
108 #define SPIINT_DMA_REQ_EN BIT(16)
109 #define SPIINT_ENABLE_HIGHZ BIT(24)
111 #define SPI_T2CDELAY_SHIFT 16
112 #define SPI_C2TDELAY_SHIFT 24
114 /* SPI Controller registers */
133 #define SPIDELAY 0x48
139 #define TGINTVEC0 0x60
140 #define TGINTVEC1 0x64
142 struct davinci_spi_slave {
144 u32 clk_ctrl_to_write;
149 /* We have 2 DMA channels per CS, one for RX and one for TX */
150 struct davinci_spi_dma {
155 enum dma_event_q eventq;
157 struct completion dma_tx_completion;
158 struct completion dma_rx_completion;
161 /* SPI Controller driver's private data. */
163 struct spi_bitbang bitbang;
167 resource_size_t pbase;
171 struct completion done;
177 struct davinci_spi_dma *dma_channels;
178 struct davinci_spi_platform_data *pdata;
180 void (*get_rx)(u32 rx_data, struct davinci_spi *);
181 u32 (*get_tx)(struct davinci_spi *);
183 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
186 static unsigned use_dma;
188 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
190 u8 *rx = davinci_spi->rx;
193 davinci_spi->rx = rx;
196 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
198 u16 *rx = davinci_spi->rx;
201 davinci_spi->rx = rx;
204 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
207 const u8 *tx = davinci_spi->tx;
210 davinci_spi->tx = tx;
214 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
217 const u16 *tx = davinci_spi->tx;
220 davinci_spi->tx = tx;
224 static inline void set_io_bits(void __iomem *addr, u32 bits)
226 u32 v = ioread32(addr);
232 static inline void clear_io_bits(void __iomem *addr, u32 bits)
234 u32 v = ioread32(addr);
240 static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
242 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
245 static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
247 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
250 static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
252 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
255 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
257 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
261 * Interface to control the chip select signal
263 static void davinci_spi_chipselect(struct spi_device *spi, int value)
265 struct davinci_spi *davinci_spi;
266 struct davinci_spi_platform_data *pdata;
267 u32 data1_reg_val = 0;
269 davinci_spi = spi_master_get_devdata(spi->master);
270 pdata = davinci_spi->pdata;
273 * Board specific chip select logic decides the polarity and cs
274 * line for the controller
276 if (value == BITBANG_CS_INACTIVE) {
277 set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
279 data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
280 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
282 while ((ioread32(davinci_spi->base + SPIBUF)
283 & SPIBUF_RXEMPTY_MASK) == 0)
289 * davinci_spi_setup_transfer - This functions will determine transfer method
290 * @spi: spi device on which data transfer to be done
291 * @t: spi transfer in which transfer info is filled
293 * This function determines data transfer method (8/16/32 bit transfer).
294 * It will also set the SPI Clock Control register according to
295 * SPI slave device freq.
297 static int davinci_spi_setup_transfer(struct spi_device *spi,
298 struct spi_transfer *t)
301 struct davinci_spi *davinci_spi;
302 struct davinci_spi_platform_data *pdata;
303 u8 bits_per_word = 0;
304 u32 hz = 0, prescale = 0, clkspeed;
306 davinci_spi = spi_master_get_devdata(spi->master);
307 pdata = davinci_spi->pdata;
310 bits_per_word = t->bits_per_word;
314 /* if bits_per_word is not set then set it default */
316 bits_per_word = spi->bits_per_word;
319 * Assign function pointer to appropriate transfer method
320 * 8bit, 16bit or 32bit transfer
322 if (bits_per_word <= 8 && bits_per_word >= 2) {
323 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
324 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
325 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
326 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
327 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
328 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
329 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
334 hz = spi->max_speed_hz;
336 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
341 clkspeed = clk_get_rate(davinci_spi->clk);
342 if (hz > clkspeed / 2)
344 if (hz < clkspeed / 256)
347 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
349 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
350 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
355 static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
357 struct spi_device *spi = (struct spi_device *)data;
358 struct davinci_spi *davinci_spi;
359 struct davinci_spi_dma *davinci_spi_dma;
360 struct davinci_spi_platform_data *pdata;
362 davinci_spi = spi_master_get_devdata(spi->master);
363 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
364 pdata = davinci_spi->pdata;
366 if (ch_status == DMA_COMPLETE)
367 edma_stop(davinci_spi_dma->dma_rx_channel);
369 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
371 complete(&davinci_spi_dma->dma_rx_completion);
372 /* We must disable the DMA RX request */
373 davinci_spi_set_dma_req(spi, 0);
376 static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
378 struct spi_device *spi = (struct spi_device *)data;
379 struct davinci_spi *davinci_spi;
380 struct davinci_spi_dma *davinci_spi_dma;
381 struct davinci_spi_platform_data *pdata;
383 davinci_spi = spi_master_get_devdata(spi->master);
384 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
385 pdata = davinci_spi->pdata;
387 if (ch_status == DMA_COMPLETE)
388 edma_stop(davinci_spi_dma->dma_tx_channel);
390 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
392 complete(&davinci_spi_dma->dma_tx_completion);
393 /* We must disable the DMA TX request */
394 davinci_spi_set_dma_req(spi, 0);
397 static int davinci_spi_request_dma(struct spi_device *spi)
399 struct davinci_spi *davinci_spi;
400 struct davinci_spi_dma *davinci_spi_dma;
401 struct davinci_spi_platform_data *pdata;
405 davinci_spi = spi_master_get_devdata(spi->master);
406 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
407 pdata = davinci_spi->pdata;
408 sdev = davinci_spi->bitbang.master->dev.parent;
410 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
411 davinci_spi_dma_rx_callback, spi,
412 davinci_spi_dma->eventq);
414 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
417 davinci_spi_dma->dma_rx_channel = r;
418 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
419 davinci_spi_dma_tx_callback, spi,
420 davinci_spi_dma->eventq);
422 edma_free_channel(davinci_spi_dma->dma_rx_channel);
423 davinci_spi_dma->dma_rx_channel = -1;
424 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
427 davinci_spi_dma->dma_tx_channel = r;
433 * davinci_spi_setup - This functions will set default transfer method
434 * @spi: spi device on which data transfer to be done
436 * This functions sets the default transfer method.
439 static int davinci_spi_setup(struct spi_device *spi)
442 struct davinci_spi *davinci_spi;
443 struct davinci_spi_dma *davinci_spi_dma;
446 davinci_spi = spi_master_get_devdata(spi->master);
447 sdev = davinci_spi->bitbang.master->dev.parent;
449 /* if bits per word length is zero then set it default 8 */
450 if (!spi->bits_per_word)
451 spi->bits_per_word = 8;
453 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
455 if (use_dma && davinci_spi->dma_channels) {
456 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
458 if ((davinci_spi_dma->dma_rx_channel == -1)
459 || (davinci_spi_dma->dma_tx_channel == -1)) {
460 retval = davinci_spi_request_dma(spi);
467 * SPI in DaVinci and DA8xx operate between
470 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
471 dev_dbg(sdev, "Operating frequency is not in acceptable "
477 * Set up SPIFMTn register, unique to this chipselect.
479 * NOTE: we could do all of these with one write. Also, some
480 * of the "version 2" features are found in chips that don't
481 * support all of them...
483 if (spi->mode & SPI_LSB_FIRST)
484 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
487 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
490 if (spi->mode & SPI_CPOL)
491 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
494 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
497 if (!(spi->mode & SPI_CPHA))
498 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
501 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
505 * Version 1 hardware supports two basic SPI modes:
506 * - Standard SPI mode uses 4 pins, with chipselect
507 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
508 * (distinct from SPI_3WIRE, with just one data wire;
509 * or similar variants without MOSI or without MISO)
511 * Version 2 hardware supports an optional handshaking signal,
512 * so it can support two more modes:
513 * - 5 pin SPI variant is standard SPI plus SPI_READY
514 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
517 if (davinci_spi->version == SPI_VERSION_2) {
518 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
520 set_fmt_bits(davinci_spi->base,
521 (davinci_spi->pdata->wdelay
522 << SPIFMT_WDELAY_SHIFT)
523 & SPIFMT_WDELAY_MASK,
526 if (davinci_spi->pdata->odd_parity)
527 set_fmt_bits(davinci_spi->base,
528 SPIFMT_ODD_PARITY_MASK,
531 clear_fmt_bits(davinci_spi->base,
532 SPIFMT_ODD_PARITY_MASK,
535 if (davinci_spi->pdata->parity_enable)
536 set_fmt_bits(davinci_spi->base,
537 SPIFMT_PARITYENA_MASK,
540 clear_fmt_bits(davinci_spi->base,
541 SPIFMT_PARITYENA_MASK,
544 if (davinci_spi->pdata->wait_enable)
545 set_fmt_bits(davinci_spi->base,
549 clear_fmt_bits(davinci_spi->base,
553 if (davinci_spi->pdata->timer_disable)
554 set_fmt_bits(davinci_spi->base,
555 SPIFMT_DISTIMER_MASK,
558 clear_fmt_bits(davinci_spi->base,
559 SPIFMT_DISTIMER_MASK,
563 retval = davinci_spi_setup_transfer(spi, NULL);
568 static void davinci_spi_cleanup(struct spi_device *spi)
570 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
571 struct davinci_spi_dma *davinci_spi_dma;
573 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
575 if (use_dma && davinci_spi->dma_channels) {
576 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
578 if ((davinci_spi_dma->dma_rx_channel != -1)
579 && (davinci_spi_dma->dma_tx_channel != -1)) {
580 edma_free_channel(davinci_spi_dma->dma_tx_channel);
581 edma_free_channel(davinci_spi_dma->dma_rx_channel);
586 static int davinci_spi_bufs_prep(struct spi_device *spi,
587 struct davinci_spi *davinci_spi)
592 * REVISIT unless devices disagree about SPI_LOOP or
593 * SPI_READY (SPI_NO_CS only allows one device!), this
594 * should not need to be done before each message...
595 * optimize for both flags staying cleared.
598 op_mode = SPIPC0_DIFUN_MASK
600 | SPIPC0_CLKFUN_MASK;
601 if (!(spi->mode & SPI_NO_CS))
602 op_mode |= 1 << spi->chip_select;
603 if (spi->mode & SPI_READY)
604 op_mode |= SPIPC0_SPIENA_MASK;
606 iowrite32(op_mode, davinci_spi->base + SPIPC0);
608 if (spi->mode & SPI_LOOP)
609 set_io_bits(davinci_spi->base + SPIGCR1,
610 SPIGCR1_LOOPBACK_MASK);
612 clear_io_bits(davinci_spi->base + SPIGCR1,
613 SPIGCR1_LOOPBACK_MASK);
618 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
621 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
623 if (int_status & SPIFLG_TIMEOUT_MASK) {
624 dev_dbg(sdev, "SPI Time-out Error\n");
627 if (int_status & SPIFLG_DESYNC_MASK) {
628 dev_dbg(sdev, "SPI Desynchronization Error\n");
631 if (int_status & SPIFLG_BITERR_MASK) {
632 dev_dbg(sdev, "SPI Bit error\n");
636 if (davinci_spi->version == SPI_VERSION_2) {
637 if (int_status & SPIFLG_DLEN_ERR_MASK) {
638 dev_dbg(sdev, "SPI Data Length Error\n");
641 if (int_status & SPIFLG_PARERR_MASK) {
642 dev_dbg(sdev, "SPI Parity Error\n");
645 if (int_status & SPIFLG_OVRRUN_MASK) {
646 dev_dbg(sdev, "SPI Data Overrun error\n");
649 if (int_status & SPIFLG_TX_INTR_MASK) {
650 dev_dbg(sdev, "SPI TX intr bit set\n");
653 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
654 dev_dbg(sdev, "SPI Buffer Init Active\n");
663 * davinci_spi_bufs - functions which will handle transfer data
664 * @spi: spi device on which data transfer to be done
665 * @t: spi transfer in which transfer info is filled
667 * This function will put data to be transferred into data register
668 * of SPI controller and then wait until the completion will be marked
669 * by the IRQ Handler.
671 static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
673 struct davinci_spi *davinci_spi;
674 int int_status, count, ret;
676 u32 tx_data, data1_reg_val;
677 u32 buf_val, flg_val;
678 struct davinci_spi_platform_data *pdata;
680 davinci_spi = spi_master_get_devdata(spi->master);
681 pdata = davinci_spi->pdata;
683 davinci_spi->tx = t->tx_buf;
684 davinci_spi->rx = t->rx_buf;
686 /* convert len to words based on bits_per_word */
687 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
688 davinci_spi->count = t->len / conv;
690 INIT_COMPLETION(davinci_spi->done);
692 ret = davinci_spi_bufs_prep(spi, davinci_spi);
697 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
699 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
700 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
701 davinci_spi->base + SPIDELAY);
703 count = davinci_spi->count;
704 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
705 tmp = ~(0x1 << spi->chip_select);
707 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
709 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
711 while ((ioread32(davinci_spi->base + SPIBUF)
712 & SPIBUF_RXEMPTY_MASK) == 0)
715 /* Determine the command to execute READ or WRITE */
717 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
720 tx_data = davinci_spi->get_tx(davinci_spi);
722 data1_reg_val &= ~(0xFFFF);
723 data1_reg_val |= (0xFFFF & tx_data);
725 buf_val = ioread32(davinci_spi->base + SPIBUF);
726 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
727 iowrite32(data1_reg_val,
728 davinci_spi->base + SPIDAT1);
732 while (ioread32(davinci_spi->base + SPIBUF)
733 & SPIBUF_RXEMPTY_MASK)
736 /* getting the returned byte */
738 buf_val = ioread32(davinci_spi->base + SPIBUF);
739 davinci_spi->get_rx(buf_val, davinci_spi);
745 if (pdata->poll_mode) {
747 /* keeps the serial clock going */
748 if ((ioread32(davinci_spi->base + SPIBUF)
749 & SPIBUF_TXFULL_MASK) == 0)
750 iowrite32(data1_reg_val,
751 davinci_spi->base + SPIDAT1);
753 while (ioread32(davinci_spi->base + SPIBUF) &
757 flg_val = ioread32(davinci_spi->base + SPIFLG);
758 buf_val = ioread32(davinci_spi->base + SPIBUF);
760 davinci_spi->get_rx(buf_val, davinci_spi);
766 } else { /* Receive in Interrupt mode */
769 for (i = 0; i < davinci_spi->count; i++) {
770 set_io_bits(davinci_spi->base + SPIINT,
775 iowrite32(data1_reg_val,
776 davinci_spi->base + SPIDAT1);
778 while (ioread32(davinci_spi->base + SPIINT) &
782 iowrite32((data1_reg_val & 0x0ffcffff),
783 davinci_spi->base + SPIDAT1);
788 * Check for bit error, desync error,parity error,timeout error and
789 * receive overflow errors
791 int_status = ioread32(davinci_spi->base + SPIFLG);
793 ret = davinci_spi_check_error(davinci_spi, int_status);
797 /* SPI Framework maintains the count only in bytes so convert back */
798 davinci_spi->count *= conv;
803 #define DAVINCI_DMA_DATA_TYPE_S8 0x01
804 #define DAVINCI_DMA_DATA_TYPE_S16 0x02
805 #define DAVINCI_DMA_DATA_TYPE_S32 0x04
807 static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
809 struct davinci_spi *davinci_spi;
811 int count, temp_count;
815 struct davinci_spi_dma *davinci_spi_dma;
816 int word_len, data_type, ret;
817 unsigned long tx_reg, rx_reg;
818 struct davinci_spi_platform_data *pdata;
821 davinci_spi = spi_master_get_devdata(spi->master);
822 pdata = davinci_spi->pdata;
823 sdev = davinci_spi->bitbang.master->dev.parent;
825 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
827 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
828 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
830 davinci_spi->tx = t->tx_buf;
831 davinci_spi->rx = t->rx_buf;
833 /* convert len to words based on bits_per_word */
834 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
835 davinci_spi->count = t->len / conv;
837 INIT_COMPLETION(davinci_spi->done);
839 init_completion(&davinci_spi_dma->dma_rx_completion);
840 init_completion(&davinci_spi_dma->dma_tx_completion);
845 data_type = DAVINCI_DMA_DATA_TYPE_S8;
846 else if (word_len <= 16)
847 data_type = DAVINCI_DMA_DATA_TYPE_S16;
848 else if (word_len <= 32)
849 data_type = DAVINCI_DMA_DATA_TYPE_S32;
853 ret = davinci_spi_bufs_prep(spi, davinci_spi);
857 /* Put delay val if required */
858 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
859 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
860 davinci_spi->base + SPIDELAY);
862 count = davinci_spi->count; /* the number of elements */
863 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
865 /* CS default = 0xFF */
866 tmp = ~(0x1 << spi->chip_select);
868 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
870 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
872 /* disable all interrupts for dma transfers */
873 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
874 /* Disable SPI to write configuration bits in SPIDAT */
875 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
876 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
878 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
880 while ((ioread32(davinci_spi->base + SPIBUF)
881 & SPIBUF_RXEMPTY_MASK) == 0)
886 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
888 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
889 dev_dbg(sdev, "Unable to DMA map a %d bytes"
890 " TX buffer\n", count);
895 /* We need TX clocking for RX transaction */
896 t->tx_dma = dma_map_single(&spi->dev,
897 (void *)davinci_spi->tmp_buf, count + 1,
899 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
900 dev_dbg(sdev, "Unable to DMA map a %d bytes"
901 " TX tmp buffer\n", count);
904 temp_count = count + 1;
907 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
908 data_type, temp_count, 1, 0, ASYNC);
909 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
910 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
911 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
912 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
915 /* initiate transaction */
916 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
918 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
920 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
921 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
923 if (t->tx_buf != NULL)
924 dma_unmap_single(NULL, t->tx_dma,
925 count, DMA_TO_DEVICE);
928 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
929 data_type, count, 1, 0, ASYNC);
930 edma_set_src(davinci_spi_dma->dma_rx_channel,
931 rx_reg, INCR, W8BIT);
932 edma_set_dest(davinci_spi_dma->dma_rx_channel,
933 t->rx_dma, INCR, W8BIT);
934 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
935 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
939 if ((t->tx_buf) || (t->rx_buf))
940 edma_start(davinci_spi_dma->dma_tx_channel);
943 edma_start(davinci_spi_dma->dma_rx_channel);
945 if ((t->rx_buf) || (t->tx_buf))
946 davinci_spi_set_dma_req(spi, 1);
949 wait_for_completion_interruptible(
950 &davinci_spi_dma->dma_tx_completion);
953 wait_for_completion_interruptible(
954 &davinci_spi_dma->dma_rx_completion);
956 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
959 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
962 * Check for bit error, desync error,parity error,timeout error and
963 * receive overflow errors
965 int_status = ioread32(davinci_spi->base + SPIFLG);
967 ret = davinci_spi_check_error(davinci_spi, int_status);
971 /* SPI Framework maintains the count only in bytes so convert back */
972 davinci_spi->count *= conv;
978 * davinci_spi_irq - IRQ handler for DaVinci SPI
979 * @irq: IRQ number for this SPI Master
980 * @context_data: structure for SPI Master controller davinci_spi
982 static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
984 struct davinci_spi *davinci_spi = context_data;
985 u32 int_status, rx_data = 0;
986 irqreturn_t ret = IRQ_NONE;
988 int_status = ioread32(davinci_spi->base + SPIFLG);
990 while ((int_status & SPIFLG_RX_INTR_MASK)) {
991 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
994 rx_data = ioread32(davinci_spi->base + SPIBUF);
995 davinci_spi->get_rx(rx_data, davinci_spi);
997 /* Disable Receive Interrupt */
998 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
999 davinci_spi->base + SPIINT);
1001 (void)davinci_spi_check_error(davinci_spi, int_status);
1003 int_status = ioread32(davinci_spi->base + SPIFLG);
1010 * davinci_spi_probe - probe function for SPI Master Controller
1011 * @pdev: platform_device structure which contains plateform specific data
1013 static int davinci_spi_probe(struct platform_device *pdev)
1015 struct spi_master *master;
1016 struct davinci_spi *davinci_spi;
1017 struct davinci_spi_platform_data *pdata;
1018 struct resource *r, *mem;
1019 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
1020 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
1021 resource_size_t dma_eventq = SPI_NO_RESOURCE;
1024 pdata = pdev->dev.platform_data;
1025 if (pdata == NULL) {
1030 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
1031 if (master == NULL) {
1036 dev_set_drvdata(&pdev->dev, master);
1038 davinci_spi = spi_master_get_devdata(master);
1039 if (davinci_spi == NULL) {
1044 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050 davinci_spi->pbase = r->start;
1051 davinci_spi->region_size = resource_size(r);
1052 davinci_spi->pdata = pdata;
1054 mem = request_mem_region(r->start, davinci_spi->region_size,
1061 davinci_spi->base = (struct davinci_spi_reg __iomem *)
1062 ioremap(r->start, davinci_spi->region_size);
1063 if (davinci_spi->base == NULL) {
1065 goto release_region;
1068 davinci_spi->irq = platform_get_irq(pdev, 0);
1069 if (davinci_spi->irq <= 0) {
1074 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1075 dev_name(&pdev->dev), davinci_spi);
1079 /* Allocate tmp_buf for tx_buf */
1080 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1081 if (davinci_spi->tmp_buf == NULL) {
1086 davinci_spi->bitbang.master = spi_master_get(master);
1087 if (davinci_spi->bitbang.master == NULL) {
1092 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1093 if (IS_ERR(davinci_spi->clk)) {
1097 clk_enable(davinci_spi->clk);
1100 master->bus_num = pdev->id;
1101 master->num_chipselect = pdata->num_chipselect;
1102 master->setup = davinci_spi_setup;
1103 master->cleanup = davinci_spi_cleanup;
1105 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1106 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1108 davinci_spi->version = pdata->version;
1109 use_dma = pdata->use_dma;
1111 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1112 if (davinci_spi->version == SPI_VERSION_2)
1113 davinci_spi->bitbang.flags |= SPI_READY;
1116 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1118 dma_rx_chan = r->start;
1119 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1121 dma_tx_chan = r->start;
1122 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1124 dma_eventq = r->start;
1128 dma_rx_chan == SPI_NO_RESOURCE ||
1129 dma_tx_chan == SPI_NO_RESOURCE ||
1130 dma_eventq == SPI_NO_RESOURCE) {
1131 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1134 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1135 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1136 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1137 if (davinci_spi->dma_channels == NULL) {
1142 for (i = 0; i < master->num_chipselect; i++) {
1143 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1144 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1146 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1147 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1149 davinci_spi->dma_channels[i].eventq = dma_eventq;
1151 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1152 "Using RX channel = %d , TX channel = %d and "
1153 "event queue = %d", dma_rx_chan, dma_tx_chan,
1157 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1158 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1160 init_completion(&davinci_spi->done);
1162 /* Reset In/OUT SPI module */
1163 iowrite32(0, davinci_spi->base + SPIGCR0);
1165 iowrite32(1, davinci_spi->base + SPIGCR0);
1167 /* Clock internal */
1168 if (davinci_spi->pdata->clk_internal)
1169 set_io_bits(davinci_spi->base + SPIGCR1,
1170 SPIGCR1_CLKMOD_MASK);
1172 clear_io_bits(davinci_spi->base + SPIGCR1,
1173 SPIGCR1_CLKMOD_MASK);
1175 /* master mode default */
1176 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1178 if (davinci_spi->pdata->intr_level)
1179 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1181 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1183 ret = spi_bitbang_start(&davinci_spi->bitbang);
1187 dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
1189 if (!pdata->poll_mode)
1190 dev_info(&pdev->dev, "Operating in interrupt mode"
1191 " using IRQ %d\n", davinci_spi->irq);
1196 clk_disable(davinci_spi->clk);
1197 clk_put(davinci_spi->clk);
1199 spi_master_put(master);
1201 kfree(davinci_spi->tmp_buf);
1203 free_irq(davinci_spi->irq, davinci_spi);
1205 iounmap(davinci_spi->base);
1207 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1215 * davinci_spi_remove - remove function for SPI Master Controller
1216 * @pdev: platform_device structure which contains plateform specific data
1218 * This function will do the reverse action of davinci_spi_probe function
1219 * It will free the IRQ and SPI controller's memory region.
1220 * It will also call spi_bitbang_stop to destroy the work queue which was
1221 * created by spi_bitbang_start.
1223 static int __exit davinci_spi_remove(struct platform_device *pdev)
1225 struct davinci_spi *davinci_spi;
1226 struct spi_master *master;
1228 master = dev_get_drvdata(&pdev->dev);
1229 davinci_spi = spi_master_get_devdata(master);
1231 spi_bitbang_stop(&davinci_spi->bitbang);
1233 clk_disable(davinci_spi->clk);
1234 clk_put(davinci_spi->clk);
1235 spi_master_put(master);
1236 kfree(davinci_spi->tmp_buf);
1237 free_irq(davinci_spi->irq, davinci_spi);
1238 iounmap(davinci_spi->base);
1239 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1244 static struct platform_driver davinci_spi_driver = {
1245 .driver.name = "spi_davinci",
1246 .remove = __exit_p(davinci_spi_remove),
1249 static int __init davinci_spi_init(void)
1251 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1253 module_init(davinci_spi_init);
1255 static void __exit davinci_spi_exit(void)
1257 platform_driver_unregister(&davinci_spi_driver);
1259 module_exit(davinci_spi_exit);
1261 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1262 MODULE_LICENSE("GPL");