drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include "dw_spi.h"
  28
  29 #ifdef CONFIG_DEBUG_FS
  30 #include <linux/debugfs.h>
  31 #endif
  32
  33 #define START_STATE     ((void *)0)
  34 #define RUNNING_STATE   ((void *)1)
  35 #define DONE_STATE      ((void *)2)
  36 #define ERROR_STATE     ((void *)-1)
  37
  38 #define QUEUE_RUNNING   0
  39 #define QUEUE_STOPPED   1
  40
  41 #define MRST_SPI_DEASSERT       0
  42 #define MRST_SPI_ASSERT         1
  43
  44 /* Slave spi_dev related */
  45 struct chip_data {
  46         u16 cr0;
  47         u8 cs;                  /* chip select pin */
  48         u8 n_bytes;             /* current is a 1/2/4 byte op */
  49         u8 tmode;               /* TR/TO/RO/EEPROM */
  50         u8 type;                /* SPI/SSP/MicroWire */
  51
  52         u8 poll_mode;           /* 1 means use poll mode */
  53
  54         u32 dma_width;
  55         u32 rx_threshold;
  56         u32 tx_threshold;
  57         u8 enable_dma;
  58         u8 bits_per_word;
  59         u16 clk_div;            /* baud rate divider */
  60         u32 speed_hz;           /* baud rate */
  61         void (*cs_control)(u32 command);
  62 };
  63
  64 #ifdef CONFIG_DEBUG_FS
  65 static int spi_show_regs_open(struct inode *inode, struct file *file)
  66 {
  67         file->private_data = inode->i_private;
  68         return 0;
  69 }
  70
  71 #define SPI_REGS_BUFSIZE        1024
  72 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  73                                 size_t count, loff_t *ppos)
  74 {
  75         struct dw_spi *dws;
  76         char *buf;
  77         u32 len = 0;
  78         ssize_t ret;
  79
  80         dws = file->private_data;
  81
  82         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  83         if (!buf)
  84                 return 0;
  85
  86         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87                         "MRST SPI0 registers:\n");
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "=================================\n");
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "=================================\n");
 122
 123         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 124         kfree(buf);
 125         return ret;
 126 }
 127
 128 static const struct file_operations mrst_spi_regs_ops = {
 129         .owner          = THIS_MODULE,
 130         .open           = spi_show_regs_open,
 131         .read           = spi_show_regs,
 132         .llseek         = default_llseek,
 133 };
 134
 135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 136 {
 137         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 138         if (!dws->debugfs)
 139                 return -ENOMEM;
 140
 141         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 142                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 143         return 0;
 144 }
 145
 146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 147 {
 148         if (dws->debugfs)
 149                 debugfs_remove_recursive(dws->debugfs);
 150 }
 151
 152 #else
 153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 154 {
 155         return 0;
 156 }
 157
 158 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 159 {
 160 }
 161 #endif /* CONFIG_DEBUG_FS */
 162
 163 /* Return the max entries we can fill into tx fifo */
 164 static inline u32 tx_max(struct dw_spi *dws)
 165 {
 166         u32 tx_left, tx_room, rxtx_gap;
 167
 168         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 169         tx_room = dws->fifo_len - dw_readw(dws, txflr);
 170
 171         /*
 172          * Another concern is about the tx/rx mismatch, we
 173          * though to use (dws->fifo_len - rxflr - txflr) as
 174          * one maximum value for tx, but it doesn't cover the
 175          * data which is out of tx/rx fifo and inside the
 176          * shift registers. So a control from sw point of
 177          * view is taken.
 178          */
 179         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 180                         / dws->n_bytes;
 181
 182         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 183 }
 184
 185 /* Return the max entries we should read out of rx fifo */
 186 static inline u32 rx_max(struct dw_spi *dws)
 187 {
 188         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 189
 190         return min(rx_left, (u32)dw_readw(dws, rxflr));
 191 }
 192
 193
 194 static void wait_till_not_busy(struct dw_spi *dws)
 195 {
 196         unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
 197
 198         while (time_before(jiffies, end)) {
 199                 if (!(dw_readw(dws, sr) & SR_BUSY))
 200                         return;
 201                 cpu_relax();
 202         }
 203         dev_err(&dws->master->dev,
 204                 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
 205 }
 206
 207 static int dw_writer(struct dw_spi *dws)
 208 {
 209         u32 max = tx_max(dws);
 210         u16 txw = 0;
 211
 212         while (max--) {
 213                 /* Set the tx word if the transfer's original "tx" is not null */
 214                 if (dws->tx_end - dws->len) {
 215                         if (dws->n_bytes == 1)
 216                                 txw = *(u8 *)(dws->tx);
 217                         else
 218                                 txw = *(u16 *)(dws->tx);
 219                 }
 220                 dw_writew(dws, dr, txw);
 221                 dws->tx += dws->n_bytes;
 222         }
 223
 224         return 1;
 225 }
 226
 227 static int dw_reader(struct dw_spi *dws)
 228 {
 229         u32 max = rx_max(dws);
 230         u16 rxw;
 231
 232         while (max--) {
 233                 rxw = dw_readw(dws, dr);
 234                 /* Care rx only if the transfer's original "rx" is not null */
 235                 if (dws->rx_end - dws->len) {
 236                         if (dws->n_bytes == 1)
 237                                 *(u8 *)(dws->rx) = rxw;
 238                         else
 239                                 *(u16 *)(dws->rx) = rxw;
 240                 }
 241                 dws->rx += dws->n_bytes;
 242         }
 243
 244         return dws->rx == dws->rx_end;
 245 }
 246
 247 static void *next_transfer(struct dw_spi *dws)
 248 {
 249         struct spi_message *msg = dws->cur_msg;
 250         struct spi_transfer *trans = dws->cur_transfer;
 251
 252         /* Move to next transfer */
 253         if (trans->transfer_list.next != &msg->transfers) {
 254                 dws->cur_transfer =
 255                         list_entry(trans->transfer_list.next,
 256                                         struct spi_transfer,
 257                                         transfer_list);
 258                 return RUNNING_STATE;
 259         } else
 260                 return DONE_STATE;
 261 }
 262
 263 /*
 264  * Note: first step is the protocol driver prepares
 265  * a dma-capable memory, and this func just need translate
 266  * the virt addr to physical
 267  */
 268 static int map_dma_buffers(struct dw_spi *dws)
 269 {
 270         if (!dws->cur_msg->is_dma_mapped
 271                 || !dws->dma_inited
 272                 || !dws->cur_chip->enable_dma
 273                 || !dws->dma_ops)
 274                 return 0;
 275
 276         if (dws->cur_transfer->tx_dma)
 277                 dws->tx_dma = dws->cur_transfer->tx_dma;
 278
 279         if (dws->cur_transfer->rx_dma)
 280                 dws->rx_dma = dws->cur_transfer->rx_dma;
 281
 282         return 1;
 283 }
 284
 285 /* Caller already set message->status; dma and pio irqs are blocked */
 286 static void giveback(struct dw_spi *dws)
 287 {
 288         struct spi_transfer *last_transfer;
 289         unsigned long flags;
 290         struct spi_message *msg;
 291
 292         spin_lock_irqsave(&dws->lock, flags);
 293         msg = dws->cur_msg;
 294         dws->cur_msg = NULL;
 295         dws->cur_transfer = NULL;
 296         dws->prev_chip = dws->cur_chip;
 297         dws->cur_chip = NULL;
 298         dws->dma_mapped = 0;
 299         queue_work(dws->workqueue, &dws->pump_messages);
 300         spin_unlock_irqrestore(&dws->lock, flags);
 301
 302         last_transfer = list_entry(msg->transfers.prev,
 303                                         struct spi_transfer,
 304                                         transfer_list);
 305
 306         if (!last_transfer->cs_change && dws->cs_control)
 307                 dws->cs_control(MRST_SPI_DEASSERT);
 308
 309         msg->state = NULL;
 310         if (msg->complete)
 311                 msg->complete(msg->context);
 312 }
 313
 314 static void int_error_stop(struct dw_spi *dws, const char *msg)
 315 {
 316         /* Stop the hw */
 317         spi_enable_chip(dws, 0);
 318
 319         dev_err(&dws->master->dev, "%s\n", msg);
 320         dws->cur_msg->state = ERROR_STATE;
 321         tasklet_schedule(&dws->pump_transfers);
 322 }
 323
 324 void dw_spi_xfer_done(struct dw_spi *dws)
 325 {
 326         /* Update total byte transfered return count actual bytes read */
 327         dws->cur_msg->actual_length += dws->len;
 328
 329         /* Move to next transfer */
 330         dws->cur_msg->state = next_transfer(dws);
 331
 332         /* Handle end of message */
 333         if (dws->cur_msg->state == DONE_STATE) {
 334                 dws->cur_msg->status = 0;
 335                 giveback(dws);
 336         } else
 337                 tasklet_schedule(&dws->pump_transfers);
 338 }
 339 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 340
 341 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 342 {
 343         u16 irq_status, irq_mask = 0x3f;
 344         u32 int_level = dws->fifo_len / 2;
 345         u32 left;
 346
 347         irq_status = dw_readw(dws, isr) & irq_mask;
 348         /* Error handling */
 349         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 350                 dw_readw(dws, txoicr);
 351                 dw_readw(dws, rxoicr);
 352                 dw_readw(dws, rxuicr);
 353                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 354                 return IRQ_HANDLED;
 355         }
 356
 357         if (irq_status & SPI_INT_TXEI) {
 358                 spi_mask_intr(dws, SPI_INT_TXEI);
 359
 360                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 361                 left = (left > int_level) ? int_level : left;
 362
 363                 while (left--)
 364                         dw_writer(dws);
 365                 dw_reader(dws);
 366
 367                 /* Re-enable the IRQ if there is still data left to tx */
 368                 if (dws->tx_end > dws->tx)
 369                         spi_umask_intr(dws, SPI_INT_TXEI);
 370                 else
 371                         dw_spi_xfer_done(dws);
 372         }
 373
 374         return IRQ_HANDLED;
 375 }
 376
 377 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 378 {
 379         struct dw_spi *dws = dev_id;
 380         u16 irq_status, irq_mask = 0x3f;
 381
 382         irq_status = dw_readw(dws, isr) & irq_mask;
 383         if (!irq_status)
 384                 return IRQ_NONE;
 385
 386         if (!dws->cur_msg) {
 387                 spi_mask_intr(dws, SPI_INT_TXEI);
 388                 /* Never fail */
 389                 return IRQ_HANDLED;
 390         }
 391
 392         return dws->transfer_handler(dws);
 393 }
 394
 395 /* Must be called inside pump_transfers() */
 396 static void poll_transfer(struct dw_spi *dws)
 397 {
 398         do {
 399                 dw_writer(dws);
 400                 dw_reader(dws);
 401                 cpu_relax();
 402         } while (dws->rx_end > dws->rx);
 403
 404         dw_spi_xfer_done(dws);
 405 }
 406
 407 static void pump_transfers(unsigned long data)
 408 {
 409         struct dw_spi *dws = (struct dw_spi *)data;
 410         struct spi_message *message = NULL;
 411         struct spi_transfer *transfer = NULL;
 412         struct spi_transfer *previous = NULL;
 413         struct spi_device *spi = NULL;
 414         struct chip_data *chip = NULL;
 415         u8 bits = 0;
 416         u8 imask = 0;
 417         u8 cs_change = 0;
 418         u16 txint_level = 0;
 419         u16 clk_div = 0;
 420         u32 speed = 0;
 421         u32 cr0 = 0;
 422
 423         /* Get current state information */
 424         message = dws->cur_msg;
 425         transfer = dws->cur_transfer;
 426         chip = dws->cur_chip;
 427         spi = message->spi;
 428
 429         if (unlikely(!chip->clk_div))
 430                 chip->clk_div = dws->max_freq / chip->speed_hz;
 431
 432         if (message->state == ERROR_STATE) {
 433                 message->status = -EIO;
 434                 goto early_exit;
 435         }
 436
 437         /* Handle end of message */
 438         if (message->state == DONE_STATE) {
 439                 message->status = 0;
 440                 goto early_exit;
 441         }
 442
 443         /* Delay if requested at end of transfer*/
 444         if (message->state == RUNNING_STATE) {
 445                 previous = list_entry(transfer->transfer_list.prev,
 446                                         struct spi_transfer,
 447                                         transfer_list);
 448                 if (previous->delay_usecs)
 449                         udelay(previous->delay_usecs);
 450         }
 451
 452         dws->n_bytes = chip->n_bytes;
 453         dws->dma_width = chip->dma_width;
 454         dws->cs_control = chip->cs_control;
 455
 456         dws->rx_dma = transfer->rx_dma;
 457         dws->tx_dma = transfer->tx_dma;
 458         dws->tx = (void *)transfer->tx_buf;
 459         dws->tx_end = dws->tx + transfer->len;
 460         dws->rx = transfer->rx_buf;
 461         dws->rx_end = dws->rx + transfer->len;
 462         dws->cs_change = transfer->cs_change;
 463         dws->len = dws->cur_transfer->len;
 464         if (chip != dws->prev_chip)
 465                 cs_change = 1;
 466
 467         cr0 = chip->cr0;
 468
 469         /* Handle per transfer options for bpw and speed */
 470         if (transfer->speed_hz) {
 471                 speed = chip->speed_hz;
 472
 473                 if (transfer->speed_hz != speed) {
 474                         speed = transfer->speed_hz;
 475                         if (speed > dws->max_freq) {
 476                                 printk(KERN_ERR "MRST SPI0: unsupported"
 477                                         "freq: %dHz\n", speed);
 478                                 message->status = -EIO;
 479                                 goto early_exit;
 480                         }
 481
 482                         /* clk_div doesn't support odd number */
 483                         clk_div = dws->max_freq / speed;
 484                         clk_div = (clk_div + 1) & 0xfffe;
 485
 486                         chip->speed_hz = speed;
 487                         chip->clk_div = clk_div;
 488                 }
 489         }
 490         if (transfer->bits_per_word) {
 491                 bits = transfer->bits_per_word;
 492
 493                 switch (bits) {
 494                 case 8:
 495                         dws->n_bytes = 1;
 496                         dws->dma_width = 1;
 497                         break;
 498                 case 16:
 499                         dws->n_bytes = 2;
 500                         dws->dma_width = 2;
 501                         break;
 502                 default:
 503                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 504                                 "%db\n", bits);
 505                         message->status = -EIO;
 506                         goto early_exit;
 507                 }
 508
 509                 cr0 = (bits - 1)
 510                         | (chip->type << SPI_FRF_OFFSET)
 511                         | (spi->mode << SPI_MODE_OFFSET)
 512                         | (chip->tmode << SPI_TMOD_OFFSET);
 513         }
 514         message->state = RUNNING_STATE;
 515
 516         /*
 517          * Adjust transfer mode if necessary. Requires platform dependent
 518          * chipselect mechanism.
 519          */
 520         if (dws->cs_control) {
 521                 if (dws->rx && dws->tx)
 522                         chip->tmode = SPI_TMOD_TR;
 523                 else if (dws->rx)
 524                         chip->tmode = SPI_TMOD_RO;
 525                 else
 526                         chip->tmode = SPI_TMOD_TO;
 527
 528                 cr0 &= ~SPI_TMOD_MASK;
 529                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 530         }
 531
 532         /* Check if current transfer is a DMA transaction */
 533         dws->dma_mapped = map_dma_buffers(dws);
 534
 535         /*
 536          * Interrupt mode
 537          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 538          */
 539         if (!dws->dma_mapped && !chip->poll_mode) {
 540                 int templen = dws->len / dws->n_bytes;
 541                 txint_level = dws->fifo_len / 2;
 542                 txint_level = (templen > txint_level) ? txint_level : templen;
 543
 544                 imask |= SPI_INT_TXEI;
 545                 dws->transfer_handler = interrupt_transfer;
 546         }
 547
 548         /*
 549          * Reprogram registers only if
 550          *      1. chip select changes
 551          *      2. clk_div is changed
 552          *      3. control value changes
 553          */
 554         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 555                 spi_enable_chip(dws, 0);
 556
 557                 if (dw_readw(dws, ctrl0) != cr0)
 558                         dw_writew(dws, ctrl0, cr0);
 559
 560                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 561                 spi_chip_sel(dws, spi->chip_select);
 562
 563                 /* Set the interrupt mask, for poll mode just disable all int */
 564                 spi_mask_intr(dws, 0xff);
 565                 if (imask)
 566                         spi_umask_intr(dws, imask);
 567                 if (txint_level)
 568                         dw_writew(dws, txfltr, txint_level);
 569
 570                 spi_enable_chip(dws, 1);
 571                 if (cs_change)
 572                         dws->prev_chip = chip;
 573         }
 574
 575         if (dws->dma_mapped)
 576                 dws->dma_ops->dma_transfer(dws, cs_change);
 577
 578         if (chip->poll_mode)
 579                 poll_transfer(dws);
 580
 581         return;
 582
 583 early_exit:
 584         giveback(dws);
 585         return;
 586 }
 587
 588 static void pump_messages(struct work_struct *work)
 589 {
 590         struct dw_spi *dws =
 591                 container_of(work, struct dw_spi, pump_messages);
 592         unsigned long flags;
 593
 594         /* Lock queue and check for queue work */
 595         spin_lock_irqsave(&dws->lock, flags);
 596         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 597                 dws->busy = 0;
 598                 spin_unlock_irqrestore(&dws->lock, flags);
 599                 return;
 600         }
 601
 602         /* Make sure we are not already running a message */
 603         if (dws->cur_msg) {
 604                 spin_unlock_irqrestore(&dws->lock, flags);
 605                 return;
 606         }
 607
 608         /* Extract head of queue */
 609         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 610         list_del_init(&dws->cur_msg->queue);
 611
 612         /* Initial message state*/
 613         dws->cur_msg->state = START_STATE;
 614         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 615                                                 struct spi_transfer,
 616                                                 transfer_list);
 617         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 618
 619         /* Mark as busy and launch transfers */
 620         tasklet_schedule(&dws->pump_transfers);
 621
 622         dws->busy = 1;
 623         spin_unlock_irqrestore(&dws->lock, flags);
 624 }
 625
 626 /* spi_device use this to queue in their spi_msg */
 627 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 628 {
 629         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 630         unsigned long flags;
 631
 632         spin_lock_irqsave(&dws->lock, flags);
 633
 634         if (dws->run == QUEUE_STOPPED) {
 635                 spin_unlock_irqrestore(&dws->lock, flags);
 636                 return -ESHUTDOWN;
 637         }
 638
 639         msg->actual_length = 0;
 640         msg->status = -EINPROGRESS;
 641         msg->state = START_STATE;
 642
 643         list_add_tail(&msg->queue, &dws->queue);
 644
 645         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 646
 647                 if (dws->cur_transfer || dws->cur_msg)
 648                         queue_work(dws->workqueue,
 649                                         &dws->pump_messages);
 650                 else {
 651                         /* If no other data transaction in air, just go */
 652                         spin_unlock_irqrestore(&dws->lock, flags);
 653                         pump_messages(&dws->pump_messages);
 654                         return 0;
 655                 }
 656         }
 657
 658         spin_unlock_irqrestore(&dws->lock, flags);
 659         return 0;
 660 }
 661
 662 /* This may be called twice for each spi dev */
 663 static int dw_spi_setup(struct spi_device *spi)
 664 {
 665         struct dw_spi_chip *chip_info = NULL;
 666         struct chip_data *chip;
 667
 668         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 669                 return -EINVAL;
 670
 671         /* Only alloc on first setup */
 672         chip = spi_get_ctldata(spi);
 673         if (!chip) {
 674                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 675                 if (!chip)
 676                         return -ENOMEM;
 677         }
 678
 679         /*
 680          * Protocol drivers may change the chip settings, so...
 681          * if chip_info exists, use it
 682          */
 683         chip_info = spi->controller_data;
 684
 685         /* chip_info doesn't always exist */
 686         if (chip_info) {
 687                 if (chip_info->cs_control)
 688                         chip->cs_control = chip_info->cs_control;
 689
 690                 chip->poll_mode = chip_info->poll_mode;
 691                 chip->type = chip_info->type;
 692
 693                 chip->rx_threshold = 0;
 694                 chip->tx_threshold = 0;
 695
 696                 chip->enable_dma = chip_info->enable_dma;
 697         }
 698
 699         if (spi->bits_per_word <= 8) {
 700                 chip->n_bytes = 1;
 701                 chip->dma_width = 1;
 702         } else if (spi->bits_per_word <= 16) {
 703                 chip->n_bytes = 2;
 704                 chip->dma_width = 2;
 705         } else {
 706                 /* Never take >16b case for MRST SPIC */
 707                 dev_err(&spi->dev, "invalid wordsize\n");
 708                 return -EINVAL;
 709         }
 710         chip->bits_per_word = spi->bits_per_word;
 711
 712         if (!spi->max_speed_hz) {
 713                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 714                 return -EINVAL;
 715         }
 716         chip->speed_hz = spi->max_speed_hz;
 717
 718         chip->tmode = 0; /* Tx & Rx */
 719         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 720         chip->cr0 = (chip->bits_per_word - 1)
 721                         | (chip->type << SPI_FRF_OFFSET)
 722                         | (spi->mode  << SPI_MODE_OFFSET)
 723                         | (chip->tmode << SPI_TMOD_OFFSET);
 724
 725         spi_set_ctldata(spi, chip);
 726         return 0;
 727 }
 728
 729 static void dw_spi_cleanup(struct spi_device *spi)
 730 {
 731         struct chip_data *chip = spi_get_ctldata(spi);
 732         kfree(chip);
 733 }
 734
 735 static int __devinit init_queue(struct dw_spi *dws)
 736 {
 737         INIT_LIST_HEAD(&dws->queue);
 738         spin_lock_init(&dws->lock);
 739
 740         dws->run = QUEUE_STOPPED;
 741         dws->busy = 0;
 742
 743         tasklet_init(&dws->pump_transfers,
 744                         pump_transfers, (unsigned long)dws);
 745
 746         INIT_WORK(&dws->pump_messages, pump_messages);
 747         dws->workqueue = create_singlethread_workqueue(
 748                                         dev_name(dws->master->dev.parent));
 749         if (dws->workqueue == NULL)
 750                 return -EBUSY;
 751
 752         return 0;
 753 }
 754
 755 static int start_queue(struct dw_spi *dws)
 756 {
 757         unsigned long flags;
 758
 759         spin_lock_irqsave(&dws->lock, flags);
 760
 761         if (dws->run == QUEUE_RUNNING || dws->busy) {
 762                 spin_unlock_irqrestore(&dws->lock, flags);
 763                 return -EBUSY;
 764         }
 765
 766         dws->run = QUEUE_RUNNING;
 767         dws->cur_msg = NULL;
 768         dws->cur_transfer = NULL;
 769         dws->cur_chip = NULL;
 770         dws->prev_chip = NULL;
 771         spin_unlock_irqrestore(&dws->lock, flags);
 772
 773         queue_work(dws->workqueue, &dws->pump_messages);
 774
 775         return 0;
 776 }
 777
 778 static int stop_queue(struct dw_spi *dws)
 779 {
 780         unsigned long flags;
 781         unsigned limit = 50;
 782         int status = 0;
 783
 784         spin_lock_irqsave(&dws->lock, flags);
 785         dws->run = QUEUE_STOPPED;
 786         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 787                 spin_unlock_irqrestore(&dws->lock, flags);
 788                 msleep(10);
 789                 spin_lock_irqsave(&dws->lock, flags);
 790         }
 791
 792         if (!list_empty(&dws->queue) || dws->busy)
 793                 status = -EBUSY;
 794         spin_unlock_irqrestore(&dws->lock, flags);
 795
 796         return status;
 797 }
 798
 799 static int destroy_queue(struct dw_spi *dws)
 800 {
 801         int status;
 802
 803         status = stop_queue(dws);
 804         if (status != 0)
 805                 return status;
 806         destroy_workqueue(dws->workqueue);
 807         return 0;
 808 }
 809
 810 /* Restart the controller, disable all interrupts, clean rx fifo */
 811 static void spi_hw_init(struct dw_spi *dws)
 812 {
 813         spi_enable_chip(dws, 0);
 814         spi_mask_intr(dws, 0xff);
 815         spi_enable_chip(dws, 1);
 816
 817         /*
 818          * Try to detect the FIFO depth if not set by interface driver,
 819          * the depth could be from 2 to 256 from HW spec
 820          */
 821         if (!dws->fifo_len) {
 822                 u32 fifo;
 823                 for (fifo = 2; fifo <= 257; fifo++) {
 824                         dw_writew(dws, txfltr, fifo);
 825                         if (fifo != dw_readw(dws, txfltr))
 826                                 break;
 827                 }
 828
 829                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 830                 dw_writew(dws, txfltr, 0);
 831         }
 832 }
 833
 834 int __devinit dw_spi_add_host(struct dw_spi *dws)
 835 {
 836         struct spi_master *master;
 837         int ret;
 838
 839         BUG_ON(dws == NULL);
 840
 841         master = spi_alloc_master(dws->parent_dev, 0);
 842         if (!master) {
 843                 ret = -ENOMEM;
 844                 goto exit;
 845         }
 846
 847         dws->master = master;
 848         dws->type = SSI_MOTO_SPI;
 849         dws->prev_chip = NULL;
 850         dws->dma_inited = 0;
 851         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 852
 853         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 854                         "dw_spi", dws);
 855         if (ret < 0) {
 856                 dev_err(&master->dev, "can not get IRQ\n");
 857                 goto err_free_master;
 858         }
 859
 860         master->mode_bits = SPI_CPOL | SPI_CPHA;
 861         master->bus_num = dws->bus_num;
 862         master->num_chipselect = dws->num_cs;
 863         master->cleanup = dw_spi_cleanup;
 864         master->setup = dw_spi_setup;
 865         master->transfer = dw_spi_transfer;
 866
 867         /* Basic HW init */
 868         spi_hw_init(dws);
 869
 870         if (dws->dma_ops && dws->dma_ops->dma_init) {
 871                 ret = dws->dma_ops->dma_init(dws);
 872                 if (ret) {
 873                         dev_warn(&master->dev, "DMA init failed\n");
 874                         dws->dma_inited = 0;
 875                 }
 876         }
 877
 878         /* Initial and start queue */
 879         ret = init_queue(dws);
 880         if (ret) {
 881                 dev_err(&master->dev, "problem initializing queue\n");
 882                 goto err_diable_hw;
 883         }
 884         ret = start_queue(dws);
 885         if (ret) {
 886                 dev_err(&master->dev, "problem starting queue\n");
 887                 goto err_diable_hw;
 888         }
 889
 890         spi_master_set_devdata(master, dws);
 891         ret = spi_register_master(master);
 892         if (ret) {
 893                 dev_err(&master->dev, "problem registering spi master\n");
 894                 goto err_queue_alloc;
 895         }
 896
 897         mrst_spi_debugfs_init(dws);
 898         return 0;
 899
 900 err_queue_alloc:
 901         destroy_queue(dws);
 902         if (dws->dma_ops && dws->dma_ops->dma_exit)
 903                 dws->dma_ops->dma_exit(dws);
 904 err_diable_hw:
 905         spi_enable_chip(dws, 0);
 906         free_irq(dws->irq, dws);
 907 err_free_master:
 908         spi_master_put(master);
 909 exit:
 910         return ret;
 911 }
 912 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 913
 914 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 915 {
 916         int status = 0;
 917
 918         if (!dws)
 919                 return;
 920         mrst_spi_debugfs_remove(dws);
 921
 922         /* Remove the queue */
 923         status = destroy_queue(dws);
 924         if (status != 0)
 925                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 926                         "complete, message memory not freed\n");
 927
 928         if (dws->dma_ops && dws->dma_ops->dma_exit)
 929                 dws->dma_ops->dma_exit(dws);
 930         spi_enable_chip(dws, 0);
 931         /* Disable clk */
 932         spi_set_clk(dws, 0);
 933         free_irq(dws->irq, dws);
 934
 935         /* Disconnect from the SPI framework */
 936         spi_unregister_master(dws->master);
 937 }
 938 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 939
 940 int dw_spi_suspend_host(struct dw_spi *dws)
 941 {
 942         int ret = 0;
 943
 944         ret = stop_queue(dws);
 945         if (ret)
 946                 return ret;
 947         spi_enable_chip(dws, 0);
 948         spi_set_clk(dws, 0);
 949         return ret;
 950 }
 951 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 952
 953 int dw_spi_resume_host(struct dw_spi *dws)
 954 {
 955         int ret;
 956
 957         spi_hw_init(dws);
 958         ret = start_queue(dws);
 959         if (ret)
 960                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 961         return ret;
 962 }
 963 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 964
 965 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 966 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 967 MODULE_LICENSE("GPL v2");