drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include "dw_spi.h"
  28
  29 #ifdef CONFIG_DEBUG_FS
  30 #include <linux/debugfs.h>
  31 #endif
  32
  33 #define START_STATE     ((void *)0)
  34 #define RUNNING_STATE   ((void *)1)
  35 #define DONE_STATE      ((void *)2)
  36 #define ERROR_STATE     ((void *)-1)
  37
  38 #define QUEUE_RUNNING   0
  39 #define QUEUE_STOPPED   1
  40
  41 #define MRST_SPI_DEASSERT       0
  42 #define MRST_SPI_ASSERT         1
  43
  44 /* Slave spi_dev related */
  45 struct chip_data {
  46         u16 cr0;
  47         u8 cs;                  /* chip select pin */
  48         u8 n_bytes;             /* current is a 1/2/4 byte op */
  49         u8 tmode;               /* TR/TO/RO/EEPROM */
  50         u8 type;                /* SPI/SSP/MicroWire */
  51
  52         u8 poll_mode;           /* 1 means use poll mode */
  53
  54         u32 dma_width;
  55         u32 rx_threshold;
  56         u32 tx_threshold;
  57         u8 enable_dma;
  58         u8 bits_per_word;
  59         u16 clk_div;            /* baud rate divider */
  60         u32 speed_hz;           /* baud rate */
  61         void (*cs_control)(u32 command);
  62 };
  63
  64 #ifdef CONFIG_DEBUG_FS
  65 static int spi_show_regs_open(struct inode *inode, struct file *file)
  66 {
  67         file->private_data = inode->i_private;
  68         return 0;
  69 }
  70
  71 #define SPI_REGS_BUFSIZE        1024
  72 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  73                                 size_t count, loff_t *ppos)
  74 {
  75         struct dw_spi *dws;
  76         char *buf;
  77         u32 len = 0;
  78         ssize_t ret;
  79
  80         dws = file->private_data;
  81
  82         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  83         if (!buf)
  84                 return 0;
  85
  86         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87                         "MRST SPI0 registers:\n");
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "=================================\n");
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "=================================\n");
 122
 123         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 124         kfree(buf);
 125         return ret;
 126 }
 127
 128 static const struct file_operations mrst_spi_regs_ops = {
 129         .owner          = THIS_MODULE,
 130         .open           = spi_show_regs_open,
 131         .read           = spi_show_regs,
 132         .llseek         = default_llseek,
 133 };
 134
 135 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 136 {
 137         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 138         if (!dws->debugfs)
 139                 return -ENOMEM;
 140
 141         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 142                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 143         return 0;
 144 }
 145
 146 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 147 {
 148         if (dws->debugfs)
 149                 debugfs_remove_recursive(dws->debugfs);
 150 }
 151
 152 #else
 153 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 154 {
 155         return 0;
 156 }
 157
 158 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 159 {
 160 }
 161 #endif /* CONFIG_DEBUG_FS */
 162
 163 static void wait_till_not_busy(struct dw_spi *dws)
 164 {
 165         unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
 166
 167         while (time_before(jiffies, end)) {
 168                 if (!(dw_readw(dws, sr) & SR_BUSY))
 169                         return;
 170                 cpu_relax();
 171         }
 172         dev_err(&dws->master->dev,
 173                 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
 174 }
 175
 176 static void flush(struct dw_spi *dws)
 177 {
 178         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) {
 179                 dw_readw(dws, dr);
 180                 cpu_relax();
 181         }
 182
 183         wait_till_not_busy(dws);
 184 }
 185
 186
 187 static int dw_writer(struct dw_spi *dws)
 188 {
 189         u16 txw = 0;
 190
 191         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 192                 || (dws->tx == dws->tx_end))
 193                 return 0;
 194
 195         /* Set the tx word if the transfer's original "tx" is not null */
 196         if (dws->tx_end - dws->len) {
 197                 if (dws->n_bytes == 1)
 198                         txw = *(u8 *)(dws->tx);
 199                 else
 200                         txw = *(u16 *)(dws->tx);
 201         }
 202
 203         dw_writew(dws, dr, txw);
 204         dws->tx += dws->n_bytes;
 205
 206         wait_till_not_busy(dws);
 207         return 1;
 208 }
 209
 210 static int dw_reader(struct dw_spi *dws)
 211 {
 212         u16 rxw;
 213
 214         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 215                 && (dws->rx < dws->rx_end)) {
 216                 rxw = dw_readw(dws, dr);
 217                 /* Care rx only if the transfer's original "rx" is not null */
 218                 if (dws->rx_end - dws->len) {
 219                         if (dws->n_bytes == 1)
 220                                 *(u8 *)(dws->rx) = rxw;
 221                         else
 222                                 *(u16 *)(dws->rx) = rxw;
 223                 }
 224                 dws->rx += dws->n_bytes;
 225         }
 226
 227         wait_till_not_busy(dws);
 228         return dws->rx == dws->rx_end;
 229 }
 230
 231 static void *next_transfer(struct dw_spi *dws)
 232 {
 233         struct spi_message *msg = dws->cur_msg;
 234         struct spi_transfer *trans = dws->cur_transfer;
 235
 236         /* Move to next transfer */
 237         if (trans->transfer_list.next != &msg->transfers) {
 238                 dws->cur_transfer =
 239                         list_entry(trans->transfer_list.next,
 240                                         struct spi_transfer,
 241                                         transfer_list);
 242                 return RUNNING_STATE;
 243         } else
 244                 return DONE_STATE;
 245 }
 246
 247 /*
 248  * Note: first step is the protocol driver prepares
 249  * a dma-capable memory, and this func just need translate
 250  * the virt addr to physical
 251  */
 252 static int map_dma_buffers(struct dw_spi *dws)
 253 {
 254         if (!dws->cur_msg->is_dma_mapped
 255                 || !dws->dma_inited
 256                 || !dws->cur_chip->enable_dma
 257                 || !dws->dma_ops)
 258                 return 0;
 259
 260         if (dws->cur_transfer->tx_dma)
 261                 dws->tx_dma = dws->cur_transfer->tx_dma;
 262
 263         if (dws->cur_transfer->rx_dma)
 264                 dws->rx_dma = dws->cur_transfer->rx_dma;
 265
 266         return 1;
 267 }
 268
 269 /* Caller already set message->status; dma and pio irqs are blocked */
 270 static void giveback(struct dw_spi *dws)
 271 {
 272         struct spi_transfer *last_transfer;
 273         unsigned long flags;
 274         struct spi_message *msg;
 275
 276         spin_lock_irqsave(&dws->lock, flags);
 277         msg = dws->cur_msg;
 278         dws->cur_msg = NULL;
 279         dws->cur_transfer = NULL;
 280         dws->prev_chip = dws->cur_chip;
 281         dws->cur_chip = NULL;
 282         dws->dma_mapped = 0;
 283         queue_work(dws->workqueue, &dws->pump_messages);
 284         spin_unlock_irqrestore(&dws->lock, flags);
 285
 286         last_transfer = list_entry(msg->transfers.prev,
 287                                         struct spi_transfer,
 288                                         transfer_list);
 289
 290         if (!last_transfer->cs_change && dws->cs_control)
 291                 dws->cs_control(MRST_SPI_DEASSERT);
 292
 293         msg->state = NULL;
 294         if (msg->complete)
 295                 msg->complete(msg->context);
 296 }
 297
 298 static void int_error_stop(struct dw_spi *dws, const char *msg)
 299 {
 300         /* Stop and reset hw */
 301         flush(dws);
 302         spi_enable_chip(dws, 0);
 303
 304         dev_err(&dws->master->dev, "%s\n", msg);
 305         dws->cur_msg->state = ERROR_STATE;
 306         tasklet_schedule(&dws->pump_transfers);
 307 }
 308
 309 void dw_spi_xfer_done(struct dw_spi *dws)
 310 {
 311         /* Update total byte transfered return count actual bytes read */
 312         dws->cur_msg->actual_length += dws->len;
 313
 314         /* Move to next transfer */
 315         dws->cur_msg->state = next_transfer(dws);
 316
 317         /* Handle end of message */
 318         if (dws->cur_msg->state == DONE_STATE) {
 319                 dws->cur_msg->status = 0;
 320                 giveback(dws);
 321         } else
 322                 tasklet_schedule(&dws->pump_transfers);
 323 }
 324 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 325
 326 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 327 {
 328         u16 irq_status, irq_mask = 0x3f;
 329         u32 int_level = dws->fifo_len / 2;
 330         u32 left;
 331
 332         irq_status = dw_readw(dws, isr) & irq_mask;
 333         /* Error handling */
 334         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 335                 dw_readw(dws, txoicr);
 336                 dw_readw(dws, rxoicr);
 337                 dw_readw(dws, rxuicr);
 338                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 339                 return IRQ_HANDLED;
 340         }
 341
 342         if (irq_status & SPI_INT_TXEI) {
 343                 spi_mask_intr(dws, SPI_INT_TXEI);
 344
 345                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 346                 left = (left > int_level) ? int_level : left;
 347
 348                 while (left--)
 349                         dw_writer(dws);
 350                 dw_reader(dws);
 351
 352                 /* Re-enable the IRQ if there is still data left to tx */
 353                 if (dws->tx_end > dws->tx)
 354                         spi_umask_intr(dws, SPI_INT_TXEI);
 355                 else
 356                         dw_spi_xfer_done(dws);
 357         }
 358
 359         return IRQ_HANDLED;
 360 }
 361
 362 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 363 {
 364         struct dw_spi *dws = dev_id;
 365         u16 irq_status, irq_mask = 0x3f;
 366
 367         irq_status = dw_readw(dws, isr) & irq_mask;
 368         if (!irq_status)
 369                 return IRQ_NONE;
 370
 371         if (!dws->cur_msg) {
 372                 spi_mask_intr(dws, SPI_INT_TXEI);
 373                 /* Never fail */
 374                 return IRQ_HANDLED;
 375         }
 376
 377         return dws->transfer_handler(dws);
 378 }
 379
 380 /* Must be called inside pump_transfers() */
 381 static void poll_transfer(struct dw_spi *dws)
 382 {
 383         while (dw_writer(dws))
 384                 dw_reader(dws);
 385         /*
 386          * There is a possibility that the last word of a transaction
 387          * will be lost if data is not ready. Re-read to solve this issue.
 388          */
 389         dw_reader(dws);
 390
 391         dw_spi_xfer_done(dws);
 392 }
 393
 394 static void pump_transfers(unsigned long data)
 395 {
 396         struct dw_spi *dws = (struct dw_spi *)data;
 397         struct spi_message *message = NULL;
 398         struct spi_transfer *transfer = NULL;
 399         struct spi_transfer *previous = NULL;
 400         struct spi_device *spi = NULL;
 401         struct chip_data *chip = NULL;
 402         u8 bits = 0;
 403         u8 imask = 0;
 404         u8 cs_change = 0;
 405         u16 txint_level = 0;
 406         u16 clk_div = 0;
 407         u32 speed = 0;
 408         u32 cr0 = 0;
 409
 410         /* Get current state information */
 411         message = dws->cur_msg;
 412         transfer = dws->cur_transfer;
 413         chip = dws->cur_chip;
 414         spi = message->spi;
 415
 416         if (unlikely(!chip->clk_div))
 417                 chip->clk_div = dws->max_freq / chip->speed_hz;
 418
 419         if (message->state == ERROR_STATE) {
 420                 message->status = -EIO;
 421                 goto early_exit;
 422         }
 423
 424         /* Handle end of message */
 425         if (message->state == DONE_STATE) {
 426                 message->status = 0;
 427                 goto early_exit;
 428         }
 429
 430         /* Delay if requested at end of transfer*/
 431         if (message->state == RUNNING_STATE) {
 432                 previous = list_entry(transfer->transfer_list.prev,
 433                                         struct spi_transfer,
 434                                         transfer_list);
 435                 if (previous->delay_usecs)
 436                         udelay(previous->delay_usecs);
 437         }
 438
 439         dws->n_bytes = chip->n_bytes;
 440         dws->dma_width = chip->dma_width;
 441         dws->cs_control = chip->cs_control;
 442
 443         dws->rx_dma = transfer->rx_dma;
 444         dws->tx_dma = transfer->tx_dma;
 445         dws->tx = (void *)transfer->tx_buf;
 446         dws->tx_end = dws->tx + transfer->len;
 447         dws->rx = transfer->rx_buf;
 448         dws->rx_end = dws->rx + transfer->len;
 449         dws->cs_change = transfer->cs_change;
 450         dws->len = dws->cur_transfer->len;
 451         if (chip != dws->prev_chip)
 452                 cs_change = 1;
 453
 454         cr0 = chip->cr0;
 455
 456         /* Handle per transfer options for bpw and speed */
 457         if (transfer->speed_hz) {
 458                 speed = chip->speed_hz;
 459
 460                 if (transfer->speed_hz != speed) {
 461                         speed = transfer->speed_hz;
 462                         if (speed > dws->max_freq) {
 463                                 printk(KERN_ERR "MRST SPI0: unsupported"
 464                                         "freq: %dHz\n", speed);
 465                                 message->status = -EIO;
 466                                 goto early_exit;
 467                         }
 468
 469                         /* clk_div doesn't support odd number */
 470                         clk_div = dws->max_freq / speed;
 471                         clk_div = (clk_div + 1) & 0xfffe;
 472
 473                         chip->speed_hz = speed;
 474                         chip->clk_div = clk_div;
 475                 }
 476         }
 477         if (transfer->bits_per_word) {
 478                 bits = transfer->bits_per_word;
 479
 480                 switch (bits) {
 481                 case 8:
 482                         dws->n_bytes = 1;
 483                         dws->dma_width = 1;
 484                         break;
 485                 case 16:
 486                         dws->n_bytes = 2;
 487                         dws->dma_width = 2;
 488                         break;
 489                 default:
 490                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 491                                 "%db\n", bits);
 492                         message->status = -EIO;
 493                         goto early_exit;
 494                 }
 495
 496                 cr0 = (bits - 1)
 497                         | (chip->type << SPI_FRF_OFFSET)
 498                         | (spi->mode << SPI_MODE_OFFSET)
 499                         | (chip->tmode << SPI_TMOD_OFFSET);
 500         }
 501         message->state = RUNNING_STATE;
 502
 503         /*
 504          * Adjust transfer mode if necessary. Requires platform dependent
 505          * chipselect mechanism.
 506          */
 507         if (dws->cs_control) {
 508                 if (dws->rx && dws->tx)
 509                         chip->tmode = SPI_TMOD_TR;
 510                 else if (dws->rx)
 511                         chip->tmode = SPI_TMOD_RO;
 512                 else
 513                         chip->tmode = SPI_TMOD_TO;
 514
 515                 cr0 &= ~SPI_TMOD_MASK;
 516                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 517         }
 518
 519         /* Check if current transfer is a DMA transaction */
 520         dws->dma_mapped = map_dma_buffers(dws);
 521
 522         /*
 523          * Interrupt mode
 524          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 525          */
 526         if (!dws->dma_mapped && !chip->poll_mode) {
 527                 int templen = dws->len / dws->n_bytes;
 528                 txint_level = dws->fifo_len / 2;
 529                 txint_level = (templen > txint_level) ? txint_level : templen;
 530
 531                 imask |= SPI_INT_TXEI;
 532                 dws->transfer_handler = interrupt_transfer;
 533         }
 534
 535         /*
 536          * Reprogram registers only if
 537          *      1. chip select changes
 538          *      2. clk_div is changed
 539          *      3. control value changes
 540          */
 541         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 542                 spi_enable_chip(dws, 0);
 543
 544                 if (dw_readw(dws, ctrl0) != cr0)
 545                         dw_writew(dws, ctrl0, cr0);
 546
 547                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 548                 spi_chip_sel(dws, spi->chip_select);
 549
 550                 /* Set the interrupt mask, for poll mode just disable all int */
 551                 spi_mask_intr(dws, 0xff);
 552                 if (imask)
 553                         spi_umask_intr(dws, imask);
 554                 if (txint_level)
 555                         dw_writew(dws, txfltr, txint_level);
 556
 557                 spi_enable_chip(dws, 1);
 558                 if (cs_change)
 559                         dws->prev_chip = chip;
 560         }
 561
 562         if (dws->dma_mapped)
 563                 dws->dma_ops->dma_transfer(dws, cs_change);
 564
 565         if (chip->poll_mode)
 566                 poll_transfer(dws);
 567
 568         return;
 569
 570 early_exit:
 571         giveback(dws);
 572         return;
 573 }
 574
 575 static void pump_messages(struct work_struct *work)
 576 {
 577         struct dw_spi *dws =
 578                 container_of(work, struct dw_spi, pump_messages);
 579         unsigned long flags;
 580
 581         /* Lock queue and check for queue work */
 582         spin_lock_irqsave(&dws->lock, flags);
 583         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 584                 dws->busy = 0;
 585                 spin_unlock_irqrestore(&dws->lock, flags);
 586                 return;
 587         }
 588
 589         /* Make sure we are not already running a message */
 590         if (dws->cur_msg) {
 591                 spin_unlock_irqrestore(&dws->lock, flags);
 592                 return;
 593         }
 594
 595         /* Extract head of queue */
 596         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 597         list_del_init(&dws->cur_msg->queue);
 598
 599         /* Initial message state*/
 600         dws->cur_msg->state = START_STATE;
 601         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 602                                                 struct spi_transfer,
 603                                                 transfer_list);
 604         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 605
 606         /* Mark as busy and launch transfers */
 607         tasklet_schedule(&dws->pump_transfers);
 608
 609         dws->busy = 1;
 610         spin_unlock_irqrestore(&dws->lock, flags);
 611 }
 612
 613 /* spi_device use this to queue in their spi_msg */
 614 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 615 {
 616         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 617         unsigned long flags;
 618
 619         spin_lock_irqsave(&dws->lock, flags);
 620
 621         if (dws->run == QUEUE_STOPPED) {
 622                 spin_unlock_irqrestore(&dws->lock, flags);
 623                 return -ESHUTDOWN;
 624         }
 625
 626         msg->actual_length = 0;
 627         msg->status = -EINPROGRESS;
 628         msg->state = START_STATE;
 629
 630         list_add_tail(&msg->queue, &dws->queue);
 631
 632         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 633
 634                 if (dws->cur_transfer || dws->cur_msg)
 635                         queue_work(dws->workqueue,
 636                                         &dws->pump_messages);
 637                 else {
 638                         /* If no other data transaction in air, just go */
 639                         spin_unlock_irqrestore(&dws->lock, flags);
 640                         pump_messages(&dws->pump_messages);
 641                         return 0;
 642                 }
 643         }
 644
 645         spin_unlock_irqrestore(&dws->lock, flags);
 646         return 0;
 647 }
 648
 649 /* This may be called twice for each spi dev */
 650 static int dw_spi_setup(struct spi_device *spi)
 651 {
 652         struct dw_spi_chip *chip_info = NULL;
 653         struct chip_data *chip;
 654
 655         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 656                 return -EINVAL;
 657
 658         /* Only alloc on first setup */
 659         chip = spi_get_ctldata(spi);
 660         if (!chip) {
 661                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 662                 if (!chip)
 663                         return -ENOMEM;
 664         }
 665
 666         /*
 667          * Protocol drivers may change the chip settings, so...
 668          * if chip_info exists, use it
 669          */
 670         chip_info = spi->controller_data;
 671
 672         /* chip_info doesn't always exist */
 673         if (chip_info) {
 674                 if (chip_info->cs_control)
 675                         chip->cs_control = chip_info->cs_control;
 676
 677                 chip->poll_mode = chip_info->poll_mode;
 678                 chip->type = chip_info->type;
 679
 680                 chip->rx_threshold = 0;
 681                 chip->tx_threshold = 0;
 682
 683                 chip->enable_dma = chip_info->enable_dma;
 684         }
 685
 686         if (spi->bits_per_word <= 8) {
 687                 chip->n_bytes = 1;
 688                 chip->dma_width = 1;
 689         } else if (spi->bits_per_word <= 16) {
 690                 chip->n_bytes = 2;
 691                 chip->dma_width = 2;
 692         } else {
 693                 /* Never take >16b case for MRST SPIC */
 694                 dev_err(&spi->dev, "invalid wordsize\n");
 695                 return -EINVAL;
 696         }
 697         chip->bits_per_word = spi->bits_per_word;
 698
 699         if (!spi->max_speed_hz) {
 700                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 701                 return -EINVAL;
 702         }
 703         chip->speed_hz = spi->max_speed_hz;
 704
 705         chip->tmode = 0; /* Tx & Rx */
 706         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 707         chip->cr0 = (chip->bits_per_word - 1)
 708                         | (chip->type << SPI_FRF_OFFSET)
 709                         | (spi->mode  << SPI_MODE_OFFSET)
 710                         | (chip->tmode << SPI_TMOD_OFFSET);
 711
 712         spi_set_ctldata(spi, chip);
 713         return 0;
 714 }
 715
 716 static void dw_spi_cleanup(struct spi_device *spi)
 717 {
 718         struct chip_data *chip = spi_get_ctldata(spi);
 719         kfree(chip);
 720 }
 721
 722 static int __devinit init_queue(struct dw_spi *dws)
 723 {
 724         INIT_LIST_HEAD(&dws->queue);
 725         spin_lock_init(&dws->lock);
 726
 727         dws->run = QUEUE_STOPPED;
 728         dws->busy = 0;
 729
 730         tasklet_init(&dws->pump_transfers,
 731                         pump_transfers, (unsigned long)dws);
 732
 733         INIT_WORK(&dws->pump_messages, pump_messages);
 734         dws->workqueue = create_singlethread_workqueue(
 735                                         dev_name(dws->master->dev.parent));
 736         if (dws->workqueue == NULL)
 737                 return -EBUSY;
 738
 739         return 0;
 740 }
 741
 742 static int start_queue(struct dw_spi *dws)
 743 {
 744         unsigned long flags;
 745
 746         spin_lock_irqsave(&dws->lock, flags);
 747
 748         if (dws->run == QUEUE_RUNNING || dws->busy) {
 749                 spin_unlock_irqrestore(&dws->lock, flags);
 750                 return -EBUSY;
 751         }
 752
 753         dws->run = QUEUE_RUNNING;
 754         dws->cur_msg = NULL;
 755         dws->cur_transfer = NULL;
 756         dws->cur_chip = NULL;
 757         dws->prev_chip = NULL;
 758         spin_unlock_irqrestore(&dws->lock, flags);
 759
 760         queue_work(dws->workqueue, &dws->pump_messages);
 761
 762         return 0;
 763 }
 764
 765 static int stop_queue(struct dw_spi *dws)
 766 {
 767         unsigned long flags;
 768         unsigned limit = 50;
 769         int status = 0;
 770
 771         spin_lock_irqsave(&dws->lock, flags);
 772         dws->run = QUEUE_STOPPED;
 773         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 774                 spin_unlock_irqrestore(&dws->lock, flags);
 775                 msleep(10);
 776                 spin_lock_irqsave(&dws->lock, flags);
 777         }
 778
 779         if (!list_empty(&dws->queue) || dws->busy)
 780                 status = -EBUSY;
 781         spin_unlock_irqrestore(&dws->lock, flags);
 782
 783         return status;
 784 }
 785
 786 static int destroy_queue(struct dw_spi *dws)
 787 {
 788         int status;
 789
 790         status = stop_queue(dws);
 791         if (status != 0)
 792                 return status;
 793         destroy_workqueue(dws->workqueue);
 794         return 0;
 795 }
 796
 797 /* Restart the controller, disable all interrupts, clean rx fifo */
 798 static void spi_hw_init(struct dw_spi *dws)
 799 {
 800         spi_enable_chip(dws, 0);
 801         spi_mask_intr(dws, 0xff);
 802         spi_enable_chip(dws, 1);
 803         flush(dws);
 804
 805         /*
 806          * Try to detect the FIFO depth if not set by interface driver,
 807          * the depth could be from 2 to 256 from HW spec
 808          */
 809         if (!dws->fifo_len) {
 810                 u32 fifo;
 811                 for (fifo = 2; fifo <= 257; fifo++) {
 812                         dw_writew(dws, txfltr, fifo);
 813                         if (fifo != dw_readw(dws, txfltr))
 814                                 break;
 815                 }
 816
 817                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 818                 dw_writew(dws, txfltr, 0);
 819         }
 820 }
 821
 822 int __devinit dw_spi_add_host(struct dw_spi *dws)
 823 {
 824         struct spi_master *master;
 825         int ret;
 826
 827         BUG_ON(dws == NULL);
 828
 829         master = spi_alloc_master(dws->parent_dev, 0);
 830         if (!master) {
 831                 ret = -ENOMEM;
 832                 goto exit;
 833         }
 834
 835         dws->master = master;
 836         dws->type = SSI_MOTO_SPI;
 837         dws->prev_chip = NULL;
 838         dws->dma_inited = 0;
 839         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 840
 841         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 842                         "dw_spi", dws);
 843         if (ret < 0) {
 844                 dev_err(&master->dev, "can not get IRQ\n");
 845                 goto err_free_master;
 846         }
 847
 848         master->mode_bits = SPI_CPOL | SPI_CPHA;
 849         master->bus_num = dws->bus_num;
 850         master->num_chipselect = dws->num_cs;
 851         master->cleanup = dw_spi_cleanup;
 852         master->setup = dw_spi_setup;
 853         master->transfer = dw_spi_transfer;
 854
 855         /* Basic HW init */
 856         spi_hw_init(dws);
 857
 858         if (dws->dma_ops && dws->dma_ops->dma_init) {
 859                 ret = dws->dma_ops->dma_init(dws);
 860                 if (ret) {
 861                         dev_warn(&master->dev, "DMA init failed\n");
 862                         dws->dma_inited = 0;
 863                 }
 864         }
 865
 866         /* Initial and start queue */
 867         ret = init_queue(dws);
 868         if (ret) {
 869                 dev_err(&master->dev, "problem initializing queue\n");
 870                 goto err_diable_hw;
 871         }
 872         ret = start_queue(dws);
 873         if (ret) {
 874                 dev_err(&master->dev, "problem starting queue\n");
 875                 goto err_diable_hw;
 876         }
 877
 878         spi_master_set_devdata(master, dws);
 879         ret = spi_register_master(master);
 880         if (ret) {
 881                 dev_err(&master->dev, "problem registering spi master\n");
 882                 goto err_queue_alloc;
 883         }
 884
 885         mrst_spi_debugfs_init(dws);
 886         return 0;
 887
 888 err_queue_alloc:
 889         destroy_queue(dws);
 890         if (dws->dma_ops && dws->dma_ops->dma_exit)
 891                 dws->dma_ops->dma_exit(dws);
 892 err_diable_hw:
 893         spi_enable_chip(dws, 0);
 894         free_irq(dws->irq, dws);
 895 err_free_master:
 896         spi_master_put(master);
 897 exit:
 898         return ret;
 899 }
 900 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 901
 902 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 903 {
 904         int status = 0;
 905
 906         if (!dws)
 907                 return;
 908         mrst_spi_debugfs_remove(dws);
 909
 910         /* Remove the queue */
 911         status = destroy_queue(dws);
 912         if (status != 0)
 913                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 914                         "complete, message memory not freed\n");
 915
 916         if (dws->dma_ops && dws->dma_ops->dma_exit)
 917                 dws->dma_ops->dma_exit(dws);
 918         spi_enable_chip(dws, 0);
 919         /* Disable clk */
 920         spi_set_clk(dws, 0);
 921         free_irq(dws->irq, dws);
 922
 923         /* Disconnect from the SPI framework */
 924         spi_unregister_master(dws->master);
 925 }
 926 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 927
 928 int dw_spi_suspend_host(struct dw_spi *dws)
 929 {
 930         int ret = 0;
 931
 932         ret = stop_queue(dws);
 933         if (ret)
 934                 return ret;
 935         spi_enable_chip(dws, 0);
 936         spi_set_clk(dws, 0);
 937         return ret;
 938 }
 939 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 940
 941 int dw_spi_resume_host(struct dw_spi *dws)
 942 {
 943         int ret;
 944
 945         spi_hw_init(dws);
 946         ret = start_queue(dws);
 947         if (ret)
 948                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 949         return ret;
 950 }
 951 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 952
 953 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 954 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 955 MODULE_LICENSE("GPL v2");