2 * SPI Driver for EP93xx
4 * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
6 * Inspired form linux kernel driver and atmel uboot driver
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/ep93xx.h>
19 #define SSPBASE SPI_BASE
22 #define SSPCR0_MODE_SHIFT 6
23 #define SSPCR0_SCR_SHIFT 8
24 #define SSPCR0_SPH BIT(7)
25 #define SSPCR0_SPO BIT(6)
26 #define SSPCR0_FRF_SPI 0
27 #define SSPCR0_DSS_8BIT 7
30 #define SSPCR1_RIE BIT(0)
31 #define SSPCR1_TIE BIT(1)
32 #define SSPCR1_RORIE BIT(2)
33 #define SSPCR1_LBM BIT(3)
34 #define SSPCR1_SSE BIT(4)
35 #define SSPCR1_MS BIT(5)
36 #define SSPCR1_SOD BIT(6)
41 #define SSPSR_TFE BIT(0)
42 #define SSPSR_TNF BIT(1)
43 #define SSPSR_RNE BIT(2)
44 #define SSPSR_RFF BIT(3)
45 #define SSPSR_BSY BIT(4)
46 #define SSPCPSR 0x0010
49 #define SSPIIR_RIS BIT(0)
50 #define SSPIIR_TIS BIT(1)
51 #define SSPIIR_RORIS BIT(2)
54 #define SSPCLOCK 14745600
55 #define SSP_MAX_RATE (SSPCLOCK / 2)
56 #define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
58 /* timeout in milliseconds */
60 /* maximum depth of RX/TX FIFO */
61 #define SPI_FIFO_SIZE 8
63 struct ep93xx_spi_slave {
64 struct spi_slave slave;
70 static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
72 return container_of(slave, struct ep93xx_spi_slave, slave);
79 static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
81 writel(value, (unsigned int *)(SSPBASE + reg));
84 static inline u8 ep93xx_spi_read_u8(u16 reg)
86 return readl((unsigned int *)(SSPBASE + reg));
89 static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
91 writel(value, (unsigned int *)(SSPBASE + reg));
94 static inline u16 ep93xx_spi_read_u16(u16 reg)
96 return (u16)readl((unsigned int *)(SSPBASE + reg));
99 static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
100 struct ep93xx_spi_slave *slave)
104 if (rate > SSP_MAX_RATE)
107 if (rate < SSP_MIN_RATE)
110 /* Calculate divisors so that we can get speed according the
112 * rate = spi_clock_rate / (cpsr * (1 + scr))
114 * cpsr must be even number and starts from 2, scr can be any number
117 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
118 for (scr = 0; scr <= 255; scr++) {
119 if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
120 /* Set CHPA and CPOL, SPI format and 8bit */
121 unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
122 SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
124 sspcr0 |= SSPCR0_SPH;
126 sspcr0 |= SSPCR0_SPO;
128 slave->sspcr0 = sspcr0;
129 slave->sspcpsr = cpsr;
138 void spi_set_speed(struct spi_slave *slave, unsigned int hz)
140 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
142 unsigned int mode = 0;
143 if (as->sspcr0 & SSPCR0_SPH)
145 if (as->sspcr0 & SSPCR0_SPO)
148 ep93xx_spi_init_hw(hz, mode, as);
151 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
152 unsigned int max_hz, unsigned int mode)
154 struct ep93xx_spi_slave *as;
156 if (!spi_cs_is_valid(bus, cs))
159 as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
163 if (ep93xx_spi_init_hw(max_hz, mode, as)) {
171 void spi_free_slave(struct spi_slave *slave)
173 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
178 int spi_claim_bus(struct spi_slave *slave)
180 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
182 /* Enable the SPI hardware */
183 ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
186 ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
187 ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
189 debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
190 slave->cs, as->sspcpsr, as->sspcr0);
194 void spi_release_bus(struct spi_slave *slave)
196 /* Disable the SPI hardware */
197 ep93xx_spi_write_u8(SSPCR1, 0);
200 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
201 const void *dout, void *din, unsigned long flags)
207 const u8 *txp = dout;
211 debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
212 slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
216 /* Finish any previously submitted transfers */
220 /* Errors always terminate an ongoing transfer */
221 flags |= SPI_XFER_END;
228 if (flags & SPI_XFER_BEGIN) {
230 while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
231 ep93xx_spi_read_u8(SSPDR);
233 spi_cs_activate(slave);
236 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
237 status = ep93xx_spi_read_u8(SSPSR);
239 if ((len_tx < len) && (status & SSPSR_TNF)) {
245 ep93xx_spi_write_u8(SSPDR, value);
249 if (status & SSPSR_RNE) {
250 value = ep93xx_spi_read_u8(SSPDR);
259 if (flags & SPI_XFER_END) {
261 * Wait until the transfer is completely done before
265 status = ep93xx_spi_read_u8(SSPSR);
266 } while (status & SSPSR_BSY);
268 spi_cs_deactivate(slave);