2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
19 #define SPI_OPCODE_WREN 0x06
20 #define SPI_OPCODE_FAST_READ 0x0b
23 pci_dev_t dev; /* PCI device number */
24 int ich_version; /* Controller version, 7 or 9 */
25 bool use_sbase; /* Use SBASE instead of RCB */
30 void *base; /* Base of register set */
39 uint32_t *pr; /* only for ich9 */
40 uint8_t *speed; /* pointer to speed control */
41 ulong max_speed; /* Maximum bus speed in MHz */
46 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave)
48 return container_of(slave, struct ich_spi_slave, slave);
51 static unsigned int ich_reg(const void *addr)
53 return (unsigned)(addr - ctlr.base) & 0xffff;
56 static u8 ich_readb(const void *addr)
58 u8 value = readb(addr);
60 debug("read %2.2x from %4.4x\n", value, ich_reg(addr));
65 static u16 ich_readw(const void *addr)
67 u16 value = readw(addr);
69 debug("read %4.4x from %4.4x\n", value, ich_reg(addr));
74 static u32 ich_readl(const void *addr)
76 u32 value = readl(addr);
78 debug("read %8.8x from %4.4x\n", value, ich_reg(addr));
83 static void ich_writeb(u8 value, void *addr)
86 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr));
89 static void ich_writew(u16 value, void *addr)
92 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr));
95 static void ich_writel(u32 value, void *addr)
98 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr));
101 static void write_reg(const void *value, void *dest, uint32_t size)
103 memcpy_toio(dest, value, size);
106 static void read_reg(const void *src, void *value, uint32_t size)
108 memcpy_fromio(value, src, size);
111 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr)
113 const uint32_t bbar_mask = 0x00ffff00;
114 uint32_t ichspi_bbar;
116 minaddr &= bbar_mask;
117 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask;
118 ichspi_bbar |= minaddr;
119 ich_writel(ichspi_bbar, ctlr->bbar);
122 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
124 puts("spi_cs_is_valid used but not implemented\n");
128 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
129 unsigned int max_hz, unsigned int mode)
131 struct ich_spi_slave *ich;
133 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs);
135 puts("ICH SPI: Out of memory\n");
140 * Yes this controller can only write a small number of bytes at
141 * once! The limit is typically 64 bytes.
143 ich->slave.max_write_size = ctlr.databytes;
147 * ICH 7 SPI controller only supports array read command
148 * and byte program command for SST flash
150 if (ctlr.ich_version == 7 || ctlr.use_sbase) {
151 ich->slave.op_mode_rx = SPI_OPM_RX_AS;
152 ich->slave.op_mode_tx = SPI_OPM_TX_BP;
158 struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
161 /* We only support a single SPI at present */
162 return spi_setup_slave(0, 0, 20000000, 0);
165 void spi_free_slave(struct spi_slave *slave)
167 struct ich_spi_slave *ich = to_ich_spi(slave);
173 * Check if this device ID matches one of supported Intel PCH devices.
175 * Return the ICH version if there is a match, or zero otherwise.
177 static int get_ich_version(uint16_t device_id)
179 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
180 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
183 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
184 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
185 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
186 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
187 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
193 /* @return 1 if the SPI flash supports the 33MHz speed */
194 static int ich9_can_do_33mhz(pci_dev_t dev)
198 /* Observe SPI Descriptor Component Section 0 */
199 pci_write_config_dword(dev, 0xb0, 0x1000);
201 /* Extract the Write/Erase SPI Frequency from descriptor */
202 pci_read_config_dword(dev, 0xb4, &fdod);
204 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
205 speed = (fdod >> 21) & 7;
210 static int ich_find_spi_controller(struct ich_ctlr *ich)
212 int last_bus = pci_last_busno();
215 if (last_bus == -1) {
216 debug("No PCI busses?\n");
220 for (bus = 0; bus <= last_bus; bus++) {
221 uint16_t vendor_id, device_id;
225 dev = PCI_BDF(bus, 31, 0);
226 pci_read_config_dword(dev, 0, &ids);
228 device_id = ids >> 16;
230 if (vendor_id == PCI_VENDOR_ID_INTEL) {
232 ich->ich_version = get_ich_version(device_id);
233 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
234 ich->use_sbase = true;
235 return ich->ich_version == 0 ? -ENODEV : 0;
239 debug("ICH SPI: No ICH found.\n");
243 static int ich_init_controller(struct ich_ctlr *ctlr)
245 uint8_t *rcrb; /* Root Complex Register Block */
246 uint32_t rcba; /* Root Complex Base Address */
250 pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
251 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
252 rcrb = (uint8_t *)(rcba & 0xffffc000);
254 /* SBASE is similar */
255 pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
256 sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
258 if (ctlr->ich_version == 7) {
259 struct ich7_spi_regs *ich7_spi;
261 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
262 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK;
263 ctlr->opmenu = ich7_spi->opmenu;
264 ctlr->menubytes = sizeof(ich7_spi->opmenu);
265 ctlr->optype = &ich7_spi->optype;
266 ctlr->addr = &ich7_spi->spia;
267 ctlr->data = (uint8_t *)ich7_spi->spid;
268 ctlr->databytes = sizeof(ich7_spi->spid);
269 ctlr->status = (uint8_t *)&ich7_spi->spis;
270 ctlr->control = &ich7_spi->spic;
271 ctlr->bbar = &ich7_spi->bbar;
272 ctlr->preop = &ich7_spi->preop;
273 ctlr->base = ich7_spi;
274 } else if (ctlr->ich_version == 9) {
275 struct ich9_spi_regs *ich9_spi;
278 ich9_spi = (struct ich9_spi_regs *)sbase;
280 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
281 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
282 ctlr->opmenu = ich9_spi->opmenu;
283 ctlr->menubytes = sizeof(ich9_spi->opmenu);
284 ctlr->optype = &ich9_spi->optype;
285 ctlr->addr = &ich9_spi->faddr;
286 ctlr->data = (uint8_t *)ich9_spi->fdata;
287 ctlr->databytes = sizeof(ich9_spi->fdata);
288 ctlr->status = &ich9_spi->ssfs;
289 ctlr->control = (uint16_t *)ich9_spi->ssfc;
290 ctlr->speed = ich9_spi->ssfc + 2;
291 ctlr->bbar = &ich9_spi->bbar;
292 ctlr->preop = &ich9_spi->preop;
293 ctlr->pr = &ich9_spi->pr[0];
294 ctlr->base = ich9_spi;
296 debug("ICH SPI: Unrecognized ICH version %d.\n",
301 /* Work out the maximum speed we can support */
302 ctlr->max_speed = 20000000;
303 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
304 ctlr->max_speed = 33000000;
305 debug("ICH SPI: Version %d detected at %p, speed %ld\n",
306 ctlr->ich_version, ctlr->base, ctlr->max_speed);
308 ich_set_bbar(ctlr, 0);
317 if (ich_find_spi_controller(&ctlr)) {
318 printf("ICH SPI: Cannot find device\n");
322 if (ich_init_controller(&ctlr)) {
323 printf("ICH SPI: Cannot setup controller\n");
328 * Disable the BIOS write protect so write commands are allowed. On
329 * v9, deassert SMM BIOS Write Protect Disable.
331 if (ctlr.use_sbase) {
332 struct ich9_spi_regs *ich9_spi;
334 ich9_spi = (struct ich9_spi_regs *)ctlr.base;
335 bios_cntl = ich_readb(&ich9_spi->bcr);
336 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
337 bios_cntl |= 1; /* Write Protect Disable (WPD) */
338 ich_writeb(bios_cntl, &ich9_spi->bcr);
340 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
341 if (ctlr.ich_version == 9)
342 bios_cntl &= ~(1 << 5);
343 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
347 int spi_claim_bus(struct spi_slave *slave)
349 /* Handled by ICH automatically. */
353 void spi_release_bus(struct spi_slave *slave)
355 /* Handled by ICH automatically. */
358 void spi_cs_activate(struct spi_slave *slave)
360 /* Handled by ICH automatically. */
363 void spi_cs_deactivate(struct spi_slave *slave)
365 /* Handled by ICH automatically. */
368 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
371 trans->bytesout -= bytes;
374 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
377 trans->bytesin -= bytes;
380 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
384 /* Try to guess spi type from read/write sizes. */
385 if (trans->bytesin == 0) {
386 if (trans->bytesout + data_bytes > 4)
388 * If bytesin = 0 and bytesout > 4, we presume this is
389 * a write data operation, which is accompanied by an
392 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
394 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
398 if (trans->bytesout == 1) { /* and bytesin is > 0 */
399 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
403 if (trans->bytesout == 4) /* and bytesin is > 0 */
404 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
406 /* Fast read command is called with 5 bytes instead of 4 */
407 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
408 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
413 static int spi_setup_opcode(struct spi_trans *trans)
416 uint8_t opmenu[ctlr.menubytes];
418 trans->opcode = trans->out[0];
419 spi_use_out(trans, 1);
420 if (!ctlr.ichspi_lock) {
421 /* The lock is off, so just use index 0. */
422 ich_writeb(trans->opcode, ctlr.opmenu);
423 optypes = ich_readw(ctlr.optype);
424 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
425 ich_writew(optypes, ctlr.optype);
428 /* The lock is on. See if what we need is on the menu. */
430 uint16_t opcode_index;
432 /* Write Enable is handled as atomic prefix */
433 if (trans->opcode == SPI_OPCODE_WREN)
436 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu));
437 for (opcode_index = 0; opcode_index < ctlr.menubytes;
439 if (opmenu[opcode_index] == trans->opcode)
443 if (opcode_index == ctlr.menubytes) {
444 printf("ICH SPI: Opcode %x not found\n",
449 optypes = ich_readw(ctlr.optype);
450 optype = (optypes >> (opcode_index * 2)) & 0x3;
451 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
452 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
453 trans->bytesout >= 3) {
454 /* We guessed wrong earlier. Fix it up. */
455 trans->type = optype;
457 if (optype != trans->type) {
458 printf("ICH SPI: Transaction doesn't fit type %d\n",
466 static int spi_setup_offset(struct spi_trans *trans)
468 /* Separate the SPI address and data. */
469 switch (trans->type) {
470 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
471 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
473 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
474 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
475 trans->offset = ((uint32_t)trans->out[0] << 16) |
476 ((uint32_t)trans->out[1] << 8) |
477 ((uint32_t)trans->out[2] << 0);
478 spi_use_out(trans, 3);
481 printf("Unrecognized SPI transaction type %#x\n", trans->type);
487 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
488 * below is true) or 0. In case the wait was for the bit(s) to set - write
489 * those bits back, which would cause resetting them.
491 * Return the last read status value on success or -1 on failure.
493 static int ich_status_poll(u16 bitmask, int wait_til_set)
495 int timeout = 600000; /* This will result in 6s */
499 status = ich_readw(ctlr.status);
500 if (wait_til_set ^ ((status & bitmask) == 0)) {
502 ich_writew((status & bitmask), ctlr.status);
508 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
514 int spi_xfer(struct spi_slave *slave, const void *dout,
515 unsigned int bitsout, void *din, unsigned int bitsin)
517 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
518 void *din, unsigned long flags)
520 struct ich_spi_slave *ich = to_ich_spi(slave);
522 int16_t opcode_index;
525 int bytes = bitlen / 8;
526 struct spi_trans *trans = &ich->trans;
527 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
530 /* Ee don't support writing partial bytes. */
532 debug("ICH SPI: Accessing partial bytes not supported\n");
536 /* An empty end transaction can be ignored */
537 if (type == SPI_XFER_END && !dout && !din)
540 if (type & SPI_XFER_BEGIN)
541 memset(trans, '\0', sizeof(*trans));
543 /* Dp we need to come back later to finish it? */
544 if (dout && type == SPI_XFER_BEGIN) {
545 if (bytes > ICH_MAX_CMD_LEN) {
546 debug("ICH SPI: Command length limit exceeded\n");
549 memcpy(trans->cmd, dout, bytes);
550 trans->cmd_len = bytes;
551 debug("ICH SPI: Saved %d bytes\n", bytes);
556 * We process a 'middle' spi_xfer() call, which has no
557 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
558 * an end. We therefore repeat the command. This is because ICH
559 * seems to have no support for this, or because interest (in digging
560 * out the details and creating a special case in the code) is low.
562 if (trans->cmd_len) {
563 trans->out = trans->cmd;
564 trans->bytesout = trans->cmd_len;
566 debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
569 trans->bytesout = dout ? bytes : 0;
573 trans->bytesin = din ? bytes : 0;
575 /* There has to always at least be an opcode. */
576 if (!trans->bytesout) {
577 debug("ICH SPI: No opcode for transfer\n");
581 if (ich_status_poll(SPIS_SCIP, 0) == -1)
584 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status);
586 spi_setup_type(trans, using_cmd ? bytes : 0);
587 opcode_index = spi_setup_opcode(trans);
588 if (opcode_index < 0)
590 with_address = spi_setup_offset(trans);
591 if (with_address < 0)
594 if (trans->opcode == SPI_OPCODE_WREN) {
596 * Treat Write Enable as Atomic Pre-Op if possible
597 * in order to prevent the Management Engine from
598 * issuing a transaction between WREN and DATA.
600 if (!ctlr.ichspi_lock)
601 ich_writew(trans->opcode, ctlr.preop);
605 if (ctlr.speed && ctlr.max_speed >= 33000000) {
608 byte = ich_readb(ctlr.speed);
609 if (ich->speed >= 33000000)
610 byte |= SSFC_SCF_33MHZ;
612 byte &= ~SSFC_SCF_33MHZ;
613 ich_writeb(byte, ctlr.speed);
616 /* See if we have used up the command data */
617 if (using_cmd && dout && bytes) {
619 trans->bytesout = bytes;
620 debug("ICH SPI: Moving to data, %d bytes\n", bytes);
623 /* Preset control fields */
624 control = ich_readw(ctlr.control);
625 control &= ~SSFC_RESERVED;
626 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
628 /* Issue atomic preop cycle if needed */
629 if (ich_readw(ctlr.preop))
632 if (!trans->bytesout && !trans->bytesin) {
633 /* SPI addresses are 24 bit only */
635 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
638 * This is a 'no data' command (like Write Enable), its
639 * bitesout size was 1, decremented to zero while executing
640 * spi_setup_opcode() above. Tell the chip to send the
643 ich_writew(control, ctlr.control);
645 /* wait for the result */
646 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
650 if (status & SPIS_FCERR) {
651 debug("ICH SPI: Command transaction error\n");
659 * Check if this is a write command atempting to transfer more bytes
660 * than the controller can handle. Iterations for writes are not
661 * supported here because each SPI write command needs to be preceded
662 * and followed by other SPI commands, and this sequence is controlled
663 * by the SPI chip driver.
665 if (trans->bytesout > ctlr.databytes) {
666 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
671 * Read or write up to databytes bytes at a time until everything has
674 while (trans->bytesout || trans->bytesin) {
675 uint32_t data_length;
677 /* SPI addresses are 24 bit only */
678 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
681 data_length = min(trans->bytesout, ctlr.databytes);
683 data_length = min(trans->bytesin, ctlr.databytes);
685 /* Program data into FDATA0 to N */
686 if (trans->bytesout) {
687 write_reg(trans->out, ctlr.data, data_length);
688 spi_use_out(trans, data_length);
690 trans->offset += data_length;
693 /* Add proper control fields' values */
694 control &= ~((ctlr.databytes - 1) << 8);
696 control |= (data_length - 1) << 8;
699 ich_writew(control, ctlr.control);
701 /* Wait for Cycle Done Status or Flash Cycle Error. */
702 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
706 if (status & SPIS_FCERR) {
707 debug("ICH SPI: Data transaction error\n");
711 if (trans->bytesin) {
712 read_reg(ctlr.data, trans->in, data_length);
713 spi_use_in(trans, data_length);
715 trans->offset += data_length;
719 /* Clear atomic preop now that xfer is done */
720 ich_writew(0, ctlr.preop);
727 * This uses the SPI controller from the Intel Cougar Point and Panther Point
728 * PCH to write-protect portions of the SPI flash until reboot. The changes
729 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
732 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint)
735 uint32_t upper_limit;
738 printf("%s: operation not supported on this chipset\n",
744 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
745 hint < 0 || hint > 4) {
746 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
747 lower_limit, length, hint);
751 upper_limit = lower_limit + length - 1;
754 * Determine bits to write, as follows:
755 * 31 Write-protection enable (includes erase operation)
757 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
758 * 15 Read-protection enable
760 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
762 tmplong = 0x80000000 |
763 ((upper_limit & 0x01fff000) << 4) |
764 ((lower_limit & 0x01fff000) >> 12);
766 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
768 ctlr.pr[hint] = tmplong;