2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/slab.h>
37 #include <linux/spi/spi.h>
40 #include <plat/clock.h>
43 #define OMAP2_MCSPI_MAX_FREQ 48000000
45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
46 #define OMAP2_MCSPI_MAX_CTRL 4
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSCONFIG 0x10
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
73 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
77 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
78 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
80 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
81 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
84 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
85 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
86 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
87 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
88 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
89 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
90 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
91 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
97 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma {
109 struct completion dma_tx_completion;
110 struct completion dma_rx_completion;
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate.
116 #define DMA_MIN_BYTES 8
120 struct work_struct work;
121 /* lock protects queue and registers */
123 struct list_head msg_queue;
124 struct spi_master *master;
127 /* Virtual base address of the controller */
130 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma *dma_channels;
134 struct omap2_mcspi_cs {
138 struct list_head node;
139 /* Context save and restore shadow register */
143 /* used for context save and restore, structure members to be updated whenever
144 * corresponding registers are modified.
146 struct omap2_mcspi_regs {
153 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
155 static struct workqueue_struct *omap2_mcspi_wq;
157 #define MOD_REG_BIT(val, mask, set) do { \
164 static inline void mcspi_write_reg(struct spi_master *master,
167 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
169 __raw_writel(val, mcspi->base + idx);
172 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
174 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
176 return __raw_readl(mcspi->base + idx);
179 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
182 struct omap2_mcspi_cs *cs = spi->controller_state;
184 __raw_writel(val, cs->base + idx);
187 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
189 struct omap2_mcspi_cs *cs = spi->controller_state;
191 return __raw_readl(cs->base + idx);
194 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
196 struct omap2_mcspi_cs *cs = spi->controller_state;
201 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
203 struct omap2_mcspi_cs *cs = spi->controller_state;
206 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
209 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
210 int is_read, int enable)
214 l = mcspi_cached_chconf0(spi);
216 if (is_read) /* 1 is read, 0 write */
217 rw = OMAP2_MCSPI_CHCONF_DMAR;
219 rw = OMAP2_MCSPI_CHCONF_DMAW;
221 MOD_REG_BIT(l, rw, enable);
222 mcspi_write_chconf0(spi, l);
225 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
229 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
230 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
233 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
237 l = mcspi_cached_chconf0(spi);
238 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
239 mcspi_write_chconf0(spi, l);
242 static void omap2_mcspi_set_master_mode(struct spi_master *master)
246 /* setup when switching from (reset default) slave mode
247 * to single-channel master mode
249 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
250 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
251 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
252 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
253 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
255 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
258 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
260 struct spi_master *spi_cntrl;
261 struct omap2_mcspi_cs *cs;
262 spi_cntrl = mcspi->master;
264 /* McSPI: context restore */
265 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
266 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
268 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
269 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
271 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
272 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
274 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
276 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
278 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
280 clk_disable(mcspi->ick);
281 clk_disable(mcspi->fck);
284 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
286 if (clk_enable(mcspi->ick))
288 if (clk_enable(mcspi->fck))
291 omap2_mcspi_restore_ctx(mcspi);
297 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
299 struct omap2_mcspi *mcspi;
300 struct omap2_mcspi_cs *cs = spi->controller_state;
301 struct omap2_mcspi_dma *mcspi_dma;
302 unsigned int count, c;
303 unsigned long base, tx_reg, rx_reg;
304 int word_len, data_type, element_count;
308 mcspi = spi_master_get_devdata(spi->master);
309 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
313 word_len = cs->word_len;
316 tx_reg = base + OMAP2_MCSPI_TX0;
317 rx_reg = base + OMAP2_MCSPI_RX0;
322 data_type = OMAP_DMA_DATA_TYPE_S8;
323 element_count = count;
324 } else if (word_len <= 16) {
325 data_type = OMAP_DMA_DATA_TYPE_S16;
326 element_count = count >> 1;
327 } else /* word_len <= 32 */ {
328 data_type = OMAP_DMA_DATA_TYPE_S32;
329 element_count = count >> 2;
333 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
334 data_type, element_count, 1,
335 OMAP_DMA_SYNC_ELEMENT,
336 mcspi_dma->dma_tx_sync_dev, 0);
338 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
339 OMAP_DMA_AMODE_CONSTANT,
342 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
343 OMAP_DMA_AMODE_POST_INC,
348 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
349 data_type, element_count - 1, 1,
350 OMAP_DMA_SYNC_ELEMENT,
351 mcspi_dma->dma_rx_sync_dev, 1);
353 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
354 OMAP_DMA_AMODE_CONSTANT,
357 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
358 OMAP_DMA_AMODE_POST_INC,
363 omap_start_dma(mcspi_dma->dma_tx_channel);
364 omap2_mcspi_set_dma_req(spi, 0, 1);
368 omap_start_dma(mcspi_dma->dma_rx_channel);
369 omap2_mcspi_set_dma_req(spi, 1, 1);
373 wait_for_completion(&mcspi_dma->dma_tx_completion);
374 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
378 wait_for_completion(&mcspi_dma->dma_rx_completion);
379 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
380 omap2_mcspi_set_enable(spi, 0);
381 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
382 & OMAP2_MCSPI_CHSTAT_RXS)) {
385 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
387 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
388 else if (word_len <= 16)
389 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
390 else /* word_len <= 32 */
391 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
393 dev_err(&spi->dev, "DMA RX last word empty");
394 count -= (word_len <= 8) ? 1 :
395 (word_len <= 16) ? 2 :
396 /* word_len <= 32 */ 4;
398 omap2_mcspi_set_enable(spi, 1);
403 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
405 unsigned long timeout;
407 timeout = jiffies + msecs_to_jiffies(1000);
408 while (!(__raw_readl(reg) & bit)) {
409 if (time_after(jiffies, timeout))
417 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
419 struct omap2_mcspi *mcspi;
420 struct omap2_mcspi_cs *cs = spi->controller_state;
421 unsigned int count, c;
423 void __iomem *base = cs->base;
424 void __iomem *tx_reg;
425 void __iomem *rx_reg;
426 void __iomem *chstat_reg;
429 mcspi = spi_master_get_devdata(spi->master);
432 word_len = cs->word_len;
434 l = mcspi_cached_chconf0(spi);
435 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
437 /* We store the pre-calculated register addresses on stack to speed
438 * up the transfer loop. */
439 tx_reg = base + OMAP2_MCSPI_TX0;
440 rx_reg = base + OMAP2_MCSPI_RX0;
441 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
453 if (mcspi_wait_for_reg_bit(chstat_reg,
454 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
455 dev_err(&spi->dev, "TXS timed out\n");
459 dev_dbg(&spi->dev, "write-%d %02x\n",
462 __raw_writel(*tx++, tx_reg);
465 if (mcspi_wait_for_reg_bit(chstat_reg,
466 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
467 dev_err(&spi->dev, "RXS timed out\n");
470 /* prevent last RX_ONLY read from triggering
471 * more word i/o: switch to rx+tx
473 if (c == 0 && tx == NULL)
474 mcspi_write_chconf0(spi, l);
475 *rx++ = __raw_readl(rx_reg);
477 dev_dbg(&spi->dev, "read-%d %02x\n",
478 word_len, *(rx - 1));
482 } else if (word_len <= 16) {
491 if (mcspi_wait_for_reg_bit(chstat_reg,
492 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
493 dev_err(&spi->dev, "TXS timed out\n");
497 dev_dbg(&spi->dev, "write-%d %04x\n",
500 __raw_writel(*tx++, tx_reg);
503 if (mcspi_wait_for_reg_bit(chstat_reg,
504 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
505 dev_err(&spi->dev, "RXS timed out\n");
508 /* prevent last RX_ONLY read from triggering
509 * more word i/o: switch to rx+tx
511 if (c == 0 && tx == NULL)
512 mcspi_write_chconf0(spi, l);
513 *rx++ = __raw_readl(rx_reg);
515 dev_dbg(&spi->dev, "read-%d %04x\n",
516 word_len, *(rx - 1));
520 } else if (word_len <= 32) {
529 if (mcspi_wait_for_reg_bit(chstat_reg,
530 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
531 dev_err(&spi->dev, "TXS timed out\n");
535 dev_dbg(&spi->dev, "write-%d %04x\n",
538 __raw_writel(*tx++, tx_reg);
541 if (mcspi_wait_for_reg_bit(chstat_reg,
542 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
543 dev_err(&spi->dev, "RXS timed out\n");
546 /* prevent last RX_ONLY read from triggering
547 * more word i/o: switch to rx+tx
549 if (c == 0 && tx == NULL)
550 mcspi_write_chconf0(spi, l);
551 *rx++ = __raw_readl(rx_reg);
553 dev_dbg(&spi->dev, "read-%d %04x\n",
554 word_len, *(rx - 1));
560 /* for TX_ONLY mode, be sure all words have shifted out */
561 if (xfer->rx_buf == NULL) {
562 if (mcspi_wait_for_reg_bit(chstat_reg,
563 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
564 dev_err(&spi->dev, "TXS timed out\n");
565 } else if (mcspi_wait_for_reg_bit(chstat_reg,
566 OMAP2_MCSPI_CHSTAT_EOT) < 0)
567 dev_err(&spi->dev, "EOT timed out\n");
573 /* called only when no transfer is active to this device */
574 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
575 struct spi_transfer *t)
577 struct omap2_mcspi_cs *cs = spi->controller_state;
578 struct omap2_mcspi *mcspi;
579 struct spi_master *spi_cntrl;
581 u8 word_len = spi->bits_per_word;
582 u32 speed_hz = spi->max_speed_hz;
584 mcspi = spi_master_get_devdata(spi->master);
585 spi_cntrl = mcspi->master;
587 if (t != NULL && t->bits_per_word)
588 word_len = t->bits_per_word;
590 cs->word_len = word_len;
592 if (t && t->speed_hz)
593 speed_hz = t->speed_hz;
596 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
602 l = mcspi_cached_chconf0(spi);
604 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
605 * REVISIT: this controller could support SPI_3WIRE mode.
607 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
608 l |= OMAP2_MCSPI_CHCONF_DPE0;
611 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
612 l |= (word_len - 1) << 7;
614 /* set chipselect polarity; manage with FORCE */
615 if (!(spi->mode & SPI_CS_HIGH))
616 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
618 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
620 /* set clock divisor */
621 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
624 /* set SPI mode 0..3 */
625 if (spi->mode & SPI_CPOL)
626 l |= OMAP2_MCSPI_CHCONF_POL;
628 l &= ~OMAP2_MCSPI_CHCONF_POL;
629 if (spi->mode & SPI_CPHA)
630 l |= OMAP2_MCSPI_CHCONF_PHA;
632 l &= ~OMAP2_MCSPI_CHCONF_PHA;
634 mcspi_write_chconf0(spi, l);
636 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
637 OMAP2_MCSPI_MAX_FREQ / (1 << div),
638 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
639 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
644 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
646 struct spi_device *spi = data;
647 struct omap2_mcspi *mcspi;
648 struct omap2_mcspi_dma *mcspi_dma;
650 mcspi = spi_master_get_devdata(spi->master);
651 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
653 complete(&mcspi_dma->dma_rx_completion);
655 /* We must disable the DMA RX request */
656 omap2_mcspi_set_dma_req(spi, 1, 0);
659 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
661 struct spi_device *spi = data;
662 struct omap2_mcspi *mcspi;
663 struct omap2_mcspi_dma *mcspi_dma;
665 mcspi = spi_master_get_devdata(spi->master);
666 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
668 complete(&mcspi_dma->dma_tx_completion);
670 /* We must disable the DMA TX request */
671 omap2_mcspi_set_dma_req(spi, 0, 0);
674 static int omap2_mcspi_request_dma(struct spi_device *spi)
676 struct spi_master *master = spi->master;
677 struct omap2_mcspi *mcspi;
678 struct omap2_mcspi_dma *mcspi_dma;
680 mcspi = spi_master_get_devdata(master);
681 mcspi_dma = mcspi->dma_channels + spi->chip_select;
683 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
684 omap2_mcspi_dma_rx_callback, spi,
685 &mcspi_dma->dma_rx_channel)) {
686 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
690 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
691 omap2_mcspi_dma_tx_callback, spi,
692 &mcspi_dma->dma_tx_channel)) {
693 omap_free_dma(mcspi_dma->dma_rx_channel);
694 mcspi_dma->dma_rx_channel = -1;
695 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
699 init_completion(&mcspi_dma->dma_rx_completion);
700 init_completion(&mcspi_dma->dma_tx_completion);
705 static int omap2_mcspi_setup(struct spi_device *spi)
708 struct omap2_mcspi *mcspi;
709 struct omap2_mcspi_dma *mcspi_dma;
710 struct omap2_mcspi_cs *cs = spi->controller_state;
712 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
713 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
718 mcspi = spi_master_get_devdata(spi->master);
719 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
722 cs = kzalloc(sizeof *cs, GFP_KERNEL);
725 cs->base = mcspi->base + spi->chip_select * 0x14;
726 cs->phys = mcspi->phys + spi->chip_select * 0x14;
728 spi->controller_state = cs;
729 /* Link this to context save list */
730 list_add_tail(&cs->node,
731 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
734 if (mcspi_dma->dma_rx_channel == -1
735 || mcspi_dma->dma_tx_channel == -1) {
736 ret = omap2_mcspi_request_dma(spi);
741 if (omap2_mcspi_enable_clocks(mcspi))
744 ret = omap2_mcspi_setup_transfer(spi, NULL);
745 omap2_mcspi_disable_clocks(mcspi);
750 static void omap2_mcspi_cleanup(struct spi_device *spi)
752 struct omap2_mcspi *mcspi;
753 struct omap2_mcspi_dma *mcspi_dma;
754 struct omap2_mcspi_cs *cs;
756 mcspi = spi_master_get_devdata(spi->master);
757 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
759 if (spi->controller_state) {
760 /* Unlink controller state from context save list */
761 cs = spi->controller_state;
764 kfree(spi->controller_state);
767 if (mcspi_dma->dma_rx_channel != -1) {
768 omap_free_dma(mcspi_dma->dma_rx_channel);
769 mcspi_dma->dma_rx_channel = -1;
771 if (mcspi_dma->dma_tx_channel != -1) {
772 omap_free_dma(mcspi_dma->dma_tx_channel);
773 mcspi_dma->dma_tx_channel = -1;
777 static void omap2_mcspi_work(struct work_struct *work)
779 struct omap2_mcspi *mcspi;
781 mcspi = container_of(work, struct omap2_mcspi, work);
782 spin_lock_irq(&mcspi->lock);
784 if (omap2_mcspi_enable_clocks(mcspi))
787 /* We only enable one channel at a time -- the one whose message is
788 * at the head of the queue -- although this controller would gladly
789 * arbitrate among multiple channels. This corresponds to "single
790 * channel" master mode. As a side effect, we need to manage the
791 * chipselect with the FORCE bit ... CS != channel enable.
793 while (!list_empty(&mcspi->msg_queue)) {
794 struct spi_message *m;
795 struct spi_device *spi;
796 struct spi_transfer *t = NULL;
798 struct omap2_mcspi_cs *cs;
799 int par_override = 0;
803 m = container_of(mcspi->msg_queue.next, struct spi_message,
806 list_del_init(&m->queue);
807 spin_unlock_irq(&mcspi->lock);
810 cs = spi->controller_state;
812 omap2_mcspi_set_enable(spi, 1);
813 list_for_each_entry(t, &m->transfers, transfer_list) {
814 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
818 if (par_override || t->speed_hz || t->bits_per_word) {
820 status = omap2_mcspi_setup_transfer(spi, t);
823 if (!t->speed_hz && !t->bits_per_word)
828 omap2_mcspi_force_cs(spi, 1);
832 chconf = mcspi_cached_chconf0(spi);
833 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
834 if (t->tx_buf == NULL)
835 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
836 else if (t->rx_buf == NULL)
837 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
838 mcspi_write_chconf0(spi, chconf);
843 /* RX_ONLY mode needs dummy data in TX reg */
844 if (t->tx_buf == NULL)
845 __raw_writel(0, cs->base
848 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
849 count = omap2_mcspi_txrx_dma(spi, t);
851 count = omap2_mcspi_txrx_pio(spi, t);
852 m->actual_length += count;
854 if (count != t->len) {
861 udelay(t->delay_usecs);
863 /* ignore the "leave it on after last xfer" hint */
865 omap2_mcspi_force_cs(spi, 0);
870 /* Restore defaults if they were overriden */
873 status = omap2_mcspi_setup_transfer(spi, NULL);
877 omap2_mcspi_force_cs(spi, 0);
879 omap2_mcspi_set_enable(spi, 0);
882 m->complete(m->context);
884 spin_lock_irq(&mcspi->lock);
887 omap2_mcspi_disable_clocks(mcspi);
890 spin_unlock_irq(&mcspi->lock);
893 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
895 struct omap2_mcspi *mcspi;
897 struct spi_transfer *t;
899 m->actual_length = 0;
902 /* reject invalid messages and transfers */
903 if (list_empty(&m->transfers) || !m->complete)
905 list_for_each_entry(t, &m->transfers, transfer_list) {
906 const void *tx_buf = t->tx_buf;
907 void *rx_buf = t->rx_buf;
908 unsigned len = t->len;
910 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
911 || (len && !(rx_buf || tx_buf))
912 || (t->bits_per_word &&
913 ( t->bits_per_word < 4
914 || t->bits_per_word > 32))) {
915 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
923 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
924 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
926 OMAP2_MCSPI_MAX_FREQ/(1<<16));
930 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
933 /* Do DMA mapping "early" for better error reporting and
934 * dcache use. Note that if dma_unmap_single() ever starts
935 * to do real work on ARM, we'd need to clean up mappings
936 * for previous transfers on *ALL* exits of this loop...
938 if (tx_buf != NULL) {
939 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
941 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
942 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
947 if (rx_buf != NULL) {
948 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
950 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
951 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
954 dma_unmap_single(NULL, t->tx_dma,
961 mcspi = spi_master_get_devdata(spi->master);
963 spin_lock_irqsave(&mcspi->lock, flags);
964 list_add_tail(&m->queue, &mcspi->msg_queue);
965 queue_work(omap2_mcspi_wq, &mcspi->work);
966 spin_unlock_irqrestore(&mcspi->lock, flags);
971 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
973 struct spi_master *master = mcspi->master;
976 if (omap2_mcspi_enable_clocks(mcspi))
979 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
980 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
982 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
983 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
985 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
986 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
987 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
988 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
989 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
991 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
992 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
993 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
995 omap2_mcspi_set_master_mode(master);
996 omap2_mcspi_disable_clocks(mcspi);
1000 static u8 __initdata spi1_rxdma_id [] = {
1001 OMAP24XX_DMA_SPI1_RX0,
1002 OMAP24XX_DMA_SPI1_RX1,
1003 OMAP24XX_DMA_SPI1_RX2,
1004 OMAP24XX_DMA_SPI1_RX3,
1007 static u8 __initdata spi1_txdma_id [] = {
1008 OMAP24XX_DMA_SPI1_TX0,
1009 OMAP24XX_DMA_SPI1_TX1,
1010 OMAP24XX_DMA_SPI1_TX2,
1011 OMAP24XX_DMA_SPI1_TX3,
1014 static u8 __initdata spi2_rxdma_id[] = {
1015 OMAP24XX_DMA_SPI2_RX0,
1016 OMAP24XX_DMA_SPI2_RX1,
1019 static u8 __initdata spi2_txdma_id[] = {
1020 OMAP24XX_DMA_SPI2_TX0,
1021 OMAP24XX_DMA_SPI2_TX1,
1024 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1025 || defined(CONFIG_ARCH_OMAP4)
1026 static u8 __initdata spi3_rxdma_id[] = {
1027 OMAP24XX_DMA_SPI3_RX0,
1028 OMAP24XX_DMA_SPI3_RX1,
1031 static u8 __initdata spi3_txdma_id[] = {
1032 OMAP24XX_DMA_SPI3_TX0,
1033 OMAP24XX_DMA_SPI3_TX1,
1037 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1038 static u8 __initdata spi4_rxdma_id[] = {
1039 OMAP34XX_DMA_SPI4_RX0,
1042 static u8 __initdata spi4_txdma_id[] = {
1043 OMAP34XX_DMA_SPI4_TX0,
1047 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1049 struct spi_master *master;
1050 struct omap2_mcspi *mcspi;
1053 const u8 *rxdma_id, *txdma_id;
1054 unsigned num_chipselect;
1058 rxdma_id = spi1_rxdma_id;
1059 txdma_id = spi1_txdma_id;
1063 rxdma_id = spi2_rxdma_id;
1064 txdma_id = spi2_txdma_id;
1067 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1068 || defined(CONFIG_ARCH_OMAP4)
1070 rxdma_id = spi3_rxdma_id;
1071 txdma_id = spi3_txdma_id;
1075 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1077 rxdma_id = spi4_rxdma_id;
1078 txdma_id = spi4_txdma_id;
1086 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1087 if (master == NULL) {
1088 dev_dbg(&pdev->dev, "master allocation failed\n");
1092 /* the spi->mode bits understood by this driver: */
1093 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1096 master->bus_num = pdev->id;
1098 master->setup = omap2_mcspi_setup;
1099 master->transfer = omap2_mcspi_transfer;
1100 master->cleanup = omap2_mcspi_cleanup;
1101 master->num_chipselect = num_chipselect;
1103 dev_set_drvdata(&pdev->dev, master);
1105 mcspi = spi_master_get_devdata(master);
1106 mcspi->master = master;
1108 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1113 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1114 dev_name(&pdev->dev))) {
1119 mcspi->phys = r->start;
1120 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1122 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1127 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1129 spin_lock_init(&mcspi->lock);
1130 INIT_LIST_HEAD(&mcspi->msg_queue);
1131 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1133 mcspi->ick = clk_get(&pdev->dev, "ick");
1134 if (IS_ERR(mcspi->ick)) {
1135 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1136 status = PTR_ERR(mcspi->ick);
1139 mcspi->fck = clk_get(&pdev->dev, "fck");
1140 if (IS_ERR(mcspi->fck)) {
1141 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1142 status = PTR_ERR(mcspi->fck);
1146 mcspi->dma_channels = kcalloc(master->num_chipselect,
1147 sizeof(struct omap2_mcspi_dma),
1150 if (mcspi->dma_channels == NULL)
1153 for (i = 0; i < num_chipselect; i++) {
1154 mcspi->dma_channels[i].dma_rx_channel = -1;
1155 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1156 mcspi->dma_channels[i].dma_tx_channel = -1;
1157 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1160 if (omap2_mcspi_reset(mcspi) < 0)
1163 status = spi_register_master(master);
1170 kfree(mcspi->dma_channels);
1172 clk_put(mcspi->fck);
1174 clk_put(mcspi->ick);
1176 iounmap(mcspi->base);
1178 release_mem_region(r->start, (r->end - r->start) + 1);
1180 spi_master_put(master);
1184 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1186 struct spi_master *master;
1187 struct omap2_mcspi *mcspi;
1188 struct omap2_mcspi_dma *dma_channels;
1192 master = dev_get_drvdata(&pdev->dev);
1193 mcspi = spi_master_get_devdata(master);
1194 dma_channels = mcspi->dma_channels;
1196 clk_put(mcspi->fck);
1197 clk_put(mcspi->ick);
1199 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200 release_mem_region(r->start, (r->end - r->start) + 1);
1203 spi_unregister_master(master);
1205 kfree(dma_channels);
1210 /* work with hotplug and coldplug */
1211 MODULE_ALIAS("platform:omap2_mcspi");
1213 static struct platform_driver omap2_mcspi_driver = {
1215 .name = "omap2_mcspi",
1216 .owner = THIS_MODULE,
1218 .remove = __exit_p(omap2_mcspi_remove),
1222 static int __init omap2_mcspi_init(void)
1224 omap2_mcspi_wq = create_singlethread_workqueue(
1225 omap2_mcspi_driver.driver.name);
1226 if (omap2_mcspi_wq == NULL)
1228 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1230 subsys_initcall(omap2_mcspi_init);
1232 static void __exit omap2_mcspi_exit(void)
1234 platform_driver_unregister(&omap2_mcspi_driver);
1236 destroy_workqueue(omap2_mcspi_wq);
1238 module_exit(omap2_mcspi_exit);
1240 MODULE_LICENSE("GPL");