2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
36 #include <linux/spi/spi.h>
39 #include <mach/clock.h>
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
44 #define OMAP2_MCSPI_REVISION 0x00
45 #define OMAP2_MCSPI_SYSCONFIG 0x10
46 #define OMAP2_MCSPI_SYSSTATUS 0x14
47 #define OMAP2_MCSPI_IRQSTATUS 0x18
48 #define OMAP2_MCSPI_IRQENABLE 0x1c
49 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
50 #define OMAP2_MCSPI_SYST 0x24
51 #define OMAP2_MCSPI_MODULCTRL 0x28
53 /* per-channel banks, 0x14 bytes each, first is: */
54 #define OMAP2_MCSPI_CHCONF0 0x2c
55 #define OMAP2_MCSPI_CHSTAT0 0x30
56 #define OMAP2_MCSPI_CHCTRL0 0x34
57 #define OMAP2_MCSPI_TX0 0x38
58 #define OMAP2_MCSPI_RX0 0x3c
60 /* per-register bitmasks: */
62 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
63 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
64 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
65 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
67 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
69 #define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0)
70 #define OMAP2_MCSPI_MODULCTRL_MS (1 << 2)
71 #define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3)
73 #define OMAP2_MCSPI_CHCONF_PHA (1 << 0)
74 #define OMAP2_MCSPI_CHCONF_POL (1 << 1)
75 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
76 #define OMAP2_MCSPI_CHCONF_EPOL (1 << 6)
77 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
78 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
79 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
80 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
81 #define OMAP2_MCSPI_CHCONF_DMAW (1 << 14)
82 #define OMAP2_MCSPI_CHCONF_DMAR (1 << 15)
83 #define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16)
84 #define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17)
85 #define OMAP2_MCSPI_CHCONF_IS (1 << 18)
86 #define OMAP2_MCSPI_CHCONF_TURBO (1 << 19)
87 #define OMAP2_MCSPI_CHCONF_FORCE (1 << 20)
89 #define OMAP2_MCSPI_CHSTAT_RXS (1 << 0)
90 #define OMAP2_MCSPI_CHSTAT_TXS (1 << 1)
91 #define OMAP2_MCSPI_CHSTAT_EOT (1 << 2)
93 #define OMAP2_MCSPI_CHCTRL_EN (1 << 0)
95 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
97 /* We have 2 DMA channels per CS, one for RX and one for TX */
98 struct omap2_mcspi_dma {
105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
109 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
110 * cache operations; better heuristics consider wordsize and bitrate.
112 #define DMA_MIN_BYTES 8
116 struct work_struct work;
117 /* lock protects queue and registers */
119 struct list_head msg_queue;
120 struct spi_master *master;
123 /* Virtual base address of the controller */
126 /* SPI1 has 4 channels, while SPI2 has 2 */
127 struct omap2_mcspi_dma *dma_channels;
130 struct omap2_mcspi_cs {
136 static struct workqueue_struct *omap2_mcspi_wq;
138 #define MOD_REG_BIT(val, mask, set) do { \
145 static inline void mcspi_write_reg(struct spi_master *master,
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
150 __raw_writel(val, mcspi->base + idx);
153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
157 return __raw_readl(mcspi->base + idx);
160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
163 struct omap2_mcspi_cs *cs = spi->controller_state;
165 __raw_writel(val, cs->base + idx);
168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
170 struct omap2_mcspi_cs *cs = spi->controller_state;
172 return __raw_readl(cs->base + idx);
175 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
176 int is_read, int enable)
180 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
182 if (is_read) /* 1 is read, 0 write */
183 rw = OMAP2_MCSPI_CHCONF_DMAR;
185 rw = OMAP2_MCSPI_CHCONF_DMAW;
187 MOD_REG_BIT(l, rw, enable);
188 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
191 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
195 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
196 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
199 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
203 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
204 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
205 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
208 static void omap2_mcspi_set_master_mode(struct spi_master *master)
212 /* setup when switching from (reset default) slave mode
213 * to single-channel master mode
215 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
216 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
217 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
218 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
219 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
223 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
225 struct omap2_mcspi *mcspi;
226 struct omap2_mcspi_cs *cs = spi->controller_state;
227 struct omap2_mcspi_dma *mcspi_dma;
228 unsigned int count, c;
229 unsigned long base, tx_reg, rx_reg;
230 int word_len, data_type, element_count;
234 mcspi = spi_master_get_devdata(spi->master);
235 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
239 word_len = cs->word_len;
242 tx_reg = base + OMAP2_MCSPI_TX0;
243 rx_reg = base + OMAP2_MCSPI_RX0;
248 data_type = OMAP_DMA_DATA_TYPE_S8;
249 element_count = count;
250 } else if (word_len <= 16) {
251 data_type = OMAP_DMA_DATA_TYPE_S16;
252 element_count = count >> 1;
253 } else /* word_len <= 32 */ {
254 data_type = OMAP_DMA_DATA_TYPE_S32;
255 element_count = count >> 2;
259 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
260 data_type, element_count, 1,
261 OMAP_DMA_SYNC_ELEMENT,
262 mcspi_dma->dma_tx_sync_dev, 0);
264 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
265 OMAP_DMA_AMODE_CONSTANT,
268 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
269 OMAP_DMA_AMODE_POST_INC,
274 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
275 data_type, element_count - 1, 1,
276 OMAP_DMA_SYNC_ELEMENT,
277 mcspi_dma->dma_rx_sync_dev, 1);
279 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
280 OMAP_DMA_AMODE_CONSTANT,
283 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
284 OMAP_DMA_AMODE_POST_INC,
289 omap_start_dma(mcspi_dma->dma_tx_channel);
290 omap2_mcspi_set_dma_req(spi, 0, 1);
294 omap_start_dma(mcspi_dma->dma_rx_channel);
295 omap2_mcspi_set_dma_req(spi, 1, 1);
299 wait_for_completion(&mcspi_dma->dma_tx_completion);
300 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
304 wait_for_completion(&mcspi_dma->dma_rx_completion);
305 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
306 omap2_mcspi_set_enable(spi, 0);
307 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
308 & OMAP2_MCSPI_CHSTAT_RXS)) {
311 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
313 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
314 else if (word_len <= 16)
315 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
316 else /* word_len <= 32 */
317 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
319 dev_err(&spi->dev, "DMA RX last word empty");
320 count -= (word_len <= 8) ? 1 :
321 (word_len <= 16) ? 2 :
322 /* word_len <= 32 */ 4;
324 omap2_mcspi_set_enable(spi, 1);
329 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
331 unsigned long timeout;
333 timeout = jiffies + msecs_to_jiffies(1000);
334 while (!(__raw_readl(reg) & bit)) {
335 if (time_after(jiffies, timeout))
343 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
345 struct omap2_mcspi *mcspi;
346 struct omap2_mcspi_cs *cs = spi->controller_state;
347 unsigned int count, c;
349 void __iomem *base = cs->base;
350 void __iomem *tx_reg;
351 void __iomem *rx_reg;
352 void __iomem *chstat_reg;
355 mcspi = spi_master_get_devdata(spi->master);
358 word_len = cs->word_len;
360 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
361 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
363 /* We store the pre-calculated register addresses on stack to speed
364 * up the transfer loop. */
365 tx_reg = base + OMAP2_MCSPI_TX0;
366 rx_reg = base + OMAP2_MCSPI_RX0;
367 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
379 if (mcspi_wait_for_reg_bit(chstat_reg,
380 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
381 dev_err(&spi->dev, "TXS timed out\n");
385 dev_dbg(&spi->dev, "write-%d %02x\n",
388 __raw_writel(*tx++, tx_reg);
391 if (mcspi_wait_for_reg_bit(chstat_reg,
392 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
393 dev_err(&spi->dev, "RXS timed out\n");
396 /* prevent last RX_ONLY read from triggering
397 * more word i/o: switch to rx+tx
399 if (c == 0 && tx == NULL)
400 mcspi_write_cs_reg(spi,
401 OMAP2_MCSPI_CHCONF0, l);
402 *rx++ = __raw_readl(rx_reg);
404 dev_dbg(&spi->dev, "read-%d %02x\n",
405 word_len, *(rx - 1));
409 } else if (word_len <= 16) {
418 if (mcspi_wait_for_reg_bit(chstat_reg,
419 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
420 dev_err(&spi->dev, "TXS timed out\n");
424 dev_dbg(&spi->dev, "write-%d %04x\n",
427 __raw_writel(*tx++, tx_reg);
430 if (mcspi_wait_for_reg_bit(chstat_reg,
431 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
432 dev_err(&spi->dev, "RXS timed out\n");
435 /* prevent last RX_ONLY read from triggering
436 * more word i/o: switch to rx+tx
438 if (c == 0 && tx == NULL)
439 mcspi_write_cs_reg(spi,
440 OMAP2_MCSPI_CHCONF0, l);
441 *rx++ = __raw_readl(rx_reg);
443 dev_dbg(&spi->dev, "read-%d %04x\n",
444 word_len, *(rx - 1));
448 } else if (word_len <= 32) {
457 if (mcspi_wait_for_reg_bit(chstat_reg,
458 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
459 dev_err(&spi->dev, "TXS timed out\n");
463 dev_dbg(&spi->dev, "write-%d %04x\n",
466 __raw_writel(*tx++, tx_reg);
469 if (mcspi_wait_for_reg_bit(chstat_reg,
470 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
471 dev_err(&spi->dev, "RXS timed out\n");
474 /* prevent last RX_ONLY read from triggering
475 * more word i/o: switch to rx+tx
477 if (c == 0 && tx == NULL)
478 mcspi_write_cs_reg(spi,
479 OMAP2_MCSPI_CHCONF0, l);
480 *rx++ = __raw_readl(rx_reg);
482 dev_dbg(&spi->dev, "read-%d %04x\n",
483 word_len, *(rx - 1));
489 /* for TX_ONLY mode, be sure all words have shifted out */
490 if (xfer->rx_buf == NULL) {
491 if (mcspi_wait_for_reg_bit(chstat_reg,
492 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
493 dev_err(&spi->dev, "TXS timed out\n");
494 } else if (mcspi_wait_for_reg_bit(chstat_reg,
495 OMAP2_MCSPI_CHSTAT_EOT) < 0)
496 dev_err(&spi->dev, "EOT timed out\n");
502 /* called only when no transfer is active to this device */
503 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
504 struct spi_transfer *t)
506 struct omap2_mcspi_cs *cs = spi->controller_state;
507 struct omap2_mcspi *mcspi;
509 u8 word_len = spi->bits_per_word;
511 mcspi = spi_master_get_devdata(spi->master);
513 if (t != NULL && t->bits_per_word)
514 word_len = t->bits_per_word;
516 cs->word_len = word_len;
518 if (spi->max_speed_hz) {
519 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
525 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
527 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
528 * REVISIT: this controller could support SPI_3WIRE mode.
530 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
531 l |= OMAP2_MCSPI_CHCONF_DPE0;
534 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
535 l |= (word_len - 1) << 7;
537 /* set chipselect polarity; manage with FORCE */
538 if (!(spi->mode & SPI_CS_HIGH))
539 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
541 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
543 /* set clock divisor */
544 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
547 /* set SPI mode 0..3 */
548 if (spi->mode & SPI_CPOL)
549 l |= OMAP2_MCSPI_CHCONF_POL;
551 l &= ~OMAP2_MCSPI_CHCONF_POL;
552 if (spi->mode & SPI_CPHA)
553 l |= OMAP2_MCSPI_CHCONF_PHA;
555 l &= ~OMAP2_MCSPI_CHCONF_PHA;
557 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
559 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
560 OMAP2_MCSPI_MAX_FREQ / (1 << div),
561 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
562 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
567 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
569 struct spi_device *spi = data;
570 struct omap2_mcspi *mcspi;
571 struct omap2_mcspi_dma *mcspi_dma;
573 mcspi = spi_master_get_devdata(spi->master);
574 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
576 complete(&mcspi_dma->dma_rx_completion);
578 /* We must disable the DMA RX request */
579 omap2_mcspi_set_dma_req(spi, 1, 0);
582 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
584 struct spi_device *spi = data;
585 struct omap2_mcspi *mcspi;
586 struct omap2_mcspi_dma *mcspi_dma;
588 mcspi = spi_master_get_devdata(spi->master);
589 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
591 complete(&mcspi_dma->dma_tx_completion);
593 /* We must disable the DMA TX request */
594 omap2_mcspi_set_dma_req(spi, 0, 0);
597 static int omap2_mcspi_request_dma(struct spi_device *spi)
599 struct spi_master *master = spi->master;
600 struct omap2_mcspi *mcspi;
601 struct omap2_mcspi_dma *mcspi_dma;
603 mcspi = spi_master_get_devdata(master);
604 mcspi_dma = mcspi->dma_channels + spi->chip_select;
606 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
607 omap2_mcspi_dma_rx_callback, spi,
608 &mcspi_dma->dma_rx_channel)) {
609 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
613 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
614 omap2_mcspi_dma_tx_callback, spi,
615 &mcspi_dma->dma_tx_channel)) {
616 omap_free_dma(mcspi_dma->dma_rx_channel);
617 mcspi_dma->dma_rx_channel = -1;
618 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
622 init_completion(&mcspi_dma->dma_rx_completion);
623 init_completion(&mcspi_dma->dma_tx_completion);
628 static int omap2_mcspi_setup(struct spi_device *spi)
631 struct omap2_mcspi *mcspi;
632 struct omap2_mcspi_dma *mcspi_dma;
633 struct omap2_mcspi_cs *cs = spi->controller_state;
635 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
636 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
641 mcspi = spi_master_get_devdata(spi->master);
642 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
645 cs = kzalloc(sizeof *cs, GFP_KERNEL);
648 cs->base = mcspi->base + spi->chip_select * 0x14;
649 cs->phys = mcspi->phys + spi->chip_select * 0x14;
650 spi->controller_state = cs;
653 if (mcspi_dma->dma_rx_channel == -1
654 || mcspi_dma->dma_tx_channel == -1) {
655 ret = omap2_mcspi_request_dma(spi);
660 clk_enable(mcspi->ick);
661 clk_enable(mcspi->fck);
662 ret = omap2_mcspi_setup_transfer(spi, NULL);
663 clk_disable(mcspi->fck);
664 clk_disable(mcspi->ick);
669 static void omap2_mcspi_cleanup(struct spi_device *spi)
671 struct omap2_mcspi *mcspi;
672 struct omap2_mcspi_dma *mcspi_dma;
674 mcspi = spi_master_get_devdata(spi->master);
675 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
677 kfree(spi->controller_state);
679 if (mcspi_dma->dma_rx_channel != -1) {
680 omap_free_dma(mcspi_dma->dma_rx_channel);
681 mcspi_dma->dma_rx_channel = -1;
683 if (mcspi_dma->dma_tx_channel != -1) {
684 omap_free_dma(mcspi_dma->dma_tx_channel);
685 mcspi_dma->dma_tx_channel = -1;
689 static void omap2_mcspi_work(struct work_struct *work)
691 struct omap2_mcspi *mcspi;
693 mcspi = container_of(work, struct omap2_mcspi, work);
694 spin_lock_irq(&mcspi->lock);
696 clk_enable(mcspi->ick);
697 clk_enable(mcspi->fck);
699 /* We only enable one channel at a time -- the one whose message is
700 * at the head of the queue -- although this controller would gladly
701 * arbitrate among multiple channels. This corresponds to "single
702 * channel" master mode. As a side effect, we need to manage the
703 * chipselect with the FORCE bit ... CS != channel enable.
705 while (!list_empty(&mcspi->msg_queue)) {
706 struct spi_message *m;
707 struct spi_device *spi;
708 struct spi_transfer *t = NULL;
710 struct omap2_mcspi_cs *cs;
711 int par_override = 0;
715 m = container_of(mcspi->msg_queue.next, struct spi_message,
718 list_del_init(&m->queue);
719 spin_unlock_irq(&mcspi->lock);
722 cs = spi->controller_state;
724 omap2_mcspi_set_enable(spi, 1);
725 list_for_each_entry(t, &m->transfers, transfer_list) {
726 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
730 if (par_override || t->speed_hz || t->bits_per_word) {
732 status = omap2_mcspi_setup_transfer(spi, t);
735 if (!t->speed_hz && !t->bits_per_word)
740 omap2_mcspi_force_cs(spi, 1);
744 chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
745 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
746 if (t->tx_buf == NULL)
747 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
748 else if (t->rx_buf == NULL)
749 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
750 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
755 /* RX_ONLY mode needs dummy data in TX reg */
756 if (t->tx_buf == NULL)
757 __raw_writel(0, cs->base
760 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
761 count = omap2_mcspi_txrx_dma(spi, t);
763 count = omap2_mcspi_txrx_pio(spi, t);
764 m->actual_length += count;
766 if (count != t->len) {
773 udelay(t->delay_usecs);
775 /* ignore the "leave it on after last xfer" hint */
777 omap2_mcspi_force_cs(spi, 0);
782 /* Restore defaults if they were overriden */
785 status = omap2_mcspi_setup_transfer(spi, NULL);
789 omap2_mcspi_force_cs(spi, 0);
791 omap2_mcspi_set_enable(spi, 0);
794 m->complete(m->context);
796 spin_lock_irq(&mcspi->lock);
799 clk_disable(mcspi->fck);
800 clk_disable(mcspi->ick);
802 spin_unlock_irq(&mcspi->lock);
805 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
807 struct omap2_mcspi *mcspi;
809 struct spi_transfer *t;
811 m->actual_length = 0;
814 /* reject invalid messages and transfers */
815 if (list_empty(&m->transfers) || !m->complete)
817 list_for_each_entry(t, &m->transfers, transfer_list) {
818 const void *tx_buf = t->tx_buf;
819 void *rx_buf = t->rx_buf;
820 unsigned len = t->len;
822 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
823 || (len && !(rx_buf || tx_buf))
824 || (t->bits_per_word &&
825 ( t->bits_per_word < 4
826 || t->bits_per_word > 32))) {
827 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
835 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
836 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
838 OMAP2_MCSPI_MAX_FREQ/(1<<16));
842 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
845 /* Do DMA mapping "early" for better error reporting and
846 * dcache use. Note that if dma_unmap_single() ever starts
847 * to do real work on ARM, we'd need to clean up mappings
848 * for previous transfers on *ALL* exits of this loop...
850 if (tx_buf != NULL) {
851 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
853 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
854 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
859 if (rx_buf != NULL) {
860 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
862 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
863 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
866 dma_unmap_single(NULL, t->tx_dma,
873 mcspi = spi_master_get_devdata(spi->master);
875 spin_lock_irqsave(&mcspi->lock, flags);
876 list_add_tail(&m->queue, &mcspi->msg_queue);
877 queue_work(omap2_mcspi_wq, &mcspi->work);
878 spin_unlock_irqrestore(&mcspi->lock, flags);
883 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
885 struct spi_master *master = mcspi->master;
888 clk_enable(mcspi->ick);
889 clk_enable(mcspi->fck);
891 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
892 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
894 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
895 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
897 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
898 OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
899 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
900 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
902 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
903 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
905 omap2_mcspi_set_master_mode(master);
907 clk_disable(mcspi->fck);
908 clk_disable(mcspi->ick);
912 static u8 __initdata spi1_rxdma_id [] = {
913 OMAP24XX_DMA_SPI1_RX0,
914 OMAP24XX_DMA_SPI1_RX1,
915 OMAP24XX_DMA_SPI1_RX2,
916 OMAP24XX_DMA_SPI1_RX3,
919 static u8 __initdata spi1_txdma_id [] = {
920 OMAP24XX_DMA_SPI1_TX0,
921 OMAP24XX_DMA_SPI1_TX1,
922 OMAP24XX_DMA_SPI1_TX2,
923 OMAP24XX_DMA_SPI1_TX3,
926 static u8 __initdata spi2_rxdma_id[] = {
927 OMAP24XX_DMA_SPI2_RX0,
928 OMAP24XX_DMA_SPI2_RX1,
931 static u8 __initdata spi2_txdma_id[] = {
932 OMAP24XX_DMA_SPI2_TX0,
933 OMAP24XX_DMA_SPI2_TX1,
936 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
937 static u8 __initdata spi3_rxdma_id[] = {
938 OMAP24XX_DMA_SPI3_RX0,
939 OMAP24XX_DMA_SPI3_RX1,
942 static u8 __initdata spi3_txdma_id[] = {
943 OMAP24XX_DMA_SPI3_TX0,
944 OMAP24XX_DMA_SPI3_TX1,
948 #ifdef CONFIG_ARCH_OMAP3
949 static u8 __initdata spi4_rxdma_id[] = {
950 OMAP34XX_DMA_SPI4_RX0,
953 static u8 __initdata spi4_txdma_id[] = {
954 OMAP34XX_DMA_SPI4_TX0,
958 static int __init omap2_mcspi_probe(struct platform_device *pdev)
960 struct spi_master *master;
961 struct omap2_mcspi *mcspi;
964 const u8 *rxdma_id, *txdma_id;
965 unsigned num_chipselect;
969 rxdma_id = spi1_rxdma_id;
970 txdma_id = spi1_txdma_id;
974 rxdma_id = spi2_rxdma_id;
975 txdma_id = spi2_txdma_id;
978 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
980 rxdma_id = spi3_rxdma_id;
981 txdma_id = spi3_txdma_id;
985 #ifdef CONFIG_ARCH_OMAP3
987 rxdma_id = spi4_rxdma_id;
988 txdma_id = spi4_txdma_id;
996 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
997 if (master == NULL) {
998 dev_dbg(&pdev->dev, "master allocation failed\n");
1002 /* the spi->mode bits understood by this driver: */
1003 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1006 master->bus_num = pdev->id;
1008 master->setup = omap2_mcspi_setup;
1009 master->transfer = omap2_mcspi_transfer;
1010 master->cleanup = omap2_mcspi_cleanup;
1011 master->num_chipselect = num_chipselect;
1013 dev_set_drvdata(&pdev->dev, master);
1015 mcspi = spi_master_get_devdata(master);
1016 mcspi->master = master;
1018 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1024 dev_name(&pdev->dev))) {
1029 mcspi->phys = r->start;
1030 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1032 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1037 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1039 spin_lock_init(&mcspi->lock);
1040 INIT_LIST_HEAD(&mcspi->msg_queue);
1042 mcspi->ick = clk_get(&pdev->dev, "ick");
1043 if (IS_ERR(mcspi->ick)) {
1044 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1045 status = PTR_ERR(mcspi->ick);
1048 mcspi->fck = clk_get(&pdev->dev, "fck");
1049 if (IS_ERR(mcspi->fck)) {
1050 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1051 status = PTR_ERR(mcspi->fck);
1055 mcspi->dma_channels = kcalloc(master->num_chipselect,
1056 sizeof(struct omap2_mcspi_dma),
1059 if (mcspi->dma_channels == NULL)
1062 for (i = 0; i < num_chipselect; i++) {
1063 mcspi->dma_channels[i].dma_rx_channel = -1;
1064 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1065 mcspi->dma_channels[i].dma_tx_channel = -1;
1066 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1069 if (omap2_mcspi_reset(mcspi) < 0)
1072 status = spi_register_master(master);
1079 kfree(mcspi->dma_channels);
1081 clk_put(mcspi->fck);
1083 clk_put(mcspi->ick);
1085 iounmap(mcspi->base);
1087 release_mem_region(r->start, (r->end - r->start) + 1);
1089 spi_master_put(master);
1093 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1095 struct spi_master *master;
1096 struct omap2_mcspi *mcspi;
1097 struct omap2_mcspi_dma *dma_channels;
1101 master = dev_get_drvdata(&pdev->dev);
1102 mcspi = spi_master_get_devdata(master);
1103 dma_channels = mcspi->dma_channels;
1105 clk_put(mcspi->fck);
1106 clk_put(mcspi->ick);
1108 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109 release_mem_region(r->start, (r->end - r->start) + 1);
1112 spi_unregister_master(master);
1114 kfree(dma_channels);
1119 /* work with hotplug and coldplug */
1120 MODULE_ALIAS("platform:omap2_mcspi");
1122 static struct platform_driver omap2_mcspi_driver = {
1124 .name = "omap2_mcspi",
1125 .owner = THIS_MODULE,
1127 .remove = __exit_p(omap2_mcspi_remove),
1131 static int __init omap2_mcspi_init(void)
1133 omap2_mcspi_wq = create_singlethread_workqueue(
1134 omap2_mcspi_driver.driver.name);
1135 if (omap2_mcspi_wq == NULL)
1137 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1139 subsys_initcall(omap2_mcspi_init);
1141 static void __exit omap2_mcspi_exit(void)
1143 platform_driver_unregister(&omap2_mcspi_driver);
1145 destroy_workqueue(omap2_mcspi_wq);
1147 module_exit(omap2_mcspi_exit);
1149 MODULE_LICENSE("GPL");