2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/dma-atmel.h>
26 #include <linux/gpio.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pm_runtime.h>
30 /* SPI register offsets */
33 #define SPI_RDR 0x0008
34 #define SPI_TDR 0x000c
36 #define SPI_IER 0x0014
37 #define SPI_IDR 0x0018
38 #define SPI_IMR 0x001c
39 #define SPI_CSR0 0x0030
40 #define SPI_CSR1 0x0034
41 #define SPI_CSR2 0x0038
42 #define SPI_CSR3 0x003c
43 #define SPI_FMR 0x0040
44 #define SPI_FLR 0x0044
45 #define SPI_VERSION 0x00fc
46 #define SPI_RPR 0x0100
47 #define SPI_RCR 0x0104
48 #define SPI_TPR 0x0108
49 #define SPI_TCR 0x010c
50 #define SPI_RNPR 0x0110
51 #define SPI_RNCR 0x0114
52 #define SPI_TNPR 0x0118
53 #define SPI_TNCR 0x011c
54 #define SPI_PTCR 0x0120
55 #define SPI_PTSR 0x0124
58 #define SPI_SPIEN_OFFSET 0
59 #define SPI_SPIEN_SIZE 1
60 #define SPI_SPIDIS_OFFSET 1
61 #define SPI_SPIDIS_SIZE 1
62 #define SPI_SWRST_OFFSET 7
63 #define SPI_SWRST_SIZE 1
64 #define SPI_LASTXFER_OFFSET 24
65 #define SPI_LASTXFER_SIZE 1
66 #define SPI_TXFCLR_OFFSET 16
67 #define SPI_TXFCLR_SIZE 1
68 #define SPI_RXFCLR_OFFSET 17
69 #define SPI_RXFCLR_SIZE 1
70 #define SPI_FIFOEN_OFFSET 30
71 #define SPI_FIFOEN_SIZE 1
72 #define SPI_FIFODIS_OFFSET 31
73 #define SPI_FIFODIS_SIZE 1
76 #define SPI_MSTR_OFFSET 0
77 #define SPI_MSTR_SIZE 1
78 #define SPI_PS_OFFSET 1
80 #define SPI_PCSDEC_OFFSET 2
81 #define SPI_PCSDEC_SIZE 1
82 #define SPI_FDIV_OFFSET 3
83 #define SPI_FDIV_SIZE 1
84 #define SPI_MODFDIS_OFFSET 4
85 #define SPI_MODFDIS_SIZE 1
86 #define SPI_WDRBT_OFFSET 5
87 #define SPI_WDRBT_SIZE 1
88 #define SPI_LLB_OFFSET 7
89 #define SPI_LLB_SIZE 1
90 #define SPI_PCS_OFFSET 16
91 #define SPI_PCS_SIZE 4
92 #define SPI_DLYBCS_OFFSET 24
93 #define SPI_DLYBCS_SIZE 8
95 /* Bitfields in RDR */
96 #define SPI_RD_OFFSET 0
97 #define SPI_RD_SIZE 16
99 /* Bitfields in TDR */
100 #define SPI_TD_OFFSET 0
101 #define SPI_TD_SIZE 16
103 /* Bitfields in SR */
104 #define SPI_RDRF_OFFSET 0
105 #define SPI_RDRF_SIZE 1
106 #define SPI_TDRE_OFFSET 1
107 #define SPI_TDRE_SIZE 1
108 #define SPI_MODF_OFFSET 2
109 #define SPI_MODF_SIZE 1
110 #define SPI_OVRES_OFFSET 3
111 #define SPI_OVRES_SIZE 1
112 #define SPI_ENDRX_OFFSET 4
113 #define SPI_ENDRX_SIZE 1
114 #define SPI_ENDTX_OFFSET 5
115 #define SPI_ENDTX_SIZE 1
116 #define SPI_RXBUFF_OFFSET 6
117 #define SPI_RXBUFF_SIZE 1
118 #define SPI_TXBUFE_OFFSET 7
119 #define SPI_TXBUFE_SIZE 1
120 #define SPI_NSSR_OFFSET 8
121 #define SPI_NSSR_SIZE 1
122 #define SPI_TXEMPTY_OFFSET 9
123 #define SPI_TXEMPTY_SIZE 1
124 #define SPI_SPIENS_OFFSET 16
125 #define SPI_SPIENS_SIZE 1
126 #define SPI_TXFEF_OFFSET 24
127 #define SPI_TXFEF_SIZE 1
128 #define SPI_TXFFF_OFFSET 25
129 #define SPI_TXFFF_SIZE 1
130 #define SPI_TXFTHF_OFFSET 26
131 #define SPI_TXFTHF_SIZE 1
132 #define SPI_RXFEF_OFFSET 27
133 #define SPI_RXFEF_SIZE 1
134 #define SPI_RXFFF_OFFSET 28
135 #define SPI_RXFFF_SIZE 1
136 #define SPI_RXFTHF_OFFSET 29
137 #define SPI_RXFTHF_SIZE 1
138 #define SPI_TXFPTEF_OFFSET 30
139 #define SPI_TXFPTEF_SIZE 1
140 #define SPI_RXFPTEF_OFFSET 31
141 #define SPI_RXFPTEF_SIZE 1
143 /* Bitfields in CSR0 */
144 #define SPI_CPOL_OFFSET 0
145 #define SPI_CPOL_SIZE 1
146 #define SPI_NCPHA_OFFSET 1
147 #define SPI_NCPHA_SIZE 1
148 #define SPI_CSAAT_OFFSET 3
149 #define SPI_CSAAT_SIZE 1
150 #define SPI_BITS_OFFSET 4
151 #define SPI_BITS_SIZE 4
152 #define SPI_SCBR_OFFSET 8
153 #define SPI_SCBR_SIZE 8
154 #define SPI_DLYBS_OFFSET 16
155 #define SPI_DLYBS_SIZE 8
156 #define SPI_DLYBCT_OFFSET 24
157 #define SPI_DLYBCT_SIZE 8
159 /* Bitfields in RCR */
160 #define SPI_RXCTR_OFFSET 0
161 #define SPI_RXCTR_SIZE 16
163 /* Bitfields in TCR */
164 #define SPI_TXCTR_OFFSET 0
165 #define SPI_TXCTR_SIZE 16
167 /* Bitfields in RNCR */
168 #define SPI_RXNCR_OFFSET 0
169 #define SPI_RXNCR_SIZE 16
171 /* Bitfields in TNCR */
172 #define SPI_TXNCR_OFFSET 0
173 #define SPI_TXNCR_SIZE 16
175 /* Bitfields in PTCR */
176 #define SPI_RXTEN_OFFSET 0
177 #define SPI_RXTEN_SIZE 1
178 #define SPI_RXTDIS_OFFSET 1
179 #define SPI_RXTDIS_SIZE 1
180 #define SPI_TXTEN_OFFSET 8
181 #define SPI_TXTEN_SIZE 1
182 #define SPI_TXTDIS_OFFSET 9
183 #define SPI_TXTDIS_SIZE 1
185 /* Bitfields in FMR */
186 #define SPI_TXRDYM_OFFSET 0
187 #define SPI_TXRDYM_SIZE 2
188 #define SPI_RXRDYM_OFFSET 4
189 #define SPI_RXRDYM_SIZE 2
190 #define SPI_TXFTHRES_OFFSET 16
191 #define SPI_TXFTHRES_SIZE 6
192 #define SPI_RXFTHRES_OFFSET 24
193 #define SPI_RXFTHRES_SIZE 6
195 /* Bitfields in FLR */
196 #define SPI_TXFL_OFFSET 0
197 #define SPI_TXFL_SIZE 6
198 #define SPI_RXFL_OFFSET 16
199 #define SPI_RXFL_SIZE 6
201 /* Constants for BITS */
202 #define SPI_BITS_8_BPT 0
203 #define SPI_BITS_9_BPT 1
204 #define SPI_BITS_10_BPT 2
205 #define SPI_BITS_11_BPT 3
206 #define SPI_BITS_12_BPT 4
207 #define SPI_BITS_13_BPT 5
208 #define SPI_BITS_14_BPT 6
209 #define SPI_BITS_15_BPT 7
210 #define SPI_BITS_16_BPT 8
211 #define SPI_ONE_DATA 0
212 #define SPI_TWO_DATA 1
213 #define SPI_FOUR_DATA 2
215 /* Bit manipulation macros */
216 #define SPI_BIT(name) \
217 (1 << SPI_##name##_OFFSET)
218 #define SPI_BF(name, value) \
219 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
220 #define SPI_BFEXT(name, value) \
221 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
222 #define SPI_BFINS(name, value, old) \
223 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
224 | SPI_BF(name, value))
226 /* Register access macros */
228 #define spi_readl(port, reg) \
229 __raw_readl((port)->regs + SPI_##reg)
230 #define spi_writel(port, reg, value) \
231 __raw_writel((value), (port)->regs + SPI_##reg)
233 #define spi_readw(port, reg) \
234 __raw_readw((port)->regs + SPI_##reg)
235 #define spi_writew(port, reg, value) \
236 __raw_writew((value), (port)->regs + SPI_##reg)
238 #define spi_readb(port, reg) \
239 __raw_readb((port)->regs + SPI_##reg)
240 #define spi_writeb(port, reg, value) \
241 __raw_writeb((value), (port)->regs + SPI_##reg)
243 #define spi_readl(port, reg) \
244 readl_relaxed((port)->regs + SPI_##reg)
245 #define spi_writel(port, reg, value) \
246 writel_relaxed((value), (port)->regs + SPI_##reg)
248 #define spi_readw(port, reg) \
249 readw_relaxed((port)->regs + SPI_##reg)
250 #define spi_writew(port, reg, value) \
251 writew_relaxed((value), (port)->regs + SPI_##reg)
253 #define spi_readb(port, reg) \
254 readb_relaxed((port)->regs + SPI_##reg)
255 #define spi_writeb(port, reg, value) \
256 writeb_relaxed((value), (port)->regs + SPI_##reg)
258 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
259 * cache operations; better heuristics consider wordsize and bitrate.
261 #define DMA_MIN_BYTES 16
263 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
265 #define AUTOSUSPEND_TIMEOUT 2000
267 struct atmel_spi_dma {
268 struct dma_chan *chan_rx;
269 struct dma_chan *chan_tx;
270 struct scatterlist sgrx;
271 struct scatterlist sgtx;
272 struct dma_async_tx_descriptor *data_desc_rx;
273 struct dma_async_tx_descriptor *data_desc_tx;
275 struct at_dma_slave dma_slave;
278 struct atmel_spi_caps {
281 bool has_dma_support;
285 * The core SPI transfer engine just talks to a register bank to set up
286 * DMA transfers; transfer queue progress is driven by IRQs. The clock
287 * framework provides the base clock, subdivided for each spi_device.
297 struct platform_device *pdev;
299 struct spi_transfer *current_transfer;
300 int current_remaining_bytes;
303 struct completion xfer_completion;
307 dma_addr_t buffer_dma;
309 struct atmel_spi_caps caps;
315 struct atmel_spi_dma dma;
323 /* Controller-specific per-slave state */
324 struct atmel_spi_device {
325 unsigned int npcs_pin;
329 #define BUFFER_SIZE PAGE_SIZE
330 #define INVALID_DMA_ADDRESS 0xffffffff
333 * Version 2 of the SPI controller has
335 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
336 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
338 * - SPI_CSRx.SBCR allows faster clocking
340 static bool atmel_spi_is_v2(struct atmel_spi *as)
342 return as->caps.is_spi2;
346 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
347 * they assume that spi slave device state will not change on deselect, so
348 * that automagic deselection is OK. ("NPCSx rises if no data is to be
349 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
350 * controllers have CSAAT and friends.
352 * Since the CSAAT functionality is a bit weird on newer controllers as
353 * well, we use GPIO to control nCSx pins on all controllers, updating
354 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
355 * support active-high chipselects despite the controller's belief that
356 * only active-low devices/systems exists.
358 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
359 * right when driven with GPIO. ("Mode Fault does not allow more than one
360 * Master on Chip Select 0.") No workaround exists for that ... so for
361 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
362 * and (c) will trigger that first erratum in some cases.
365 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
367 struct atmel_spi_device *asd = spi->controller_state;
368 unsigned active = spi->mode & SPI_CS_HIGH;
371 if (atmel_spi_is_v2(as)) {
372 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
373 /* For the low SPI version, there is a issue that PDC transfer
374 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
376 spi_writel(as, CSR0, asd->csr);
377 if (as->caps.has_wdrbt) {
379 SPI_BF(PCS, ~(0x01 << spi->chip_select))
385 SPI_BF(PCS, ~(0x01 << spi->chip_select))
390 mr = spi_readl(as, MR);
391 if (as->use_cs_gpios)
392 gpio_set_value(asd->npcs_pin, active);
394 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
398 /* Make sure clock polarity is correct */
399 for (i = 0; i < spi->master->num_chipselect; i++) {
400 csr = spi_readl(as, CSR0 + 4 * i);
401 if ((csr ^ cpol) & SPI_BIT(CPOL))
402 spi_writel(as, CSR0 + 4 * i,
403 csr ^ SPI_BIT(CPOL));
406 mr = spi_readl(as, MR);
407 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
408 if (as->use_cs_gpios && spi->chip_select != 0)
409 gpio_set_value(asd->npcs_pin, active);
410 spi_writel(as, MR, mr);
413 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
414 asd->npcs_pin, active ? " (high)" : "",
418 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
420 struct atmel_spi_device *asd = spi->controller_state;
421 unsigned active = spi->mode & SPI_CS_HIGH;
424 /* only deactivate *this* device; sometimes transfers to
425 * another device may be active when this routine is called.
427 mr = spi_readl(as, MR);
428 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
429 mr = SPI_BFINS(PCS, 0xf, mr);
430 spi_writel(as, MR, mr);
433 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
434 asd->npcs_pin, active ? " (low)" : "",
437 if (!as->use_cs_gpios)
438 spi_writel(as, CR, SPI_BIT(LASTXFER));
439 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
440 gpio_set_value(asd->npcs_pin, !active);
443 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
445 spin_lock_irqsave(&as->lock, as->flags);
448 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
450 spin_unlock_irqrestore(&as->lock, as->flags);
453 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
454 struct spi_transfer *xfer)
456 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
459 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
460 struct dma_slave_config *slave_config,
465 if (bits_per_word > 8) {
466 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
467 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
469 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
470 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
473 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
474 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
475 slave_config->src_maxburst = 1;
476 slave_config->dst_maxburst = 1;
477 slave_config->device_fc = false;
480 * This driver uses fixed peripheral select mode (PS bit set to '0' in
481 * the Mode Register).
482 * So according to the datasheet, when FIFOs are available (and
483 * enabled), the Transmit FIFO operates in Multiple Data Mode.
484 * In this mode, up to 2 data, not 4, can be written into the Transmit
485 * Data Register in a single access.
486 * However, the first data has to be written into the lowest 16 bits and
487 * the second data into the highest 16 bits of the Transmit
488 * Data Register. For 8bit data (the most frequent case), it would
489 * require to rework tx_buf so each data would actualy fit 16 bits.
490 * So we'd rather write only one data at the time. Hence the transmit
491 * path works the same whether FIFOs are available (and enabled) or not.
493 slave_config->direction = DMA_MEM_TO_DEV;
494 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
495 dev_err(&as->pdev->dev,
496 "failed to configure tx dma channel\n");
501 * This driver configures the spi controller for master mode (MSTR bit
502 * set to '1' in the Mode Register).
503 * So according to the datasheet, when FIFOs are available (and
504 * enabled), the Receive FIFO operates in Single Data Mode.
505 * So the receive path works the same whether FIFOs are available (and
508 slave_config->direction = DMA_DEV_TO_MEM;
509 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
510 dev_err(&as->pdev->dev,
511 "failed to configure rx dma channel\n");
518 static int atmel_spi_configure_dma(struct atmel_spi *as)
520 struct dma_slave_config slave_config;
521 struct device *dev = &as->pdev->dev;
526 dma_cap_set(DMA_SLAVE, mask);
528 as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
529 if (IS_ERR(as->dma.chan_tx)) {
530 err = PTR_ERR(as->dma.chan_tx);
531 if (err == -EPROBE_DEFER) {
532 dev_warn(dev, "no DMA channel available at the moment\n");
536 "DMA TX channel not available, SPI unable to use DMA\n");
542 * No reason to check EPROBE_DEFER here since we have already requested
543 * tx channel. If it fails here, it's for another reason.
545 as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
547 if (!as->dma.chan_rx) {
549 "DMA RX channel not available, SPI unable to use DMA\n");
554 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
558 dev_info(&as->pdev->dev,
559 "Using %s (tx) and %s (rx) for DMA transfers\n",
560 dma_chan_name(as->dma.chan_tx),
561 dma_chan_name(as->dma.chan_rx));
565 dma_release_channel(as->dma.chan_rx);
566 if (!IS_ERR(as->dma.chan_tx))
567 dma_release_channel(as->dma.chan_tx);
571 static void atmel_spi_stop_dma(struct atmel_spi *as)
574 dmaengine_terminate_all(as->dma.chan_rx);
576 dmaengine_terminate_all(as->dma.chan_tx);
579 static void atmel_spi_release_dma(struct atmel_spi *as)
582 dma_release_channel(as->dma.chan_rx);
584 dma_release_channel(as->dma.chan_tx);
587 /* This function is called by the DMA driver from tasklet context */
588 static void dma_callback(void *data)
590 struct spi_master *master = data;
591 struct atmel_spi *as = spi_master_get_devdata(master);
593 complete(&as->xfer_completion);
597 * Next transfer using PIO without FIFO.
599 static void atmel_spi_next_xfer_single(struct spi_master *master,
600 struct spi_transfer *xfer)
602 struct atmel_spi *as = spi_master_get_devdata(master);
603 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
605 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
607 /* Make sure data is not remaining in RDR */
609 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
615 if (xfer->bits_per_word > 8)
616 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
618 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
620 spi_writel(as, TDR, 0);
623 dev_dbg(master->dev.parent,
624 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
625 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
626 xfer->bits_per_word);
628 /* Enable relevant interrupts */
629 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
633 * Next transfer using PIO with FIFO.
635 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
636 struct spi_transfer *xfer)
638 struct atmel_spi *as = spi_master_get_devdata(master);
639 u32 current_remaining_data, num_data;
640 u32 offset = xfer->len - as->current_remaining_bytes;
641 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
642 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
646 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
648 /* Compute the number of data to transfer in the current iteration */
649 current_remaining_data = ((xfer->bits_per_word > 8) ?
650 ((u32)as->current_remaining_bytes >> 1) :
651 (u32)as->current_remaining_bytes);
652 num_data = min(current_remaining_data, as->fifo_size);
654 /* Flush RX and TX FIFOs */
655 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
656 while (spi_readl(as, FLR))
659 /* Set RX FIFO Threshold to the number of data to transfer */
660 fifomr = spi_readl(as, FMR);
661 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
663 /* Clear FIFO flags in the Status Register, especially RXFTHF */
664 (void)spi_readl(as, SR);
667 while (num_data >= 2) {
669 if (xfer->bits_per_word > 8) {
681 spi_writel(as, TDR, (td1 << 16) | td0);
687 if (xfer->bits_per_word > 8)
695 spi_writew(as, TDR, td0);
699 dev_dbg(master->dev.parent,
700 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
701 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
702 xfer->bits_per_word);
705 * Enable RX FIFO Threshold Flag interrupt to be notified about
706 * transfer completion.
708 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
712 * Next transfer using PIO.
714 static void atmel_spi_next_xfer_pio(struct spi_master *master,
715 struct spi_transfer *xfer)
717 struct atmel_spi *as = spi_master_get_devdata(master);
720 atmel_spi_next_xfer_fifo(master, xfer);
722 atmel_spi_next_xfer_single(master, xfer);
726 * Submit next transfer for DMA.
728 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
729 struct spi_transfer *xfer,
732 struct atmel_spi *as = spi_master_get_devdata(master);
733 struct dma_chan *rxchan = as->dma.chan_rx;
734 struct dma_chan *txchan = as->dma.chan_tx;
735 struct dma_async_tx_descriptor *rxdesc;
736 struct dma_async_tx_descriptor *txdesc;
737 struct dma_slave_config slave_config;
741 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
743 /* Check that the channels are available */
744 if (!rxchan || !txchan)
747 /* release lock for DMA operations */
748 atmel_spi_unlock(as);
750 /* prepare the RX dma transfer */
751 sg_init_table(&as->dma.sgrx, 1);
753 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
755 as->dma.sgrx.dma_address = as->buffer_dma;
756 if (len > BUFFER_SIZE)
760 /* prepare the TX dma transfer */
761 sg_init_table(&as->dma.sgtx, 1);
763 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
765 as->dma.sgtx.dma_address = as->buffer_dma;
766 if (len > BUFFER_SIZE)
768 memset(as->buffer, 0, len);
771 sg_dma_len(&as->dma.sgtx) = len;
772 sg_dma_len(&as->dma.sgrx) = len;
776 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
779 /* Send both scatterlists */
780 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
782 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
786 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
788 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
792 dev_dbg(master->dev.parent,
793 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
794 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
795 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
797 /* Enable relevant interrupts */
798 spi_writel(as, IER, SPI_BIT(OVRES));
800 /* Put the callback on the RX transfer only, that should finish last */
801 rxdesc->callback = dma_callback;
802 rxdesc->callback_param = master;
804 /* Submit and fire RX and TX with TX last so we're ready to read! */
805 cookie = rxdesc->tx_submit(rxdesc);
806 if (dma_submit_error(cookie))
808 cookie = txdesc->tx_submit(txdesc);
809 if (dma_submit_error(cookie))
811 rxchan->device->device_issue_pending(rxchan);
812 txchan->device->device_issue_pending(txchan);
819 spi_writel(as, IDR, SPI_BIT(OVRES));
820 atmel_spi_stop_dma(as);
826 static void atmel_spi_next_xfer_data(struct spi_master *master,
827 struct spi_transfer *xfer,
832 struct atmel_spi *as = spi_master_get_devdata(master);
835 /* use scratch buffer only when rx or tx data is unspecified */
837 *rx_dma = xfer->rx_dma + xfer->len - *plen;
839 *rx_dma = as->buffer_dma;
840 if (len > BUFFER_SIZE)
845 *tx_dma = xfer->tx_dma + xfer->len - *plen;
847 *tx_dma = as->buffer_dma;
848 if (len > BUFFER_SIZE)
850 memset(as->buffer, 0, len);
851 dma_sync_single_for_device(&as->pdev->dev,
852 as->buffer_dma, len, DMA_TO_DEVICE);
858 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
859 struct spi_device *spi,
860 struct spi_transfer *xfer)
863 unsigned long bus_hz;
865 /* v1 chips start out at half the peripheral bus speed. */
866 bus_hz = clk_get_rate(as->clk);
867 if (!atmel_spi_is_v2(as))
871 * Calculate the lowest divider that satisfies the
872 * constraint, assuming div32/fdiv/mbz == 0.
874 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
877 * If the resulting divider doesn't fit into the
878 * register bitfield, we can't satisfy the constraint.
880 if (scbr >= (1 << SPI_SCBR_SIZE)) {
882 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
883 xfer->speed_hz, scbr, bus_hz/255);
888 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
889 xfer->speed_hz, scbr, bus_hz);
892 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
893 csr = SPI_BFINS(SCBR, scbr, csr);
894 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
900 * Submit next transfer for PDC.
901 * lock is held, spi irq is blocked
903 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
904 struct spi_message *msg,
905 struct spi_transfer *xfer)
907 struct atmel_spi *as = spi_master_get_devdata(master);
909 dma_addr_t tx_dma, rx_dma;
911 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
913 len = as->current_remaining_bytes;
914 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
915 as->current_remaining_bytes -= len;
917 spi_writel(as, RPR, rx_dma);
918 spi_writel(as, TPR, tx_dma);
920 if (msg->spi->bits_per_word > 8)
922 spi_writel(as, RCR, len);
923 spi_writel(as, TCR, len);
925 dev_dbg(&msg->spi->dev,
926 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
927 xfer, xfer->len, xfer->tx_buf,
928 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
929 (unsigned long long)xfer->rx_dma);
931 if (as->current_remaining_bytes) {
932 len = as->current_remaining_bytes;
933 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
934 as->current_remaining_bytes -= len;
936 spi_writel(as, RNPR, rx_dma);
937 spi_writel(as, TNPR, tx_dma);
939 if (msg->spi->bits_per_word > 8)
941 spi_writel(as, RNCR, len);
942 spi_writel(as, TNCR, len);
944 dev_dbg(&msg->spi->dev,
945 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
946 xfer, xfer->len, xfer->tx_buf,
947 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
948 (unsigned long long)xfer->rx_dma);
951 /* REVISIT: We're waiting for RXBUFF before we start the next
952 * transfer because we need to handle some difficult timing
953 * issues otherwise. If we wait for TXBUFE in one transfer and
954 * then starts waiting for RXBUFF in the next, it's difficult
955 * to tell the difference between the RXBUFF interrupt we're
956 * actually waiting for and the RXBUFF interrupt of the
959 * It should be doable, though. Just not now...
961 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
962 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
966 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
967 * - The buffer is either valid for CPU access, else NULL
968 * - If the buffer is valid, so is its DMA address
970 * This driver manages the dma address unless message->is_dma_mapped.
973 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
975 struct device *dev = &as->pdev->dev;
977 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
979 /* tx_buf is a const void* where we need a void * for the dma
981 void *nonconst_tx = (void *)xfer->tx_buf;
983 xfer->tx_dma = dma_map_single(dev,
984 nonconst_tx, xfer->len,
986 if (dma_mapping_error(dev, xfer->tx_dma))
990 xfer->rx_dma = dma_map_single(dev,
991 xfer->rx_buf, xfer->len,
993 if (dma_mapping_error(dev, xfer->rx_dma)) {
995 dma_unmap_single(dev,
996 xfer->tx_dma, xfer->len,
1004 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
1005 struct spi_transfer *xfer)
1007 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
1008 dma_unmap_single(master->dev.parent, xfer->tx_dma,
1009 xfer->len, DMA_TO_DEVICE);
1010 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
1011 dma_unmap_single(master->dev.parent, xfer->rx_dma,
1012 xfer->len, DMA_FROM_DEVICE);
1015 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1017 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1021 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1025 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
1028 if (xfer->bits_per_word > 8) {
1029 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1030 *rxp16 = spi_readl(as, RDR);
1032 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1033 *rxp = spi_readl(as, RDR);
1038 if (xfer->bits_per_word > 8) {
1039 if (as->current_remaining_bytes > 2)
1040 as->current_remaining_bytes -= 2;
1042 as->current_remaining_bytes = 0;
1044 as->current_remaining_bytes--;
1049 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1051 u32 fifolr = spi_readl(as, FLR);
1052 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1053 u32 offset = xfer->len - as->current_remaining_bytes;
1054 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1055 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1056 u16 rd; /* RD field is the lowest 16 bits of RDR */
1058 /* Update the number of remaining bytes to transfer */
1059 num_bytes = ((xfer->bits_per_word > 8) ?
1063 if (as->current_remaining_bytes > num_bytes)
1064 as->current_remaining_bytes -= num_bytes;
1066 as->current_remaining_bytes = 0;
1068 /* Handle odd number of bytes when data are more than 8bit width */
1069 if (xfer->bits_per_word > 8)
1070 as->current_remaining_bytes &= ~0x1;
1074 rd = spi_readl(as, RDR);
1076 if (xfer->bits_per_word > 8)
1087 * Must update "current_remaining_bytes" to keep track of data
1091 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1094 atmel_spi_pump_fifo_data(as, xfer);
1096 atmel_spi_pump_single_data(as, xfer);
1101 * No need for locking in this Interrupt handler: done_status is the
1102 * only information modified.
1105 atmel_spi_pio_interrupt(int irq, void *dev_id)
1107 struct spi_master *master = dev_id;
1108 struct atmel_spi *as = spi_master_get_devdata(master);
1109 u32 status, pending, imr;
1110 struct spi_transfer *xfer;
1113 imr = spi_readl(as, IMR);
1114 status = spi_readl(as, SR);
1115 pending = status & imr;
1117 if (pending & SPI_BIT(OVRES)) {
1119 spi_writel(as, IDR, SPI_BIT(OVRES));
1120 dev_warn(master->dev.parent, "overrun\n");
1123 * When we get an overrun, we disregard the current
1124 * transfer. Data will not be copied back from any
1125 * bounce buffer and msg->actual_len will not be
1126 * updated with the last xfer.
1128 * We will also not process any remaning transfers in
1131 as->done_status = -EIO;
1134 /* Clear any overrun happening while cleaning up */
1137 complete(&as->xfer_completion);
1139 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1142 if (as->current_remaining_bytes) {
1144 xfer = as->current_transfer;
1145 atmel_spi_pump_pio_data(as, xfer);
1146 if (!as->current_remaining_bytes)
1147 spi_writel(as, IDR, pending);
1149 complete(&as->xfer_completion);
1152 atmel_spi_unlock(as);
1154 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1156 spi_writel(as, IDR, pending);
1163 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1165 struct spi_master *master = dev_id;
1166 struct atmel_spi *as = spi_master_get_devdata(master);
1167 u32 status, pending, imr;
1170 imr = spi_readl(as, IMR);
1171 status = spi_readl(as, SR);
1172 pending = status & imr;
1174 if (pending & SPI_BIT(OVRES)) {
1178 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1181 /* Clear any overrun happening while cleaning up */
1184 as->done_status = -EIO;
1186 complete(&as->xfer_completion);
1188 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1191 spi_writel(as, IDR, pending);
1193 complete(&as->xfer_completion);
1199 static int atmel_spi_setup(struct spi_device *spi)
1201 struct atmel_spi *as;
1202 struct atmel_spi_device *asd;
1204 unsigned int bits = spi->bits_per_word;
1205 unsigned int npcs_pin;
1208 as = spi_master_get_devdata(spi->master);
1210 /* see notes above re chipselect */
1211 if (!atmel_spi_is_v2(as)
1212 && spi->chip_select == 0
1213 && (spi->mode & SPI_CS_HIGH)) {
1214 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1218 csr = SPI_BF(BITS, bits - 8);
1219 if (spi->mode & SPI_CPOL)
1220 csr |= SPI_BIT(CPOL);
1221 if (!(spi->mode & SPI_CPHA))
1222 csr |= SPI_BIT(NCPHA);
1223 if (!as->use_cs_gpios)
1224 csr |= SPI_BIT(CSAAT);
1226 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1228 * DLYBCT would add delays between words, slowing down transfers.
1229 * It could potentially be useful to cope with DMA bottlenecks, but
1230 * in those cases it's probably best to just use a lower bitrate.
1232 csr |= SPI_BF(DLYBS, 0);
1233 csr |= SPI_BF(DLYBCT, 0);
1235 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1236 npcs_pin = (unsigned long)spi->controller_data;
1238 if (!as->use_cs_gpios)
1239 npcs_pin = spi->chip_select;
1240 else if (gpio_is_valid(spi->cs_gpio))
1241 npcs_pin = spi->cs_gpio;
1243 asd = spi->controller_state;
1245 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1249 if (as->use_cs_gpios) {
1250 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1256 gpio_direction_output(npcs_pin,
1257 !(spi->mode & SPI_CS_HIGH));
1260 asd->npcs_pin = npcs_pin;
1261 spi->controller_state = asd;
1267 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1268 bits, spi->mode, spi->chip_select, csr);
1270 if (!atmel_spi_is_v2(as))
1271 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1276 static int atmel_spi_one_transfer(struct spi_master *master,
1277 struct spi_message *msg,
1278 struct spi_transfer *xfer)
1280 struct atmel_spi *as;
1281 struct spi_device *spi = msg->spi;
1284 struct atmel_spi_device *asd;
1287 unsigned long dma_timeout;
1289 as = spi_master_get_devdata(master);
1291 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1292 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1296 asd = spi->controller_state;
1297 bits = (asd->csr >> 4) & 0xf;
1298 if (bits != xfer->bits_per_word - 8) {
1300 "you can't yet change bits_per_word in transfers\n");
1301 return -ENOPROTOOPT;
1305 * DMA map early, for performance (empties dcache ASAP) and
1306 * better fault reporting.
1308 if ((!msg->is_dma_mapped)
1309 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1310 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1314 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1316 as->done_status = 0;
1317 as->current_transfer = xfer;
1318 as->current_remaining_bytes = xfer->len;
1319 while (as->current_remaining_bytes) {
1320 reinit_completion(&as->xfer_completion);
1323 atmel_spi_pdc_next_xfer(master, msg, xfer);
1324 } else if (atmel_spi_use_dma(as, xfer)) {
1325 len = as->current_remaining_bytes;
1326 ret = atmel_spi_next_xfer_dma_submit(master,
1330 "unable to use DMA, fallback to PIO\n");
1331 atmel_spi_next_xfer_pio(master, xfer);
1333 as->current_remaining_bytes -= len;
1334 if (as->current_remaining_bytes < 0)
1335 as->current_remaining_bytes = 0;
1338 atmel_spi_next_xfer_pio(master, xfer);
1341 /* interrupts are disabled, so free the lock for schedule */
1342 atmel_spi_unlock(as);
1343 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1346 if (WARN_ON(dma_timeout == 0)) {
1347 dev_err(&spi->dev, "spi transfer timeout\n");
1348 as->done_status = -EIO;
1351 if (as->done_status)
1355 if (as->done_status) {
1357 dev_warn(master->dev.parent,
1358 "overrun (%u/%u remaining)\n",
1359 spi_readl(as, TCR), spi_readl(as, RCR));
1362 * Clean up DMA registers and make sure the data
1363 * registers are empty.
1365 spi_writel(as, RNCR, 0);
1366 spi_writel(as, TNCR, 0);
1367 spi_writel(as, RCR, 0);
1368 spi_writel(as, TCR, 0);
1369 for (timeout = 1000; timeout; timeout--)
1370 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1373 dev_warn(master->dev.parent,
1374 "timeout waiting for TXEMPTY");
1375 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1378 /* Clear any overrun happening while cleaning up */
1381 } else if (atmel_spi_use_dma(as, xfer)) {
1382 atmel_spi_stop_dma(as);
1385 if (!msg->is_dma_mapped
1386 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1387 atmel_spi_dma_unmap_xfer(master, xfer);
1392 /* only update length if no error */
1393 msg->actual_length += xfer->len;
1396 if (!msg->is_dma_mapped
1397 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1398 atmel_spi_dma_unmap_xfer(master, xfer);
1400 if (xfer->delay_usecs)
1401 udelay(xfer->delay_usecs);
1403 if (xfer->cs_change) {
1404 if (list_is_last(&xfer->transfer_list,
1408 as->cs_active = !as->cs_active;
1410 cs_activate(as, msg->spi);
1412 cs_deactivate(as, msg->spi);
1419 static int atmel_spi_transfer_one_message(struct spi_master *master,
1420 struct spi_message *msg)
1422 struct atmel_spi *as;
1423 struct spi_transfer *xfer;
1424 struct spi_device *spi = msg->spi;
1427 as = spi_master_get_devdata(master);
1429 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1430 msg, dev_name(&spi->dev));
1433 cs_activate(as, spi);
1435 as->cs_active = true;
1436 as->keep_cs = false;
1439 msg->actual_length = 0;
1441 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1442 ret = atmel_spi_one_transfer(master, msg, xfer);
1448 atmel_spi_disable_pdc_transfer(as);
1450 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1452 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1454 xfer->tx_buf, &xfer->tx_dma,
1455 xfer->rx_buf, &xfer->rx_dma);
1460 cs_deactivate(as, msg->spi);
1462 atmel_spi_unlock(as);
1464 msg->status = as->done_status;
1465 spi_finalize_current_message(spi->master);
1470 static void atmel_spi_cleanup(struct spi_device *spi)
1472 struct atmel_spi_device *asd = spi->controller_state;
1473 unsigned gpio = (unsigned long) spi->controller_data;
1478 spi->controller_state = NULL;
1483 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1485 return spi_readl(as, VERSION) & 0x00000fff;
1488 static void atmel_get_caps(struct atmel_spi *as)
1490 unsigned int version;
1492 version = atmel_get_version(as);
1493 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1495 as->caps.is_spi2 = version > 0x121;
1496 as->caps.has_wdrbt = version >= 0x210;
1497 as->caps.has_dma_support = version >= 0x212;
1500 /*-------------------------------------------------------------------------*/
1502 static int atmel_spi_probe(struct platform_device *pdev)
1504 struct resource *regs;
1508 struct spi_master *master;
1509 struct atmel_spi *as;
1511 /* Select default pin state */
1512 pinctrl_pm_select_default_state(&pdev->dev);
1514 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1518 irq = platform_get_irq(pdev, 0);
1522 clk = devm_clk_get(&pdev->dev, "spi_clk");
1524 return PTR_ERR(clk);
1526 /* setup spi core then atmel-specific driver state */
1528 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1532 /* the spi->mode bits understood by this driver: */
1533 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1534 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1535 master->dev.of_node = pdev->dev.of_node;
1536 master->bus_num = pdev->id;
1537 master->num_chipselect = master->dev.of_node ? 0 : 4;
1538 master->setup = atmel_spi_setup;
1539 master->transfer_one_message = atmel_spi_transfer_one_message;
1540 master->cleanup = atmel_spi_cleanup;
1541 master->auto_runtime_pm = true;
1542 platform_set_drvdata(pdev, master);
1544 as = spi_master_get_devdata(master);
1547 * Scratch buffer is used for throwaway rx and tx data.
1548 * It's coherent to minimize dcache pollution.
1550 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1551 &as->buffer_dma, GFP_KERNEL);
1555 spin_lock_init(&as->lock);
1558 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1559 if (IS_ERR(as->regs)) {
1560 ret = PTR_ERR(as->regs);
1561 goto out_free_buffer;
1563 as->phybase = regs->start;
1567 init_completion(&as->xfer_completion);
1571 as->use_cs_gpios = true;
1572 if (atmel_spi_is_v2(as) &&
1573 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1574 as->use_cs_gpios = false;
1575 master->num_chipselect = 4;
1578 as->use_dma = false;
1579 as->use_pdc = false;
1580 if (as->caps.has_dma_support) {
1581 ret = atmel_spi_configure_dma(as);
1584 else if (ret == -EPROBE_DEFER)
1590 if (as->caps.has_dma_support && !as->use_dma)
1591 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1594 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1595 0, dev_name(&pdev->dev), master);
1597 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1598 0, dev_name(&pdev->dev), master);
1601 goto out_unmap_regs;
1603 /* Initialize the hardware */
1604 ret = clk_prepare_enable(clk);
1607 spi_writel(as, CR, SPI_BIT(SWRST));
1608 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1609 if (as->caps.has_wdrbt) {
1610 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1613 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1617 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1618 spi_writel(as, CR, SPI_BIT(SPIEN));
1621 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1623 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1624 spi_writel(as, CR, SPI_BIT(FIFOEN));
1628 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1629 (unsigned long)regs->start, irq);
1631 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1632 pm_runtime_use_autosuspend(&pdev->dev);
1633 pm_runtime_set_active(&pdev->dev);
1634 pm_runtime_enable(&pdev->dev);
1636 ret = devm_spi_register_master(&pdev->dev, master);
1643 pm_runtime_disable(&pdev->dev);
1644 pm_runtime_set_suspended(&pdev->dev);
1647 atmel_spi_release_dma(as);
1649 spi_writel(as, CR, SPI_BIT(SWRST));
1650 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1651 clk_disable_unprepare(clk);
1655 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1658 spi_master_put(master);
1662 static int atmel_spi_remove(struct platform_device *pdev)
1664 struct spi_master *master = platform_get_drvdata(pdev);
1665 struct atmel_spi *as = spi_master_get_devdata(master);
1667 pm_runtime_get_sync(&pdev->dev);
1669 /* reset the hardware and block queue progress */
1670 spin_lock_irq(&as->lock);
1672 atmel_spi_stop_dma(as);
1673 atmel_spi_release_dma(as);
1676 spi_writel(as, CR, SPI_BIT(SWRST));
1677 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1679 spin_unlock_irq(&as->lock);
1681 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1684 clk_disable_unprepare(as->clk);
1686 pm_runtime_put_noidle(&pdev->dev);
1687 pm_runtime_disable(&pdev->dev);
1693 static int atmel_spi_runtime_suspend(struct device *dev)
1695 struct spi_master *master = dev_get_drvdata(dev);
1696 struct atmel_spi *as = spi_master_get_devdata(master);
1698 clk_disable_unprepare(as->clk);
1699 pinctrl_pm_select_sleep_state(dev);
1704 static int atmel_spi_runtime_resume(struct device *dev)
1706 struct spi_master *master = dev_get_drvdata(dev);
1707 struct atmel_spi *as = spi_master_get_devdata(master);
1709 pinctrl_pm_select_default_state(dev);
1711 return clk_prepare_enable(as->clk);
1714 #ifdef CONFIG_PM_SLEEP
1715 static int atmel_spi_suspend(struct device *dev)
1717 struct spi_master *master = dev_get_drvdata(dev);
1720 /* Stop the queue running */
1721 ret = spi_master_suspend(master);
1723 dev_warn(dev, "cannot suspend master\n");
1727 if (!pm_runtime_suspended(dev))
1728 atmel_spi_runtime_suspend(dev);
1733 static int atmel_spi_resume(struct device *dev)
1735 struct spi_master *master = dev_get_drvdata(dev);
1738 if (!pm_runtime_suspended(dev)) {
1739 ret = atmel_spi_runtime_resume(dev);
1744 /* Start the queue running */
1745 ret = spi_master_resume(master);
1747 dev_err(dev, "problem starting queue (%d)\n", ret);
1753 static const struct dev_pm_ops atmel_spi_pm_ops = {
1754 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1755 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1756 atmel_spi_runtime_resume, NULL)
1758 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1760 #define ATMEL_SPI_PM_OPS NULL
1763 #if defined(CONFIG_OF)
1764 static const struct of_device_id atmel_spi_dt_ids[] = {
1765 { .compatible = "atmel,at91rm9200-spi" },
1769 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1772 static struct platform_driver atmel_spi_driver = {
1774 .name = "atmel_spi",
1775 .pm = ATMEL_SPI_PM_OPS,
1776 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1778 .probe = atmel_spi_probe,
1779 .remove = atmel_spi_remove,
1781 module_platform_driver(atmel_spi_driver);
1783 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1784 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1785 MODULE_LICENSE("GPL");
1786 MODULE_ALIAS("platform:atmel_spi");