2 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
4 * the driver does not rely on the native chipselects at all
5 * but only uses the gpio type chipselects
7 * Based on: spi-bcm2835.c
9 * Copyright (C) 2015 Martin Sperl
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
31 #include <linux/of_address.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_irq.h>
35 #include <linux/regmap.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spinlock.h>
40 * spi register defines
42 * note there is garbage in the "official" documentation,
43 * so some data is taken from the file:
44 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
46 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
49 /* SPI register offsets */
50 #define BCM2835_AUX_SPI_CNTL0 0x00
51 #define BCM2835_AUX_SPI_CNTL1 0x04
52 #define BCM2835_AUX_SPI_STAT 0x08
53 #define BCM2835_AUX_SPI_PEEK 0x0C
54 #define BCM2835_AUX_SPI_IO 0x20
55 #define BCM2835_AUX_SPI_TXHOLD 0x30
57 /* Bitfields in CNTL0 */
58 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
61 #define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
66 #define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
67 #define BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400
68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
69 #define BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100
70 #define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
74 /* Bitfields in CNTL1 */
75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
76 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000080
77 #define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000040
78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
81 /* Bitfields in STAT */
82 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
83 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
84 #define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
86 #define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
88 #define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
89 #define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US 30
93 #define BCM2835_AUX_SPI_POLLING_JIFFIES 2
95 #define BCM2835_AUX_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
98 struct bcm2835aux_spi {
110 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
112 return readl(bs->regs + reg);
115 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
118 writel(val, bs->regs + reg);
121 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
124 int count = min(bs->rx_len, 3);
126 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
130 *bs->rx_buf++ = (data >> 24) & 0xff;
133 *bs->rx_buf++ = (data >> 16) & 0xff;
136 *bs->rx_buf++ = (data >> 8) & 0xff;
139 *bs->rx_buf++ = (data >> 0) & 0xff;
140 /* fallthrough - no default */
144 bs->pending -= count;
147 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
154 /* gather up to 3 bytes to write to the FIFO */
155 count = min(bs->tx_len, 3);
157 for (i = 0; i < count; i++) {
158 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
159 data |= byte << (8 * (2 - i));
162 /* and set the variable bit-length */
163 data |= (count * 8) << 24;
165 /* and decrement length */
167 bs->pending += count;
169 /* write to the correct TX-register */
171 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
173 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
176 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
178 /* disable spi clearing fifo and interrupts */
179 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
180 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
181 BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
184 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
186 struct spi_master *master = dev_id;
187 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
188 irqreturn_t ret = IRQ_NONE;
190 /* check if we have data to read */
192 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
193 BCM2835_AUX_SPI_STAT_RX_EMPTY))) {
194 bcm2835aux_rd_fifo(bs);
198 /* check if we have data to write */
200 (bs->pending < 12) &&
201 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
202 BCM2835_AUX_SPI_STAT_TX_FULL))) {
203 bcm2835aux_wr_fifo(bs);
207 /* and check if we have reached "done" */
209 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
210 BCM2835_AUX_SPI_STAT_BUSY))) {
211 bcm2835aux_rd_fifo(bs);
216 /* disable tx fifo empty interrupt */
217 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
218 BCM2835_AUX_SPI_CNTL1_IDLE);
221 /* and if rx_len is 0 then wake up completion and disable spi */
223 bcm2835aux_spi_reset_hw(bs);
224 complete(&master->xfer_completion);
231 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
232 struct spi_device *spi,
233 struct spi_transfer *tfr)
235 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
237 /* enable interrupts */
238 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
239 BCM2835_AUX_SPI_CNTL1_TXEMPTY |
240 BCM2835_AUX_SPI_CNTL1_IDLE);
242 /* and wait for finish... */
246 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
247 struct spi_device *spi,
248 struct spi_transfer *tfr)
250 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
252 /* fill in registers and fifos before enabling interrupts */
253 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
254 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
256 /* fill in tx fifo with data before enabling interrupts */
257 while ((bs->tx_len) &&
258 (bs->pending < 12) &&
259 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
260 BCM2835_AUX_SPI_STAT_TX_FULL))) {
261 bcm2835aux_wr_fifo(bs);
264 /* now run the interrupt mode */
265 return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
268 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
269 struct spi_device *spi,
270 struct spi_transfer *tfr)
272 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
273 unsigned long timeout;
277 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
278 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
280 /* set the timeout */
281 timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;
283 /* loop until finished the transfer */
286 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
288 /* fill in tx fifo with remaining data */
289 if ((bs->tx_len) && (!(stat & BCM2835_AUX_SPI_STAT_TX_FULL))) {
290 bcm2835aux_wr_fifo(bs);
294 /* read data from fifo for both cases */
295 if (!(stat & BCM2835_AUX_SPI_STAT_RX_EMPTY)) {
296 bcm2835aux_rd_fifo(bs);
299 if (!(stat & BCM2835_AUX_SPI_STAT_BUSY)) {
300 bcm2835aux_rd_fifo(bs);
304 /* there is still data pending to read check the timeout */
305 if (bs->rx_len && time_after(jiffies, timeout)) {
306 dev_dbg_ratelimited(&spi->dev,
307 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
309 bs->tx_len, bs->rx_len);
310 /* forward to interrupt handler */
311 return __bcm2835aux_spi_transfer_one_irq(master,
316 /* Transfer complete - reset SPI HW */
317 bcm2835aux_spi_reset_hw(bs);
319 /* and return without waiting for completion */
323 static int bcm2835aux_spi_transfer_one(struct spi_master *master,
324 struct spi_device *spi,
325 struct spi_transfer *tfr)
327 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
328 unsigned long spi_hz, clk_hz, speed;
329 unsigned long spi_used_hz;
330 unsigned long long xfer_time_us;
332 /* calculate the registers to handle
334 * note that we use the variable data mode, which
335 * is not optimal for longer transfers as we waste registers
336 * resulting (potentially) in more interrupts when transferring
339 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
340 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
341 BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
342 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
345 spi_hz = tfr->speed_hz;
346 clk_hz = clk_get_rate(bs->clk);
348 if (spi_hz >= clk_hz / 2) {
351 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
352 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
353 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
354 } else { /* the slowest we can go */
355 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
357 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
359 spi_used_hz = clk_hz / (2 * (speed + 1));
361 /* handle all the modes */
362 if (spi->mode & SPI_CPOL)
363 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
364 if (spi->mode & SPI_CPHA)
365 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
366 BCM2835_AUX_SPI_CNTL0_CPHA_IN;
368 /* set transmit buffers and length */
369 bs->tx_buf = tfr->tx_buf;
370 bs->rx_buf = tfr->rx_buf;
371 bs->tx_len = tfr->len;
372 bs->rx_len = tfr->len;
375 /* calculate the estimated time in us the transfer runs
376 * note that there are are 2 idle clocks after each
377 * chunk getting transferred - in our case the chunk size
378 * is 3 bytes, so we approximate this by 9 bits/byte
380 xfer_time_us = tfr->len * 9 * 1000000;
381 do_div(xfer_time_us, spi_used_hz);
383 /* run in polling mode for short transfers */
384 if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US)
385 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
387 /* run in interrupt mode for all others */
388 return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
391 static void bcm2835aux_spi_handle_err(struct spi_master *master,
392 struct spi_message *msg)
394 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
396 bcm2835aux_spi_reset_hw(bs);
399 static int bcm2835aux_spi_probe(struct platform_device *pdev)
401 struct spi_master *master;
402 struct bcm2835aux_spi *bs;
403 struct resource *res;
404 unsigned long clk_hz;
407 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
409 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
413 platform_set_drvdata(pdev, master);
414 master->mode_bits = BCM2835_AUX_SPI_MODE_BITS;
415 master->bits_per_word_mask = SPI_BPW_MASK(8);
416 master->num_chipselect = -1;
417 master->transfer_one = bcm2835aux_spi_transfer_one;
418 master->handle_err = bcm2835aux_spi_handle_err;
419 master->dev.of_node = pdev->dev.of_node;
421 bs = spi_master_get_devdata(master);
424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425 bs->regs = devm_ioremap_resource(&pdev->dev, res);
426 if (IS_ERR(bs->regs)) {
427 err = PTR_ERR(bs->regs);
431 bs->clk = devm_clk_get(&pdev->dev, NULL);
432 if ((!bs->clk) || (IS_ERR(bs->clk))) {
433 err = PTR_ERR(bs->clk);
434 dev_err(&pdev->dev, "could not get clk: %d\n", err);
438 bs->irq = platform_get_irq(pdev, 0);
440 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
441 err = bs->irq ? bs->irq : -ENODEV;
445 /* this also enables the HW block */
446 err = clk_prepare_enable(bs->clk);
448 dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
452 /* just checking if the clock returns a sane value */
453 clk_hz = clk_get_rate(bs->clk);
455 dev_err(&pdev->dev, "clock returns 0 Hz\n");
457 goto out_clk_disable;
460 /* reset SPI-HW block */
461 bcm2835aux_spi_reset_hw(bs);
463 err = devm_request_irq(&pdev->dev, bs->irq,
464 bcm2835aux_spi_interrupt,
466 dev_name(&pdev->dev), master);
468 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
469 goto out_clk_disable;
472 err = devm_spi_register_master(&pdev->dev, master);
474 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
475 goto out_clk_disable;
481 clk_disable_unprepare(bs->clk);
483 spi_master_put(master);
487 static int bcm2835aux_spi_remove(struct platform_device *pdev)
489 struct spi_master *master = platform_get_drvdata(pdev);
490 struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
492 bcm2835aux_spi_reset_hw(bs);
494 /* disable the HW block by releasing the clock */
495 clk_disable_unprepare(bs->clk);
500 static const struct of_device_id bcm2835aux_spi_match[] = {
501 { .compatible = "brcm,bcm2835-aux-spi", },
504 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
506 static struct platform_driver bcm2835aux_spi_driver = {
508 .name = "spi-bcm2835aux",
509 .of_match_table = bcm2835aux_spi_match,
511 .probe = bcm2835aux_spi_probe,
512 .remove = bcm2835aux_spi_remove,
514 module_platform_driver(bcm2835aux_spi_driver);
516 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
517 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
518 MODULE_LICENSE("GPL v2");