2 * Special handling for DW core on Intel MID platform
4 * Copyright (c) 2009, 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
25 #ifdef CONFIG_SPI_DW_MID_DMA
26 #include <linux/intel_mid_dma.h>
27 #include <linux/pci.h>
33 struct intel_mid_dma_slave dmas_tx;
34 struct intel_mid_dma_slave dmas_rx;
37 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
39 struct dw_spi *dws = param;
41 return dws->dma_dev == chan->device->dev;
44 static int mid_spi_dma_init(struct dw_spi *dws)
46 struct mid_dma *dw_dma = dws->dma_priv;
47 struct pci_dev *dma_dev;
48 struct intel_mid_dma_slave *rxs, *txs;
52 * Get pci device for DMA controller, currently it could only
53 * be the DMA controller of Medfield
55 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
59 dws->dma_dev = &dma_dev->dev;
62 dma_cap_set(DMA_SLAVE, mask);
64 /* 1. Init rx channel */
65 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
68 rxs = &dw_dma->dmas_rx;
69 rxs->hs_mode = LNW_DMA_HW_HS;
70 rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
71 dws->rxchan->private = rxs;
73 /* 2. Init tx channel */
74 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
77 txs = &dw_dma->dmas_tx;
78 txs->hs_mode = LNW_DMA_HW_HS;
79 txs->cfg_mode = LNW_DMA_MEM_TO_PER;
80 dws->txchan->private = txs;
86 dma_release_channel(dws->rxchan);
91 static void mid_spi_dma_exit(struct dw_spi *dws)
96 dmaengine_terminate_all(dws->txchan);
97 dma_release_channel(dws->txchan);
99 dmaengine_terminate_all(dws->rxchan);
100 dma_release_channel(dws->rxchan);
104 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
105 * channel will clear a corresponding bit.
107 static void dw_spi_dma_tx_done(void *arg)
109 struct dw_spi *dws = arg;
111 clear_bit(TX_BUSY, &dws->dma_chan_busy);
112 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
114 dw_spi_xfer_done(dws);
117 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
119 struct dma_slave_config txconf;
120 struct dma_async_tx_descriptor *txdesc;
125 txconf.direction = DMA_MEM_TO_DEV;
126 txconf.dst_addr = dws->dma_addr;
127 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
128 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
129 txconf.dst_addr_width = dws->dma_width;
130 txconf.device_fc = false;
132 dmaengine_slave_config(dws->txchan, &txconf);
134 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
135 dws->tx_sgl.dma_address = dws->tx_dma;
136 dws->tx_sgl.length = dws->len;
138 txdesc = dmaengine_prep_slave_sg(dws->txchan,
142 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
146 txdesc->callback = dw_spi_dma_tx_done;
147 txdesc->callback_param = dws;
153 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
154 * channel will clear a corresponding bit.
156 static void dw_spi_dma_rx_done(void *arg)
158 struct dw_spi *dws = arg;
160 clear_bit(RX_BUSY, &dws->dma_chan_busy);
161 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
163 dw_spi_xfer_done(dws);
166 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
168 struct dma_slave_config rxconf;
169 struct dma_async_tx_descriptor *rxdesc;
174 rxconf.direction = DMA_DEV_TO_MEM;
175 rxconf.src_addr = dws->dma_addr;
176 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
177 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
178 rxconf.src_addr_width = dws->dma_width;
179 rxconf.device_fc = false;
181 dmaengine_slave_config(dws->rxchan, &rxconf);
183 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
184 dws->rx_sgl.dma_address = dws->rx_dma;
185 dws->rx_sgl.length = dws->len;
187 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
191 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
195 rxdesc->callback = dw_spi_dma_rx_done;
196 rxdesc->callback_param = dws;
201 static void dw_spi_dma_setup(struct dw_spi *dws)
205 spi_enable_chip(dws, 0);
207 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
208 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
211 dma_ctrl |= SPI_DMA_TDMAE;
213 dma_ctrl |= SPI_DMA_RDMAE;
214 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
216 spi_enable_chip(dws, 1);
219 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
221 struct dma_async_tx_descriptor *txdesc, *rxdesc;
223 /* 1. setup DMA related registers */
225 dw_spi_dma_setup(dws);
227 /* 2. Prepare the TX dma transfer */
228 txdesc = dw_spi_dma_prepare_tx(dws);
230 /* 3. Prepare the RX dma transfer */
231 rxdesc = dw_spi_dma_prepare_rx(dws);
233 /* rx must be started before tx due to spi instinct */
235 set_bit(RX_BUSY, &dws->dma_chan_busy);
236 dmaengine_submit(rxdesc);
237 dma_async_issue_pending(dws->rxchan);
241 set_bit(TX_BUSY, &dws->dma_chan_busy);
242 dmaengine_submit(txdesc);
243 dma_async_issue_pending(dws->txchan);
249 static struct dw_spi_dma_ops mid_dma_ops = {
250 .dma_init = mid_spi_dma_init,
251 .dma_exit = mid_spi_dma_exit,
252 .dma_transfer = mid_spi_dma_transfer,
256 /* Some specific info for SPI0 controller on Intel MID */
258 /* HW info for MRST Clk Control Unit, 32b reg per controller */
259 #define MRST_SPI_CLK_BASE 100000000 /* 100m */
260 #define MRST_CLK_SPI_REG 0xff11d86c
261 #define CLK_SPI_BDIV_OFFSET 0
262 #define CLK_SPI_BDIV_MASK 0x00000007
263 #define CLK_SPI_CDIV_OFFSET 9
264 #define CLK_SPI_CDIV_MASK 0x00000e00
265 #define CLK_SPI_DISABLE_OFFSET 8
267 int dw_spi_mid_init(struct dw_spi *dws)
269 void __iomem *clk_reg;
272 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
276 /* Get SPI controller operating freq info */
277 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
278 clk_cdiv &= CLK_SPI_CDIV_MASK;
279 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
280 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
284 #ifdef CONFIG_SPI_DW_MID_DMA
285 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
288 dws->dma_ops = &mid_dma_ops;