drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u16 cr0;
  34         u8 cs;                  /* chip select pin */
  35         u8 n_bytes;             /* current is a 1/2/4 byte op */
  36         u8 tmode;               /* TR/TO/RO/EEPROM */
  37         u8 type;                /* SPI/SSP/MicroWire */
  38
  39         u8 poll_mode;           /* 1 means use poll mode */
  40
  41         u32 dma_width;
  42         u32 rx_threshold;
  43         u32 tx_threshold;
  44         u8 enable_dma;
  45         u8 bits_per_word;
  46         u16 clk_div;            /* baud rate divider */
  47         u32 speed_hz;           /* baud rate */
  48         void (*cs_control)(u32 command);
  49 };
  50
  51 #ifdef CONFIG_DEBUG_FS
  52 #define SPI_REGS_BUFSIZE        1024
  53 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  54                 size_t count, loff_t *ppos)
  55 {
  56         struct dw_spi *dws = file->private_data;
  57         char *buf;
  58         u32 len = 0;
  59         ssize_t ret;
  60
  61         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  62         if (!buf)
  63                 return 0;
  64
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "%s registers:\n", dev_name(&dws->master->dev));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "=================================\n");
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  97         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  99         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "=================================\n");
 101
 102         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
 103         kfree(buf);
 104         return ret;
 105 }
 106
 107 static const struct file_operations dw_spi_regs_ops = {
 108         .owner          = THIS_MODULE,
 109         .open           = simple_open,
 110         .read           = dw_spi_show_regs,
 111         .llseek         = default_llseek,
 112 };
 113
 114 static int dw_spi_debugfs_init(struct dw_spi *dws)
 115 {
 116         dws->debugfs = debugfs_create_dir("dw_spi", NULL);
 117         if (!dws->debugfs)
 118                 return -ENOMEM;
 119
 120         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 121                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 122         return 0;
 123 }
 124
 125 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 126 {
 127         debugfs_remove_recursive(dws->debugfs);
 128 }
 129
 130 #else
 131 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 132 {
 133         return 0;
 134 }
 135
 136 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 137 {
 138 }
 139 #endif /* CONFIG_DEBUG_FS */
 140
 141 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
 142 {
 143         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 144         struct chip_data *chip = spi_get_ctldata(spi);
 145
 146         /* Chip select logic is inverted from spi_set_cs() */
 147         if (chip && chip->cs_control)
 148                 chip->cs_control(!enable);
 149
 150         if (!enable)
 151                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 152 }
 153
 154 /* Return the max entries we can fill into tx fifo */
 155 static inline u32 tx_max(struct dw_spi *dws)
 156 {
 157         u32 tx_left, tx_room, rxtx_gap;
 158
 159         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 160         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 161
 162         /*
 163          * Another concern is about the tx/rx mismatch, we
 164          * though to use (dws->fifo_len - rxflr - txflr) as
 165          * one maximum value for tx, but it doesn't cover the
 166          * data which is out of tx/rx fifo and inside the
 167          * shift registers. So a control from sw point of
 168          * view is taken.
 169          */
 170         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 171                         / dws->n_bytes;
 172
 173         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 174 }
 175
 176 /* Return the max entries we should read out of rx fifo */
 177 static inline u32 rx_max(struct dw_spi *dws)
 178 {
 179         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 180
 181         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 182 }
 183
 184 static void dw_writer(struct dw_spi *dws)
 185 {
 186         u32 max = tx_max(dws);
 187         u16 txw = 0;
 188
 189         while (max--) {
 190                 /* Set the tx word if the transfer's original "tx" is not null */
 191                 if (dws->tx_end - dws->len) {
 192                         if (dws->n_bytes == 1)
 193                                 txw = *(u8 *)(dws->tx);
 194                         else
 195                                 txw = *(u16 *)(dws->tx);
 196                 }
 197                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 198                 dws->tx += dws->n_bytes;
 199         }
 200 }
 201
 202 static void dw_reader(struct dw_spi *dws)
 203 {
 204         u32 max = rx_max(dws);
 205         u16 rxw;
 206
 207         while (max--) {
 208                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 209                 /* Care rx only if the transfer's original "rx" is not null */
 210                 if (dws->rx_end - dws->len) {
 211                         if (dws->n_bytes == 1)
 212                                 *(u8 *)(dws->rx) = rxw;
 213                         else
 214                                 *(u16 *)(dws->rx) = rxw;
 215                 }
 216                 dws->rx += dws->n_bytes;
 217         }
 218 }
 219
 220 static void int_error_stop(struct dw_spi *dws, const char *msg)
 221 {
 222         spi_reset_chip(dws);
 223
 224         dev_err(&dws->master->dev, "%s\n", msg);
 225         dws->master->cur_msg->status = -EIO;
 226         spi_finalize_current_transfer(dws->master);
 227 }
 228
 229 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 230 {
 231         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 232
 233         /* Error handling */
 234         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 235                 dw_readl(dws, DW_SPI_ICR);
 236                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 237                 return IRQ_HANDLED;
 238         }
 239
 240         dw_reader(dws);
 241         if (dws->rx_end == dws->rx) {
 242                 spi_mask_intr(dws, SPI_INT_TXEI);
 243                 spi_finalize_current_transfer(dws->master);
 244                 return IRQ_HANDLED;
 245         }
 246         if (irq_status & SPI_INT_TXEI) {
 247                 spi_mask_intr(dws, SPI_INT_TXEI);
 248                 dw_writer(dws);
 249                 /* Enable TX irq always, it will be disabled when RX finished */
 250                 spi_umask_intr(dws, SPI_INT_TXEI);
 251         }
 252
 253         return IRQ_HANDLED;
 254 }
 255
 256 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 257 {
 258         struct spi_master *master = dev_id;
 259         struct dw_spi *dws = spi_master_get_devdata(master);
 260         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 261
 262         if (!irq_status)
 263                 return IRQ_NONE;
 264
 265         if (!master->cur_msg) {
 266                 spi_mask_intr(dws, SPI_INT_TXEI);
 267                 return IRQ_HANDLED;
 268         }
 269
 270         return dws->transfer_handler(dws);
 271 }
 272
 273 /* Must be called inside pump_transfers() */
 274 static int poll_transfer(struct dw_spi *dws)
 275 {
 276         do {
 277                 dw_writer(dws);
 278                 dw_reader(dws);
 279                 cpu_relax();
 280         } while (dws->rx_end > dws->rx);
 281
 282         return 0;
 283 }
 284
 285 static int dw_spi_transfer_one(struct spi_master *master,
 286                 struct spi_device *spi, struct spi_transfer *transfer)
 287 {
 288         struct dw_spi *dws = spi_master_get_devdata(master);
 289         struct chip_data *chip = spi_get_ctldata(spi);
 290         u8 imask = 0;
 291         u16 txlevel = 0;
 292         u16 clk_div = 0;
 293         u32 speed = 0;
 294         u32 cr0 = 0;
 295         int ret;
 296
 297         dws->dma_mapped = 0;
 298         dws->n_bytes = chip->n_bytes;
 299         dws->dma_width = chip->dma_width;
 300
 301         dws->tx = (void *)transfer->tx_buf;
 302         dws->tx_end = dws->tx + transfer->len;
 303         dws->rx = transfer->rx_buf;
 304         dws->rx_end = dws->rx + transfer->len;
 305         dws->len = transfer->len;
 306
 307         spi_enable_chip(dws, 0);
 308
 309         cr0 = chip->cr0;
 310
 311         /* Handle per transfer options for bpw and speed */
 312         speed = chip->speed_hz;
 313         if ((transfer->speed_hz != speed) || !chip->clk_div) {
 314                 speed = transfer->speed_hz;
 315
 316                 /* clk_div doesn't support odd number */
 317                 clk_div = (dws->max_freq / speed + 1) & 0xfffe;
 318
 319                 chip->speed_hz = speed;
 320                 chip->clk_div = clk_div;
 321
 322                 spi_set_clk(dws, chip->clk_div);
 323         }
 324         if (transfer->bits_per_word == 8) {
 325                 dws->n_bytes = 1;
 326                 dws->dma_width = 1;
 327         } else if (transfer->bits_per_word == 16) {
 328                 dws->n_bytes = 2;
 329                 dws->dma_width = 2;
 330         }
 331         cr0 = (transfer->bits_per_word - 1)
 332                 | (chip->type << SPI_FRF_OFFSET)
 333                 | (spi->mode << SPI_MODE_OFFSET)
 334                 | (chip->tmode << SPI_TMOD_OFFSET);
 335
 336         /*
 337          * Adjust transfer mode if necessary. Requires platform dependent
 338          * chipselect mechanism.
 339          */
 340         if (chip->cs_control) {
 341                 if (dws->rx && dws->tx)
 342                         chip->tmode = SPI_TMOD_TR;
 343                 else if (dws->rx)
 344                         chip->tmode = SPI_TMOD_RO;
 345                 else
 346                         chip->tmode = SPI_TMOD_TO;
 347
 348                 cr0 &= ~SPI_TMOD_MASK;
 349                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 350         }
 351
 352         dw_writel(dws, DW_SPI_CTRL0, cr0);
 353
 354         /* Check if current transfer is a DMA transaction */
 355         if (master->can_dma && master->can_dma(master, spi, transfer))
 356                 dws->dma_mapped = master->cur_msg_mapped;
 357
 358         /* For poll mode just disable all interrupts */
 359         spi_mask_intr(dws, 0xff);
 360
 361         /*
 362          * Interrupt mode
 363          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 364          */
 365         if (dws->dma_mapped) {
 366                 ret = dws->dma_ops->dma_setup(dws, transfer);
 367                 if (ret < 0) {
 368                         spi_enable_chip(dws, 1);
 369                         return ret;
 370                 }
 371         } else if (!chip->poll_mode) {
 372                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 373                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 374
 375                 /* Set the interrupt mask */
 376                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 377                          SPI_INT_RXUI | SPI_INT_RXOI;
 378                 spi_umask_intr(dws, imask);
 379
 380                 dws->transfer_handler = interrupt_transfer;
 381         }
 382
 383         spi_enable_chip(dws, 1);
 384
 385         if (dws->dma_mapped) {
 386                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 387                 if (ret < 0)
 388                         return ret;
 389         }
 390
 391         if (chip->poll_mode)
 392                 return poll_transfer(dws);
 393
 394         return 1;
 395 }
 396
 397 static void dw_spi_handle_err(struct spi_master *master,
 398                 struct spi_message *msg)
 399 {
 400         struct dw_spi *dws = spi_master_get_devdata(master);
 401
 402         if (dws->dma_mapped)
 403                 dws->dma_ops->dma_stop(dws);
 404
 405         spi_reset_chip(dws);
 406 }
 407
 408 /* This may be called twice for each spi dev */
 409 static int dw_spi_setup(struct spi_device *spi)
 410 {
 411         struct dw_spi_chip *chip_info = NULL;
 412         struct chip_data *chip;
 413         int ret;
 414
 415         /* Only alloc on first setup */
 416         chip = spi_get_ctldata(spi);
 417         if (!chip) {
 418                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 419                 if (!chip)
 420                         return -ENOMEM;
 421                 spi_set_ctldata(spi, chip);
 422         }
 423
 424         /*
 425          * Protocol drivers may change the chip settings, so...
 426          * if chip_info exists, use it
 427          */
 428         chip_info = spi->controller_data;
 429
 430         /* chip_info doesn't always exist */
 431         if (chip_info) {
 432                 if (chip_info->cs_control)
 433                         chip->cs_control = chip_info->cs_control;
 434
 435                 chip->poll_mode = chip_info->poll_mode;
 436                 chip->type = chip_info->type;
 437
 438                 chip->rx_threshold = 0;
 439                 chip->tx_threshold = 0;
 440         }
 441
 442         if (spi->bits_per_word == 8) {
 443                 chip->n_bytes = 1;
 444                 chip->dma_width = 1;
 445         } else if (spi->bits_per_word == 16) {
 446                 chip->n_bytes = 2;
 447                 chip->dma_width = 2;
 448         }
 449         chip->bits_per_word = spi->bits_per_word;
 450
 451         chip->tmode = 0; /* Tx & Rx */
 452         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 453         chip->cr0 = (chip->bits_per_word - 1)
 454                         | (chip->type << SPI_FRF_OFFSET)
 455                         | (spi->mode  << SPI_MODE_OFFSET)
 456                         | (chip->tmode << SPI_TMOD_OFFSET);
 457
 458         if (spi->mode & SPI_LOOP)
 459                 chip->cr0 |= 1 << SPI_SRL_OFFSET;
 460
 461         if (gpio_is_valid(spi->cs_gpio)) {
 462                 ret = gpio_direction_output(spi->cs_gpio,
 463                                 !(spi->mode & SPI_CS_HIGH));
 464                 if (ret)
 465                         return ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static void dw_spi_cleanup(struct spi_device *spi)
 472 {
 473         struct chip_data *chip = spi_get_ctldata(spi);
 474
 475         kfree(chip);
 476         spi_set_ctldata(spi, NULL);
 477 }
 478
 479 /* Restart the controller, disable all interrupts, clean rx fifo */
 480 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 481 {
 482         spi_reset_chip(dws);
 483
 484         /*
 485          * Try to detect the FIFO depth if not set by interface driver,
 486          * the depth could be from 2 to 256 from HW spec
 487          */
 488         if (!dws->fifo_len) {
 489                 u32 fifo;
 490
 491                 for (fifo = 1; fifo < 256; fifo++) {
 492                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 493                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 494                                 break;
 495                 }
 496                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 497
 498                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 499                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 500         }
 501 }
 502
 503 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 504 {
 505         struct spi_master *master;
 506         int ret;
 507
 508         BUG_ON(dws == NULL);
 509
 510         master = spi_alloc_master(dev, 0);
 511         if (!master)
 512                 return -ENOMEM;
 513
 514         dws->master = master;
 515         dws->type = SSI_MOTO_SPI;
 516         dws->dma_inited = 0;
 517         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 518         snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
 519
 520         ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
 521                         dws->name, master);
 522         if (ret < 0) {
 523                 dev_err(&master->dev, "can not get IRQ\n");
 524                 goto err_free_master;
 525         }
 526
 527         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 528         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 529         master->bus_num = dws->bus_num;
 530         master->num_chipselect = dws->num_cs;
 531         master->setup = dw_spi_setup;
 532         master->cleanup = dw_spi_cleanup;
 533         master->set_cs = dw_spi_set_cs;
 534         master->transfer_one = dw_spi_transfer_one;
 535         master->handle_err = dw_spi_handle_err;
 536         master->max_speed_hz = dws->max_freq;
 537         master->dev.of_node = dev->of_node;
 538
 539         /* Basic HW init */
 540         spi_hw_init(dev, dws);
 541
 542         if (dws->dma_ops && dws->dma_ops->dma_init) {
 543                 ret = dws->dma_ops->dma_init(dws);
 544                 if (ret) {
 545                         dev_warn(dev, "DMA init failed\n");
 546                         dws->dma_inited = 0;
 547                 } else {
 548                         master->can_dma = dws->dma_ops->can_dma;
 549                 }
 550         }
 551
 552         spi_master_set_devdata(master, dws);
 553         ret = devm_spi_register_master(dev, master);
 554         if (ret) {
 555                 dev_err(&master->dev, "problem registering spi master\n");
 556                 goto err_dma_exit;
 557         }
 558
 559         dw_spi_debugfs_init(dws);
 560         return 0;
 561
 562 err_dma_exit:
 563         if (dws->dma_ops && dws->dma_ops->dma_exit)
 564                 dws->dma_ops->dma_exit(dws);
 565         spi_enable_chip(dws, 0);
 566 err_free_master:
 567         spi_master_put(master);
 568         return ret;
 569 }
 570 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 571
 572 void dw_spi_remove_host(struct dw_spi *dws)
 573 {
 574         if (!dws)
 575                 return;
 576         dw_spi_debugfs_remove(dws);
 577
 578         if (dws->dma_ops && dws->dma_ops->dma_exit)
 579                 dws->dma_ops->dma_exit(dws);
 580         spi_enable_chip(dws, 0);
 581         /* Disable clk */
 582         spi_set_clk(dws, 0);
 583 }
 584 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 585
 586 int dw_spi_suspend_host(struct dw_spi *dws)
 587 {
 588         int ret = 0;
 589
 590         ret = spi_master_suspend(dws->master);
 591         if (ret)
 592                 return ret;
 593         spi_enable_chip(dws, 0);
 594         spi_set_clk(dws, 0);
 595         return ret;
 596 }
 597 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 598
 599 int dw_spi_resume_host(struct dw_spi *dws)
 600 {
 601         int ret;
 602
 603         spi_hw_init(&dws->master->dev, dws);
 604         ret = spi_master_resume(dws->master);
 605         if (ret)
 606                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 607         return ret;
 608 }
 609 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 610
 611 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 612 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 613 MODULE_LICENSE("GPL v2");