2 * Driver for Cirrus Logic EP93xx SPI controller.
4 * Copyright (C) 2010-2011 Mika Westerberg
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 * For more information about the SPI controller see documentation on Cirrus
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dmaengine.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/workqueue.h>
30 #include <linux/sched.h>
31 #include <linux/scatterlist.h>
32 #include <linux/spi/spi.h>
34 #include <linux/platform_data/dma-ep93xx.h>
35 #include <linux/platform_data/spi-ep93xx.h>
38 #define SSPCR0_MODE_SHIFT 6
39 #define SSPCR0_SCR_SHIFT 8
42 #define SSPCR1_RIE BIT(0)
43 #define SSPCR1_TIE BIT(1)
44 #define SSPCR1_RORIE BIT(2)
45 #define SSPCR1_LBM BIT(3)
46 #define SSPCR1_SSE BIT(4)
47 #define SSPCR1_MS BIT(5)
48 #define SSPCR1_SOD BIT(6)
53 #define SSPSR_TFE BIT(0)
54 #define SSPSR_TNF BIT(1)
55 #define SSPSR_RNE BIT(2)
56 #define SSPSR_RFF BIT(3)
57 #define SSPSR_BSY BIT(4)
58 #define SSPCPSR 0x0010
61 #define SSPIIR_RIS BIT(0)
62 #define SSPIIR_TIS BIT(1)
63 #define SSPIIR_RORIS BIT(2)
66 /* timeout in milliseconds */
68 /* maximum depth of RX/TX FIFO */
69 #define SPI_FIFO_SIZE 8
72 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @lock: spinlock that protects concurrent accesses to fields @running,
74 * @current_msg and @msg_queue
75 * @pdev: pointer to platform device
76 * @clk: clock for the controller
77 * @regs_base: pointer to ioremap()'d registers
78 * @sspdr_phys: physical address of the SSPDR register
79 * @min_rate: minimum clock rate (in Hz) supported by the controller
80 * @max_rate: maximum clock rate (in Hz) supported by the controller
81 * @running: is the queue running
82 * @wq: workqueue used by the driver
83 * @msg_work: work that is queued for the driver
84 * @wait: wait here until given transfer is completed
85 * @msg_queue: queue for the messages
86 * @current_msg: message that is currently processed (or %NULL if none)
87 * @tx: current byte in transfer to transmit
88 * @rx: current byte in transfer to receive
89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
90 * frame decreases this level and sending one frame increases it.
91 * @dma_rx: RX DMA channel
92 * @dma_tx: TX DMA channel
93 * @dma_rx_data: RX parameters passed to the DMA engine
94 * @dma_tx_data: TX parameters passed to the DMA engine
95 * @rx_sgt: sg table for RX transfers
96 * @tx_sgt: sg table for TX transfers
97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
100 * This structure holds EP93xx SPI controller specific information. When
101 * @running is %true, driver accepts transfer requests from protocol drivers.
102 * @current_msg is used to hold pointer to the message that is currently
103 * processed. If @current_msg is %NULL, it means that no processing is going
106 * Most of the fields are only written once and they can be accessed without
107 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
108 * @running, and @msg_queue.
112 const struct platform_device *pdev;
114 void __iomem *regs_base;
115 unsigned long sspdr_phys;
116 unsigned long min_rate;
117 unsigned long max_rate;
119 struct workqueue_struct *wq;
120 struct work_struct msg_work;
121 struct completion wait;
122 struct list_head msg_queue;
123 struct spi_message *current_msg;
127 struct dma_chan *dma_rx;
128 struct dma_chan *dma_tx;
129 struct ep93xx_dma_data dma_rx_data;
130 struct ep93xx_dma_data dma_tx_data;
131 struct sg_table rx_sgt;
132 struct sg_table tx_sgt;
137 * struct ep93xx_spi_chip - SPI device hardware settings
138 * @spi: back pointer to the SPI device
139 * @div_cpsr: cpsr (pre-scaler) divider
140 * @div_scr: scr divider
141 * @ops: private chip operations
143 * This structure is used to store hardware register specific settings for each
144 * SPI device. Settings are written to hardware by function
145 * ep93xx_spi_chip_setup().
147 struct ep93xx_spi_chip {
148 const struct spi_device *spi;
151 struct ep93xx_spi_chip_ops *ops;
154 /* converts bits per word to CR0.DSS value */
155 #define bits_per_word_to_dss(bpw) ((bpw) - 1)
157 static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
160 writeb(value, espi->regs_base + reg);
163 static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
165 return readb(spi->regs_base + reg);
168 static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
171 writew(value, espi->regs_base + reg);
174 static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
176 return readw(spi->regs_base + reg);
179 static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
184 err = clk_enable(espi->clk);
188 regval = ep93xx_spi_read_u8(espi, SSPCR1);
189 regval |= SSPCR1_SSE;
190 ep93xx_spi_write_u8(espi, SSPCR1, regval);
195 static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
199 regval = ep93xx_spi_read_u8(espi, SSPCR1);
200 regval &= ~SSPCR1_SSE;
201 ep93xx_spi_write_u8(espi, SSPCR1, regval);
203 clk_disable(espi->clk);
206 static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
210 regval = ep93xx_spi_read_u8(espi, SSPCR1);
211 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
212 ep93xx_spi_write_u8(espi, SSPCR1, regval);
215 static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
219 regval = ep93xx_spi_read_u8(espi, SSPCR1);
220 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
221 ep93xx_spi_write_u8(espi, SSPCR1, regval);
225 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
226 * @espi: ep93xx SPI controller struct
227 * @chip: divisors are calculated for this chip
228 * @rate: desired SPI output clock rate
230 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
231 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
232 * for some reason, divisors cannot be calculated nothing is stored and
233 * %-EINVAL is returned.
235 static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
236 struct ep93xx_spi_chip *chip,
239 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
243 * Make sure that max value is between values supported by the
244 * controller. Note that minimum value is already checked in
245 * ep93xx_spi_transfer().
247 rate = clamp(rate, espi->min_rate, espi->max_rate);
250 * Calculate divisors so that we can get speed according the
252 * rate = spi_clock_rate / (cpsr * (1 + scr))
254 * cpsr must be even number and starts from 2, scr can be any number
257 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
258 for (scr = 0; scr <= 255; scr++) {
259 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
260 chip->div_scr = (u8)scr;
261 chip->div_cpsr = (u8)cpsr;
270 static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
272 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
273 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
275 if (chip->ops && chip->ops->cs_control)
276 chip->ops->cs_control(spi, value);
280 * ep93xx_spi_setup() - setup an SPI device
281 * @spi: SPI device to setup
283 * This function sets up SPI device mode, speed etc. Can be called multiple
284 * times for a single device. Returns %0 in case of success, negative error in
285 * case of failure. When this function returns success, the device is
288 static int ep93xx_spi_setup(struct spi_device *spi)
290 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
291 struct ep93xx_spi_chip *chip;
293 chip = spi_get_ctldata(spi);
295 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
298 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
303 chip->ops = spi->controller_data;
305 if (chip->ops && chip->ops->setup) {
306 int ret = chip->ops->setup(spi);
313 spi_set_ctldata(spi, chip);
316 ep93xx_spi_cs_control(spi, false);
321 * ep93xx_spi_transfer() - queue message to be transferred
322 * @spi: target SPI device
323 * @msg: message to be transferred
325 * This function is called by SPI device drivers when they are going to transfer
326 * a new message. It simply puts the message in the queue and schedules
327 * workqueue to perform the actual transfer later on.
329 * Returns %0 on success and negative error in case of failure.
331 static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
333 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
334 struct spi_transfer *t;
337 if (!msg || !msg->complete)
340 /* first validate each transfer */
341 list_for_each_entry(t, &msg->transfers, transfer_list) {
342 if (t->speed_hz && t->speed_hz < espi->min_rate)
347 * Now that we own the message, let's initialize it so that it is
348 * suitable for us. We use @msg->status to signal whether there was
349 * error in transfer and @msg->state is used to hold pointer to the
350 * current transfer (or %NULL if no active current transfer).
354 msg->actual_length = 0;
356 spin_lock_irqsave(&espi->lock, flags);
357 if (!espi->running) {
358 spin_unlock_irqrestore(&espi->lock, flags);
361 list_add_tail(&msg->queue, &espi->msg_queue);
362 queue_work(espi->wq, &espi->msg_work);
363 spin_unlock_irqrestore(&espi->lock, flags);
369 * ep93xx_spi_cleanup() - cleans up master controller specific state
370 * @spi: SPI device to cleanup
372 * This function releases master controller specific state for given @spi
375 static void ep93xx_spi_cleanup(struct spi_device *spi)
377 struct ep93xx_spi_chip *chip;
379 chip = spi_get_ctldata(spi);
381 if (chip->ops && chip->ops->cleanup)
382 chip->ops->cleanup(spi);
383 spi_set_ctldata(spi, NULL);
389 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
390 * @espi: ep93xx SPI controller struct
391 * @chip: chip specific settings
392 * @bits_per_word: transfer bits_per_word
394 * This function sets up the actual hardware registers with settings given in
395 * @chip. Note that no validation is done so make sure that callers validate
396 * settings before calling this.
398 static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
399 const struct ep93xx_spi_chip *chip,
402 u8 dss = bits_per_word_to_dss(bits_per_word);
405 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
406 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
409 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
410 chip->spi->mode, chip->div_cpsr, chip->div_scr, dss);
411 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
413 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
414 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
417 static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
419 if (t->bits_per_word > 8) {
423 tx_val = ((u16 *)t->tx_buf)[espi->tx];
424 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
425 espi->tx += sizeof(tx_val);
430 tx_val = ((u8 *)t->tx_buf)[espi->tx];
431 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
432 espi->tx += sizeof(tx_val);
436 static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
438 if (t->bits_per_word > 8) {
441 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
443 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
444 espi->rx += sizeof(rx_val);
448 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
450 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
451 espi->rx += sizeof(rx_val);
456 * ep93xx_spi_read_write() - perform next RX/TX transfer
457 * @espi: ep93xx SPI controller struct
459 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
460 * called several times, the whole transfer will be completed. Returns
461 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
463 * When this function is finished, RX FIFO should be empty and TX FIFO should be
466 static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
468 struct spi_message *msg = espi->current_msg;
469 struct spi_transfer *t = msg->state;
471 /* read as long as RX FIFO has frames in it */
472 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
473 ep93xx_do_read(espi, t);
477 /* write as long as TX FIFO has room */
478 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
479 ep93xx_do_write(espi, t);
483 if (espi->rx == t->len)
489 static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
492 * Now everything is set up for the current transfer. We prime the TX
493 * FIFO, enable interrupts, and wait for the transfer to complete.
495 if (ep93xx_spi_read_write(espi)) {
496 ep93xx_spi_enable_interrupts(espi);
497 wait_for_completion(&espi->wait);
502 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
503 * @espi: ep93xx SPI controller struct
504 * @dir: DMA transfer direction
506 * Function configures the DMA, maps the buffer and prepares the DMA
507 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
508 * in case of failure.
510 static struct dma_async_tx_descriptor *
511 ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
513 struct spi_transfer *t = espi->current_msg->state;
514 struct dma_async_tx_descriptor *txd;
515 enum dma_slave_buswidth buswidth;
516 struct dma_slave_config conf;
517 struct scatterlist *sg;
518 struct sg_table *sgt;
519 struct dma_chan *chan;
520 const void *buf, *pbuf;
524 if (t->bits_per_word > 8)
525 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
527 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
529 memset(&conf, 0, sizeof(conf));
530 conf.direction = dir;
532 if (dir == DMA_DEV_TO_MEM) {
537 conf.src_addr = espi->sspdr_phys;
538 conf.src_addr_width = buswidth;
544 conf.dst_addr = espi->sspdr_phys;
545 conf.dst_addr_width = buswidth;
548 ret = dmaengine_slave_config(chan, &conf);
553 * We need to split the transfer into PAGE_SIZE'd chunks. This is
554 * because we are using @espi->zeropage to provide a zero RX buffer
555 * for the TX transfers and we have only allocated one page for that.
557 * For performance reasons we allocate a new sg_table only when
558 * needed. Otherwise we will re-use the current one. Eventually the
559 * last sg_table is released in ep93xx_spi_release_dma().
562 nents = DIV_ROUND_UP(len, PAGE_SIZE);
563 if (nents != sgt->nents) {
566 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
572 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
573 size_t bytes = min_t(size_t, len, PAGE_SIZE);
576 sg_set_page(sg, virt_to_page(pbuf), bytes,
577 offset_in_page(pbuf));
579 sg_set_page(sg, virt_to_page(espi->zeropage),
588 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len);
589 return ERR_PTR(-EINVAL);
592 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
594 return ERR_PTR(-ENOMEM);
596 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
598 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
599 return ERR_PTR(-ENOMEM);
605 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
606 * @espi: ep93xx SPI controller struct
607 * @dir: DMA transfer direction
609 * Function finishes with the DMA transfer. After this, the DMA buffer is
612 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
613 enum dma_transfer_direction dir)
615 struct dma_chan *chan;
616 struct sg_table *sgt;
618 if (dir == DMA_DEV_TO_MEM) {
626 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
629 static void ep93xx_spi_dma_callback(void *callback_param)
631 complete(callback_param);
634 static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
636 struct spi_message *msg = espi->current_msg;
637 struct dma_async_tx_descriptor *rxd, *txd;
639 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
641 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
642 msg->status = PTR_ERR(rxd);
646 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
648 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
649 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
650 msg->status = PTR_ERR(txd);
654 /* We are ready when RX is done */
655 rxd->callback = ep93xx_spi_dma_callback;
656 rxd->callback_param = &espi->wait;
658 /* Now submit both descriptors and wait while they finish */
659 dmaengine_submit(rxd);
660 dmaengine_submit(txd);
662 dma_async_issue_pending(espi->dma_rx);
663 dma_async_issue_pending(espi->dma_tx);
665 wait_for_completion(&espi->wait);
667 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
668 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
672 * ep93xx_spi_process_transfer() - processes one SPI transfer
673 * @espi: ep93xx SPI controller struct
674 * @msg: current message
675 * @t: transfer to process
677 * This function processes one SPI transfer given in @t. Function waits until
678 * transfer is complete (may sleep) and updates @msg->status based on whether
679 * transfer was successfully processed or not.
681 static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
682 struct spi_message *msg,
683 struct spi_transfer *t)
685 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
690 err = ep93xx_spi_calc_divisors(espi, chip, t->speed_hz);
692 dev_err(&espi->pdev->dev, "failed to adjust speed\n");
697 ep93xx_spi_chip_setup(espi, chip, t->bits_per_word);
703 * There is no point of setting up DMA for the transfers which will
704 * fit into the FIFO and can be transferred with a single interrupt.
705 * So in these cases we will be using PIO and don't bother for DMA.
707 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
708 ep93xx_spi_dma_transfer(espi);
710 ep93xx_spi_pio_transfer(espi);
713 * In case of error during transmit, we bail out from processing
719 msg->actual_length += t->len;
722 * After this transfer is finished, perform any possible
723 * post-transfer actions requested by the protocol driver.
725 if (t->delay_usecs) {
726 set_current_state(TASK_UNINTERRUPTIBLE);
727 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
730 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
732 * In case protocol driver is asking us to drop the
733 * chipselect briefly, we let the scheduler to handle
736 ep93xx_spi_cs_control(msg->spi, false);
738 ep93xx_spi_cs_control(msg->spi, true);
744 * ep93xx_spi_process_message() - process one SPI message
745 * @espi: ep93xx SPI controller struct
746 * @msg: message to process
748 * This function processes a single SPI message. We go through all transfers in
749 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
750 * asserted during the whole message (unless per transfer cs_change is set).
752 * @msg->status contains %0 in case of success or negative error code in case of
755 static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
756 struct spi_message *msg)
758 unsigned long timeout;
759 struct spi_transfer *t;
763 * Enable the SPI controller and its clock.
765 err = ep93xx_spi_enable(espi);
767 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
773 * Just to be sure: flush any data from RX FIFO.
775 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
776 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
777 if (time_after(jiffies, timeout)) {
778 dev_warn(&espi->pdev->dev,
779 "timeout while flushing RX FIFO\n");
780 msg->status = -ETIMEDOUT;
783 ep93xx_spi_read_u16(espi, SSPDR);
787 * We explicitly handle FIFO level. This way we don't have to check TX
788 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
790 espi->fifo_level = 0;
793 * Assert the chipselect.
795 ep93xx_spi_cs_control(msg->spi, true);
797 list_for_each_entry(t, &msg->transfers, transfer_list) {
798 ep93xx_spi_process_transfer(espi, msg, t);
804 * Now the whole message is transferred (or failed for some reason). We
805 * deselect the device and disable the SPI controller.
807 ep93xx_spi_cs_control(msg->spi, false);
808 ep93xx_spi_disable(espi);
811 #define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
814 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
817 * Workqueue worker function. This function is called when there are new
818 * SPI messages to be processed. Message is taken out from the queue and then
819 * passed to ep93xx_spi_process_message().
821 * After message is transferred, protocol driver is notified by calling
822 * @msg->complete(). In case of error, @msg->status is set to negative error
823 * number, otherwise it contains zero (and @msg->actual_length is updated).
825 static void ep93xx_spi_work(struct work_struct *work)
827 struct ep93xx_spi *espi = work_to_espi(work);
828 struct spi_message *msg;
830 spin_lock_irq(&espi->lock);
831 if (!espi->running || espi->current_msg ||
832 list_empty(&espi->msg_queue)) {
833 spin_unlock_irq(&espi->lock);
836 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
837 list_del_init(&msg->queue);
838 espi->current_msg = msg;
839 spin_unlock_irq(&espi->lock);
841 ep93xx_spi_process_message(espi, msg);
844 * Update the current message and re-schedule ourselves if there are
845 * more messages in the queue.
847 spin_lock_irq(&espi->lock);
848 espi->current_msg = NULL;
849 if (espi->running && !list_empty(&espi->msg_queue))
850 queue_work(espi->wq, &espi->msg_work);
851 spin_unlock_irq(&espi->lock);
853 /* notify the protocol driver that we are done with this message */
854 msg->complete(msg->context);
857 static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
859 struct ep93xx_spi *espi = dev_id;
860 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
863 * If we got ROR (receive overrun) interrupt we know that something is
864 * wrong. Just abort the message.
866 if (unlikely(irq_status & SSPIIR_RORIS)) {
867 /* clear the overrun interrupt */
868 ep93xx_spi_write_u8(espi, SSPICR, 0);
869 dev_warn(&espi->pdev->dev,
870 "receive overrun, aborting the message\n");
871 espi->current_msg->status = -EIO;
874 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
875 * simply execute next data transfer.
877 if (ep93xx_spi_read_write(espi)) {
879 * In normal case, there still is some processing left
880 * for current transfer. Let's wait for the next
888 * Current transfer is finished, either with error or with success. In
889 * any case we disable interrupts and notify the worker to handle
890 * any post-processing of the message.
892 ep93xx_spi_disable_interrupts(espi);
893 complete(&espi->wait);
897 static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
899 if (ep93xx_dma_chan_is_m2p(chan))
902 chan->private = filter_param;
906 static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
911 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
916 dma_cap_set(DMA_SLAVE, mask);
918 espi->dma_rx_data.port = EP93XX_DMA_SSP;
919 espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
920 espi->dma_rx_data.name = "ep93xx-spi-rx";
922 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
929 espi->dma_tx_data.port = EP93XX_DMA_SSP;
930 espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
931 espi->dma_tx_data.name = "ep93xx-spi-tx";
933 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
937 goto fail_release_rx;
943 dma_release_channel(espi->dma_rx);
946 free_page((unsigned long)espi->zeropage);
951 static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
954 dma_release_channel(espi->dma_rx);
955 sg_free_table(&espi->rx_sgt);
958 dma_release_channel(espi->dma_tx);
959 sg_free_table(&espi->tx_sgt);
963 free_page((unsigned long)espi->zeropage);
966 static int ep93xx_spi_probe(struct platform_device *pdev)
968 struct spi_master *master;
969 struct ep93xx_spi_info *info;
970 struct ep93xx_spi *espi;
971 struct resource *res;
975 info = pdev->dev.platform_data;
977 irq = platform_get_irq(pdev, 0);
979 dev_err(&pdev->dev, "failed to get irq resources\n");
983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
985 dev_err(&pdev->dev, "unable to get iomem resource\n");
989 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
993 master->setup = ep93xx_spi_setup;
994 master->transfer = ep93xx_spi_transfer;
995 master->cleanup = ep93xx_spi_cleanup;
996 master->bus_num = pdev->id;
997 master->num_chipselect = info->num_chipselect;
998 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
999 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1001 platform_set_drvdata(pdev, master);
1003 espi = spi_master_get_devdata(master);
1005 espi->clk = devm_clk_get(&pdev->dev, NULL);
1006 if (IS_ERR(espi->clk)) {
1007 dev_err(&pdev->dev, "unable to get spi clock\n");
1008 error = PTR_ERR(espi->clk);
1009 goto fail_release_master;
1012 spin_lock_init(&espi->lock);
1013 init_completion(&espi->wait);
1016 * Calculate maximum and minimum supported clock rates
1017 * for the controller.
1019 espi->max_rate = clk_get_rate(espi->clk) / 2;
1020 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1023 espi->sspdr_phys = res->start + SSPDR;
1025 espi->regs_base = devm_ioremap_resource(&pdev->dev, res);
1026 if (IS_ERR(espi->regs_base)) {
1027 error = PTR_ERR(espi->regs_base);
1028 goto fail_release_master;
1031 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
1032 0, "ep93xx-spi", espi);
1034 dev_err(&pdev->dev, "failed to request irq\n");
1035 goto fail_release_master;
1038 if (info->use_dma && ep93xx_spi_setup_dma(espi))
1039 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
1041 espi->wq = create_singlethread_workqueue("ep93xx_spid");
1043 dev_err(&pdev->dev, "unable to create workqueue\n");
1047 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
1048 INIT_LIST_HEAD(&espi->msg_queue);
1049 espi->running = true;
1051 /* make sure that the hardware is disabled */
1052 ep93xx_spi_write_u8(espi, SSPCR1, 0);
1054 error = spi_register_master(master);
1056 dev_err(&pdev->dev, "failed to register SPI master\n");
1057 goto fail_free_queue;
1060 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1061 (unsigned long)res->start, irq);
1066 destroy_workqueue(espi->wq);
1068 ep93xx_spi_release_dma(espi);
1069 fail_release_master:
1070 spi_master_put(master);
1075 static int ep93xx_spi_remove(struct platform_device *pdev)
1077 struct spi_master *master = platform_get_drvdata(pdev);
1078 struct ep93xx_spi *espi = spi_master_get_devdata(master);
1080 spin_lock_irq(&espi->lock);
1081 espi->running = false;
1082 spin_unlock_irq(&espi->lock);
1084 destroy_workqueue(espi->wq);
1087 * Complete remaining messages with %-ESHUTDOWN status.
1089 spin_lock_irq(&espi->lock);
1090 while (!list_empty(&espi->msg_queue)) {
1091 struct spi_message *msg;
1093 msg = list_first_entry(&espi->msg_queue,
1094 struct spi_message, queue);
1095 list_del_init(&msg->queue);
1096 msg->status = -ESHUTDOWN;
1097 spin_unlock_irq(&espi->lock);
1098 msg->complete(msg->context);
1099 spin_lock_irq(&espi->lock);
1101 spin_unlock_irq(&espi->lock);
1103 ep93xx_spi_release_dma(espi);
1105 spi_unregister_master(master);
1109 static struct platform_driver ep93xx_spi_driver = {
1111 .name = "ep93xx-spi",
1112 .owner = THIS_MODULE,
1114 .probe = ep93xx_spi_probe,
1115 .remove = ep93xx_spi_remove,
1117 module_platform_driver(ep93xx_spi_driver);
1119 MODULE_DESCRIPTION("EP93xx SPI Controller driver");
1120 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1121 MODULE_LICENSE("GPL");
1122 MODULE_ALIAS("platform:ep93xx-spi");