drivers/spi/spi-fsl-spi.c

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * GRLIB support:
  14  * Copyright (c) 2012 Aeroflex Gaisler AB.
  15  * Author: Andreas Larsson <andreas@gaisler.com>
  16  *
  17  * This program is free software; you can redistribute  it and/or modify it
  18  * under  the terms of  the GNU General  Public License as published by the
  19  * Free Software Foundation;  either version 2 of the  License, or (at your
  20  * option) any later version.
  21  */
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/gpio.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/kernel.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mutex.h>
  32 #include <linux/of.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/spi/spi_bitbang.h>
  40 #include <linux/types.h>
  41
  42 #include "spi-fsl-lib.h"
  43 #include "spi-fsl-cpm.h"
  44 #include "spi-fsl-spi.h"
  45
  46 #define TYPE_FSL        0
  47 #define TYPE_GRLIB      1
  48
  49 struct fsl_spi_match_data {
  50         int type;
  51 };
  52
  53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  54         .type = TYPE_FSL,
  55 };
  56
  57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  58         .type = TYPE_GRLIB,
  59 };
  60
  61 static const struct of_device_id of_fsl_spi_match[] = {
  62         {
  63                 .compatible = "fsl,spi",
  64                 .data = &of_fsl_spi_fsl_config,
  65         },
  66         {
  67                 .compatible = "aeroflexgaisler,spictrl",
  68                 .data = &of_fsl_spi_grlib_config,
  69         },
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  73
  74 static int fsl_spi_get_type(struct device *dev)
  75 {
  76         const struct of_device_id *match;
  77
  78         if (dev->of_node) {
  79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  80                 if (match && match->data)
  81                         return ((struct fsl_spi_match_data *)match->data)->type;
  82         }
  83         return TYPE_FSL;
  84 }
  85
  86 static void fsl_spi_change_mode(struct spi_device *spi)
  87 {
  88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  90         struct fsl_spi_reg *reg_base = mspi->reg_base;
  91         __be32 __iomem *mode = &reg_base->mode;
  92         unsigned long flags;
  93
  94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  95                 return;
  96
  97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  98         local_irq_save(flags);
  99
 100         /* Turn off SPI unit prior changing mode */
 101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 102
 103         /* When in CPM mode, we need to reinit tx and rx. */
 104         if (mspi->flags & SPI_CPM_MODE) {
 105                 fsl_spi_cpm_reinit_txrx(mspi);
 106         }
 107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 108         local_irq_restore(flags);
 109 }
 110
 111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 112 {
 113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 114         struct fsl_spi_platform_data *pdata;
 115         bool pol = spi->mode & SPI_CS_HIGH;
 116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 117
 118         pdata = spi->dev.parent->parent->platform_data;
 119
 120         if (value == BITBANG_CS_INACTIVE) {
 121                 if (pdata->cs_control)
 122                         pdata->cs_control(spi, !pol);
 123         }
 124
 125         if (value == BITBANG_CS_ACTIVE) {
 126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 128                 mpc8xxx_spi->get_rx = cs->get_rx;
 129                 mpc8xxx_spi->get_tx = cs->get_tx;
 130
 131                 fsl_spi_change_mode(spi);
 132
 133                 if (pdata->cs_control)
 134                         pdata->cs_control(spi, pol);
 135         }
 136 }
 137
 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 139                                       int bits_per_word, int msb_first)
 140 {
 141         *rx_shift = 0;
 142         *tx_shift = 0;
 143         if (msb_first) {
 144                 if (bits_per_word <= 8) {
 145                         *rx_shift = 16;
 146                         *tx_shift = 24;
 147                 } else if (bits_per_word <= 16) {
 148                         *rx_shift = 16;
 149                         *tx_shift = 16;
 150                 }
 151         } else {
 152                 if (bits_per_word <= 8)
 153                         *rx_shift = 8;
 154         }
 155 }
 156
 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 158                                      int bits_per_word, int msb_first)
 159 {
 160         *rx_shift = 0;
 161         *tx_shift = 0;
 162         if (bits_per_word <= 16) {
 163                 if (msb_first) {
 164                         *rx_shift = 16; /* LSB in bit 16 */
 165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 166                 } else {
 167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 168                 }
 169         }
 170 }
 171
 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 173                                 struct spi_device *spi,
 174                                 struct mpc8xxx_spi *mpc8xxx_spi,
 175                                 int bits_per_word)
 176 {
 177         cs->rx_shift = 0;
 178         cs->tx_shift = 0;
 179         if (bits_per_word <= 8) {
 180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 182         } else if (bits_per_word <= 16) {
 183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 185         } else if (bits_per_word <= 32) {
 186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 188         } else
 189                 return -EINVAL;
 190
 191         if (mpc8xxx_spi->set_shifts)
 192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 193                                         bits_per_word,
 194                                         !(spi->mode & SPI_LSB_FIRST));
 195
 196         mpc8xxx_spi->rx_shift = cs->rx_shift;
 197         mpc8xxx_spi->tx_shift = cs->tx_shift;
 198         mpc8xxx_spi->get_rx = cs->get_rx;
 199         mpc8xxx_spi->get_tx = cs->get_tx;
 200
 201         return bits_per_word;
 202 }
 203
 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 205                                 struct spi_device *spi,
 206                                 int bits_per_word)
 207 {
 208         /* QE uses Little Endian for words > 8
 209          * so transform all words > 8 into 8 bits
 210          * Unfortnatly that doesn't work for LSB so
 211          * reject these for now */
 212         /* Note: 32 bits word, LSB works iff
 213          * tfcr/rfcr is set to CPMFCR_GBL */
 214         if (spi->mode & SPI_LSB_FIRST &&
 215             bits_per_word > 8)
 216                 return -EINVAL;
 217         if (bits_per_word > 8)
 218                 return 8; /* pretend its 8 bits */
 219         return bits_per_word;
 220 }
 221
 222 static int fsl_spi_setup_transfer(struct spi_device *spi,
 223                                         struct spi_transfer *t)
 224 {
 225         struct mpc8xxx_spi *mpc8xxx_spi;
 226         int bits_per_word = 0;
 227         u8 pm;
 228         u32 hz = 0;
 229         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 230
 231         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 232
 233         if (t) {
 234                 bits_per_word = t->bits_per_word;
 235                 hz = t->speed_hz;
 236         }
 237
 238         /* spi_transfer level calls that work per-word */
 239         if (!bits_per_word)
 240                 bits_per_word = spi->bits_per_word;
 241
 242         if (!hz)
 243                 hz = spi->max_speed_hz;
 244
 245         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 246                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 247                                                            mpc8xxx_spi,
 248                                                            bits_per_word);
 249         else if (mpc8xxx_spi->flags & SPI_QE)
 250                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 251                                                           bits_per_word);
 252
 253         if (bits_per_word < 0)
 254                 return bits_per_word;
 255
 256         if (bits_per_word == 32)
 257                 bits_per_word = 0;
 258         else
 259                 bits_per_word = bits_per_word - 1;
 260
 261         /* mask out bits we are going to set */
 262         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 263                                   | SPMODE_PM(0xF));
 264
 265         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 266
 267         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 268                 cs->hw_mode |= SPMODE_DIV16;
 269                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 270
 271                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 272                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 273                           hz, mpc8xxx_spi->spibrg / 1024);
 274                 if (pm > 16)
 275                         pm = 16;
 276         } else {
 277                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 278         }
 279         if (pm)
 280                 pm--;
 281
 282         cs->hw_mode |= SPMODE_PM(pm);
 283
 284         fsl_spi_change_mode(spi);
 285         return 0;
 286 }
 287
 288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 289                                 struct spi_transfer *t, unsigned int len)
 290 {
 291         u32 word;
 292         struct fsl_spi_reg *reg_base = mspi->reg_base;
 293
 294         mspi->count = len;
 295
 296         /* enable rx ints */
 297         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 298
 299         /* transmit word */
 300         word = mspi->get_tx(mspi);
 301         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 302
 303         return 0;
 304 }
 305
 306 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 307                             bool is_dma_mapped)
 308 {
 309         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 310         struct fsl_spi_reg *reg_base;
 311         unsigned int len = t->len;
 312         u8 bits_per_word;
 313         int ret;
 314
 315         reg_base = mpc8xxx_spi->reg_base;
 316         bits_per_word = spi->bits_per_word;
 317         if (t->bits_per_word)
 318                 bits_per_word = t->bits_per_word;
 319
 320         if (bits_per_word > 8) {
 321                 /* invalid length? */
 322                 if (len & 1)
 323                         return -EINVAL;
 324                 len /= 2;
 325         }
 326         if (bits_per_word > 16) {
 327                 /* invalid length? */
 328                 if (len & 1)
 329                         return -EINVAL;
 330                 len /= 2;
 331         }
 332
 333         mpc8xxx_spi->tx = t->tx_buf;
 334         mpc8xxx_spi->rx = t->rx_buf;
 335
 336         reinit_completion(&mpc8xxx_spi->done);
 337
 338         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 339                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 340         else
 341                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 342         if (ret)
 343                 return ret;
 344
 345         wait_for_completion(&mpc8xxx_spi->done);
 346
 347         /* disable rx ints */
 348         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 349
 350         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 351                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 352
 353         return mpc8xxx_spi->count;
 354 }
 355
 356 static int fsl_spi_do_one_msg(struct spi_master *master,
 357                               struct spi_message *m)
 358 {
 359         struct spi_device *spi = m->spi;
 360         struct spi_transfer *t, *first;
 361         unsigned int cs_change;
 362         const int nsecs = 50;
 363         int status;
 364
 365         /* Don't allow changes if CS is active */
 366         first = list_first_entry(&m->transfers, struct spi_transfer,
 367                         transfer_list);
 368         list_for_each_entry(t, &m->transfers, transfer_list) {
 369                 if ((first->bits_per_word != t->bits_per_word) ||
 370                         (first->speed_hz != t->speed_hz)) {
 371                         dev_err(&spi->dev,
 372                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
 373                         return -EINVAL;
 374                 }
 375         }
 376
 377         cs_change = 1;
 378         status = -EINVAL;
 379         list_for_each_entry(t, &m->transfers, transfer_list) {
 380                 if (t->bits_per_word || t->speed_hz) {
 381                         if (cs_change)
 382                                 status = fsl_spi_setup_transfer(spi, t);
 383                         if (status < 0)
 384                                 break;
 385                 }
 386
 387                 if (cs_change) {
 388                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 389                         ndelay(nsecs);
 390                 }
 391                 cs_change = t->cs_change;
 392                 if (t->len)
 393                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 394                 if (status) {
 395                         status = -EMSGSIZE;
 396                         break;
 397                 }
 398                 m->actual_length += t->len;
 399
 400                 if (t->delay_usecs)
 401                         udelay(t->delay_usecs);
 402
 403                 if (cs_change) {
 404                         ndelay(nsecs);
 405                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 406                         ndelay(nsecs);
 407                 }
 408         }
 409
 410         m->status = status;
 411         spi_finalize_current_message(master);
 412
 413         if (status || !cs_change) {
 414                 ndelay(nsecs);
 415                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 416         }
 417
 418         fsl_spi_setup_transfer(spi, NULL);
 419         return 0;
 420 }
 421
 422 static int fsl_spi_setup(struct spi_device *spi)
 423 {
 424         struct mpc8xxx_spi *mpc8xxx_spi;
 425         struct fsl_spi_reg *reg_base;
 426         int retval;
 427         u32 hw_mode;
 428         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 429
 430         if (!spi->max_speed_hz)
 431                 return -EINVAL;
 432
 433         if (!cs) {
 434                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 435                 if (!cs)
 436                         return -ENOMEM;
 437                 spi_set_ctldata(spi, cs);
 438         }
 439         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 440
 441         reg_base = mpc8xxx_spi->reg_base;
 442
 443         hw_mode = cs->hw_mode; /* Save original settings */
 444         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 445         /* mask out bits we are going to set */
 446         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 447                          | SPMODE_REV | SPMODE_LOOP);
 448
 449         if (spi->mode & SPI_CPHA)
 450                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 451         if (spi->mode & SPI_CPOL)
 452                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 453         if (!(spi->mode & SPI_LSB_FIRST))
 454                 cs->hw_mode |= SPMODE_REV;
 455         if (spi->mode & SPI_LOOP)
 456                 cs->hw_mode |= SPMODE_LOOP;
 457
 458         retval = fsl_spi_setup_transfer(spi, NULL);
 459         if (retval < 0) {
 460                 cs->hw_mode = hw_mode; /* Restore settings */
 461                 return retval;
 462         }
 463
 464         if (mpc8xxx_spi->type == TYPE_GRLIB) {
 465                 if (gpio_is_valid(spi->cs_gpio)) {
 466                         int desel;
 467
 468                         retval = gpio_request(spi->cs_gpio,
 469                                               dev_name(&spi->dev));
 470                         if (retval)
 471                                 return retval;
 472
 473                         desel = !(spi->mode & SPI_CS_HIGH);
 474                         retval = gpio_direction_output(spi->cs_gpio, desel);
 475                         if (retval) {
 476                                 gpio_free(spi->cs_gpio);
 477                                 return retval;
 478                         }
 479                 } else if (spi->cs_gpio != -ENOENT) {
 480                         if (spi->cs_gpio < 0)
 481                                 return spi->cs_gpio;
 482                         return -EINVAL;
 483                 }
 484                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
 485                  * indicates to use native chipselect if present, or allow for
 486                  * an always selected chip
 487                  */
 488         }
 489
 490         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 491         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 492
 493         return 0;
 494 }
 495
 496 static void fsl_spi_cleanup(struct spi_device *spi)
 497 {
 498         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 499         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 500
 501         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
 502                 gpio_free(spi->cs_gpio);
 503
 504         kfree(cs);
 505         spi_set_ctldata(spi, NULL);
 506 }
 507
 508 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 509 {
 510         struct fsl_spi_reg *reg_base = mspi->reg_base;
 511
 512         /* We need handle RX first */
 513         if (events & SPIE_NE) {
 514                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 515
 516                 if (mspi->rx)
 517                         mspi->get_rx(rx_data, mspi);
 518         }
 519
 520         if ((events & SPIE_NF) == 0)
 521                 /* spin until TX is done */
 522                 while (((events =
 523                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 524                                                 SPIE_NF) == 0)
 525                         cpu_relax();
 526
 527         /* Clear the events */
 528         mpc8xxx_spi_write_reg(&reg_base->event, events);
 529
 530         mspi->count -= 1;
 531         if (mspi->count) {
 532                 u32 word = mspi->get_tx(mspi);
 533
 534                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 535         } else {
 536                 complete(&mspi->done);
 537         }
 538 }
 539
 540 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 541 {
 542         struct mpc8xxx_spi *mspi = context_data;
 543         irqreturn_t ret = IRQ_NONE;
 544         u32 events;
 545         struct fsl_spi_reg *reg_base = mspi->reg_base;
 546
 547         /* Get interrupt events(tx/rx) */
 548         events = mpc8xxx_spi_read_reg(&reg_base->event);
 549         if (events)
 550                 ret = IRQ_HANDLED;
 551
 552         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 553
 554         if (mspi->flags & SPI_CPM_MODE)
 555                 fsl_spi_cpm_irq(mspi, events);
 556         else
 557                 fsl_spi_cpu_irq(mspi, events);
 558
 559         return ret;
 560 }
 561
 562 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
 563 {
 564         fsl_spi_cpm_free(mspi);
 565 }
 566
 567 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 568 {
 569         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 570         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 571         u32 slvsel;
 572         u16 cs = spi->chip_select;
 573
 574         if (gpio_is_valid(spi->cs_gpio)) {
 575                 gpio_set_value(spi->cs_gpio, on);
 576         } else if (cs < mpc8xxx_spi->native_chipselects) {
 577                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 578                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 579                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 580         }
 581 }
 582
 583 static void fsl_spi_grlib_probe(struct device *dev)
 584 {
 585         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 586         struct spi_master *master = dev_get_drvdata(dev);
 587         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 588         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 589         int mbits;
 590         u32 capabilities;
 591
 592         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 593
 594         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 595         mbits = SPCAP_MAXWLEN(capabilities);
 596         if (mbits)
 597                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 598
 599         mpc8xxx_spi->native_chipselects = 0;
 600         if (SPCAP_SSEN(capabilities)) {
 601                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 602                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 603         }
 604         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 605         pdata->cs_control = fsl_spi_grlib_cs_control;
 606 }
 607
 608 static struct spi_master * fsl_spi_probe(struct device *dev,
 609                 struct resource *mem, unsigned int irq)
 610 {
 611         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 612         struct spi_master *master;
 613         struct mpc8xxx_spi *mpc8xxx_spi;
 614         struct fsl_spi_reg *reg_base;
 615         u32 regval;
 616         int ret = 0;
 617
 618         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 619         if (master == NULL) {
 620                 ret = -ENOMEM;
 621                 goto err;
 622         }
 623
 624         dev_set_drvdata(dev, master);
 625
 626         mpc8xxx_spi_probe(dev, mem, irq);
 627
 628         master->setup = fsl_spi_setup;
 629         master->cleanup = fsl_spi_cleanup;
 630         master->transfer_one_message = fsl_spi_do_one_msg;
 631
 632         mpc8xxx_spi = spi_master_get_devdata(master);
 633         mpc8xxx_spi->spi_remove = fsl_spi_remove;
 634         mpc8xxx_spi->max_bits_per_word = 32;
 635         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 636
 637         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 638         if (ret)
 639                 goto err_cpm_init;
 640
 641         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 642         if (mpc8xxx_spi->reg_base == NULL) {
 643                 ret = -ENOMEM;
 644                 goto err_probe;
 645         }
 646
 647         if (mpc8xxx_spi->type == TYPE_GRLIB)
 648                 fsl_spi_grlib_probe(dev);
 649
 650         master->bits_per_word_mask =
 651                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 652                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 653
 654         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 655                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 656
 657         if (mpc8xxx_spi->set_shifts)
 658                 /* 8 bits per word and MSB first */
 659                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 660                                         &mpc8xxx_spi->tx_shift, 8, 1);
 661
 662         /* Register for SPI Interrupt */
 663         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 664                                0, "fsl_spi", mpc8xxx_spi);
 665
 666         if (ret != 0)
 667                 goto err_probe;
 668
 669         reg_base = mpc8xxx_spi->reg_base;
 670
 671         /* SPI controller initializations */
 672         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 673         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 674         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 675         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 676
 677         /* Enable SPI interface */
 678         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 679         if (mpc8xxx_spi->max_bits_per_word < 8) {
 680                 regval &= ~SPMODE_LEN(0xF);
 681                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 682         }
 683         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 684                 regval |= SPMODE_OP;
 685
 686         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 687
 688         ret = devm_spi_register_master(dev, master);
 689         if (ret < 0)
 690                 goto err_probe;
 691
 692         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 693                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 694
 695         return master;
 696
 697 err_probe:
 698         fsl_spi_cpm_free(mpc8xxx_spi);
 699 err_cpm_init:
 700         spi_master_put(master);
 701 err:
 702         return ERR_PTR(ret);
 703 }
 704
 705 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 706 {
 707         struct device *dev = spi->dev.parent->parent;
 708         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 709         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 710         u16 cs = spi->chip_select;
 711         int gpio = pinfo->gpios[cs];
 712         bool alow = pinfo->alow_flags[cs];
 713
 714         gpio_set_value(gpio, on ^ alow);
 715 }
 716
 717 static int of_fsl_spi_get_chipselects(struct device *dev)
 718 {
 719         struct device_node *np = dev->of_node;
 720         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 721         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 722         int ngpios;
 723         int i = 0;
 724         int ret;
 725
 726         ngpios = of_gpio_count(np);
 727         if (ngpios <= 0) {
 728                 /*
 729                  * SPI w/o chip-select line. One SPI device is still permitted
 730                  * though.
 731                  */
 732                 pdata->max_chipselect = 1;
 733                 return 0;
 734         }
 735
 736         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 737         if (!pinfo->gpios)
 738                 return -ENOMEM;
 739         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 740
 741         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 742                                     GFP_KERNEL);
 743         if (!pinfo->alow_flags) {
 744                 ret = -ENOMEM;
 745                 goto err_alloc_flags;
 746         }
 747
 748         for (; i < ngpios; i++) {
 749                 int gpio;
 750                 enum of_gpio_flags flags;
 751
 752                 gpio = of_get_gpio_flags(np, i, &flags);
 753                 if (!gpio_is_valid(gpio)) {
 754                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 755                         ret = gpio;
 756                         goto err_loop;
 757                 }
 758
 759                 ret = gpio_request(gpio, dev_name(dev));
 760                 if (ret) {
 761                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 762                         goto err_loop;
 763                 }
 764
 765                 pinfo->gpios[i] = gpio;
 766                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 767
 768                 ret = gpio_direction_output(pinfo->gpios[i],
 769                                             pinfo->alow_flags[i]);
 770                 if (ret) {
 771                         dev_err(dev, "can't set output direction for gpio "
 772                                 "#%d: %d\n", i, ret);
 773                         goto err_loop;
 774                 }
 775         }
 776
 777         pdata->max_chipselect = ngpios;
 778         pdata->cs_control = fsl_spi_cs_control;
 779
 780         return 0;
 781
 782 err_loop:
 783         while (i >= 0) {
 784                 if (gpio_is_valid(pinfo->gpios[i]))
 785                         gpio_free(pinfo->gpios[i]);
 786                 i--;
 787         }
 788
 789         kfree(pinfo->alow_flags);
 790         pinfo->alow_flags = NULL;
 791 err_alloc_flags:
 792         kfree(pinfo->gpios);
 793         pinfo->gpios = NULL;
 794         return ret;
 795 }
 796
 797 static int of_fsl_spi_free_chipselects(struct device *dev)
 798 {
 799         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 800         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 801         int i;
 802
 803         if (!pinfo->gpios)
 804                 return 0;
 805
 806         for (i = 0; i < pdata->max_chipselect; i++) {
 807                 if (gpio_is_valid(pinfo->gpios[i]))
 808                         gpio_free(pinfo->gpios[i]);
 809         }
 810
 811         kfree(pinfo->gpios);
 812         kfree(pinfo->alow_flags);
 813         return 0;
 814 }
 815
 816 static int of_fsl_spi_probe(struct platform_device *ofdev)
 817 {
 818         struct device *dev = &ofdev->dev;
 819         struct device_node *np = ofdev->dev.of_node;
 820         struct spi_master *master;
 821         struct resource mem;
 822         int irq, type;
 823         int ret = -ENOMEM;
 824
 825         ret = of_mpc8xxx_spi_probe(ofdev);
 826         if (ret)
 827                 return ret;
 828
 829         type = fsl_spi_get_type(&ofdev->dev);
 830         if (type == TYPE_FSL) {
 831                 ret = of_fsl_spi_get_chipselects(dev);
 832                 if (ret)
 833                         goto err;
 834         }
 835
 836         ret = of_address_to_resource(np, 0, &mem);
 837         if (ret)
 838                 goto err;
 839
 840         irq = irq_of_parse_and_map(np, 0);
 841         if (!irq) {
 842                 ret = -EINVAL;
 843                 goto err;
 844         }
 845
 846         master = fsl_spi_probe(dev, &mem, irq);
 847         if (IS_ERR(master)) {
 848                 ret = PTR_ERR(master);
 849                 goto err;
 850         }
 851
 852         return 0;
 853
 854 err:
 855         if (type == TYPE_FSL)
 856                 of_fsl_spi_free_chipselects(dev);
 857         return ret;
 858 }
 859
 860 static int of_fsl_spi_remove(struct platform_device *ofdev)
 861 {
 862         struct spi_master *master = platform_get_drvdata(ofdev);
 863         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 864         int ret;
 865
 866         ret = mpc8xxx_spi_remove(&ofdev->dev);
 867         if (ret)
 868                 return ret;
 869         if (mpc8xxx_spi->type == TYPE_FSL)
 870                 of_fsl_spi_free_chipselects(&ofdev->dev);
 871         return 0;
 872 }
 873
 874 static struct platform_driver of_fsl_spi_driver = {
 875         .driver = {
 876                 .name = "fsl_spi",
 877                 .of_match_table = of_fsl_spi_match,
 878         },
 879         .probe          = of_fsl_spi_probe,
 880         .remove         = of_fsl_spi_remove,
 881 };
 882
 883 #ifdef CONFIG_MPC832x_RDB
 884 /*
 885  * XXX XXX XXX
 886  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 887  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 888  * tree can work with OpenFirmware driver. But for now we support old trees
 889  * as well.
 890  */
 891 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 892 {
 893         struct resource *mem;
 894         int irq;
 895         struct spi_master *master;
 896
 897         if (!dev_get_platdata(&pdev->dev))
 898                 return -EINVAL;
 899
 900         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         if (!mem)
 902                 return -EINVAL;
 903
 904         irq = platform_get_irq(pdev, 0);
 905         if (irq <= 0)
 906                 return -EINVAL;
 907
 908         master = fsl_spi_probe(&pdev->dev, mem, irq);
 909         return PTR_ERR_OR_ZERO(master);
 910 }
 911
 912 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 913 {
 914         return mpc8xxx_spi_remove(&pdev->dev);
 915 }
 916
 917 MODULE_ALIAS("platform:mpc8xxx_spi");
 918 static struct platform_driver mpc8xxx_spi_driver = {
 919         .probe = plat_mpc8xxx_spi_probe,
 920         .remove = plat_mpc8xxx_spi_remove,
 921         .driver = {
 922                 .name = "mpc8xxx_spi",
 923         },
 924 };
 925
 926 static bool legacy_driver_failed;
 927
 928 static void __init legacy_driver_register(void)
 929 {
 930         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 931 }
 932
 933 static void __exit legacy_driver_unregister(void)
 934 {
 935         if (legacy_driver_failed)
 936                 return;
 937         platform_driver_unregister(&mpc8xxx_spi_driver);
 938 }
 939 #else
 940 static void __init legacy_driver_register(void) {}
 941 static void __exit legacy_driver_unregister(void) {}
 942 #endif /* CONFIG_MPC832x_RDB */
 943
 944 static int __init fsl_spi_init(void)
 945 {
 946         legacy_driver_register();
 947         return platform_driver_register(&of_fsl_spi_driver);
 948 }
 949 module_init(fsl_spi_init);
 950
 951 static void __exit fsl_spi_exit(void)
 952 {
 953         platform_driver_unregister(&of_fsl_spi_driver);
 954         legacy_driver_unregister();
 955 }
 956 module_exit(fsl_spi_exit);
 957
 958 MODULE_AUTHOR("Kumar Gala");
 959 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 960 MODULE_LICENSE("GPL");