2 * IMG SPFI controller driver
4 * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/scatterlist.h>
24 #include <linux/slab.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spinlock.h>
28 #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
29 #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
30 #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
31 #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
32 #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
33 #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
34 #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
35 #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
36 #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
38 #define SPFI_CONTROL 0x14
39 #define SPFI_CONTROL_CONTINUE BIT(12)
40 #define SPFI_CONTROL_SOFT_RESET BIT(11)
41 #define SPFI_CONTROL_SEND_DMA BIT(10)
42 #define SPFI_CONTROL_GET_DMA BIT(9)
43 #define SPFI_CONTROL_TMODE_SHIFT 5
44 #define SPFI_CONTROL_TMODE_MASK 0x7
45 #define SPFI_CONTROL_TMODE_SINGLE 0
46 #define SPFI_CONTROL_TMODE_DUAL 1
47 #define SPFI_CONTROL_TMODE_QUAD 2
48 #define SPFI_CONTROL_SPFI_EN BIT(0)
50 #define SPFI_TRANSACTION 0x18
51 #define SPFI_TRANSACTION_TSIZE_SHIFT 16
52 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
54 #define SPFI_PORT_STATE 0x1c
55 #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
56 #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
57 #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
58 #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
60 #define SPFI_TX_32BIT_VALID_DATA 0x20
61 #define SPFI_TX_8BIT_VALID_DATA 0x24
62 #define SPFI_RX_32BIT_VALID_DATA 0x28
63 #define SPFI_RX_8BIT_VALID_DATA 0x2c
65 #define SPFI_INTERRUPT_STATUS 0x30
66 #define SPFI_INTERRUPT_ENABLE 0x34
67 #define SPFI_INTERRUPT_CLEAR 0x38
68 #define SPFI_INTERRUPT_IACCESS BIT(12)
69 #define SPFI_INTERRUPT_GDEX8BIT BIT(11)
70 #define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
71 #define SPFI_INTERRUPT_GDFUL BIT(8)
72 #define SPFI_INTERRUPT_GDHF BIT(7)
73 #define SPFI_INTERRUPT_GDEX32BIT BIT(6)
74 #define SPFI_INTERRUPT_GDTRIG BIT(5)
75 #define SPFI_INTERRUPT_SDFUL BIT(3)
76 #define SPFI_INTERRUPT_SDHF BIT(2)
77 #define SPFI_INTERRUPT_SDE BIT(1)
78 #define SPFI_INTERRUPT_SDTRIG BIT(0)
81 * There are four parallel FIFOs of 16 bytes each. The word buffer
82 * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
83 * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
84 * accesses only a single FIFO, resulting in an effective FIFO size of
87 #define SPFI_32BIT_FIFO_SIZE 64
88 #define SPFI_8BIT_FIFO_SIZE 16
92 struct spi_master *master;
101 struct dma_chan *rx_ch;
102 struct dma_chan *tx_ch;
107 static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
109 return readl(spfi->regs + reg);
112 static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
114 writel(val, spfi->regs + reg);
117 static inline void spfi_start(struct img_spfi *spfi)
121 val = spfi_readl(spfi, SPFI_CONTROL);
122 val |= SPFI_CONTROL_SPFI_EN;
123 spfi_writel(spfi, val, SPFI_CONTROL);
126 static inline void spfi_reset(struct img_spfi *spfi)
128 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
129 spfi_writel(spfi, 0, SPFI_CONTROL);
132 static int spfi_wait_all_done(struct img_spfi *spfi)
134 unsigned long timeout = jiffies + msecs_to_jiffies(50);
136 while (time_before(jiffies, timeout)) {
137 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
139 if (status & SPFI_INTERRUPT_ALLDONETRIG) {
140 spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
141 SPFI_INTERRUPT_CLEAR);
147 dev_err(spfi->dev, "Timed out waiting for transaction to complete\n");
153 static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
156 unsigned int count = 0;
159 while (count < max / 4) {
160 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
161 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
162 if (status & SPFI_INTERRUPT_SDFUL)
164 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
171 static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
174 unsigned int count = 0;
177 while (count < max) {
178 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
179 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
180 if (status & SPFI_INTERRUPT_SDFUL)
182 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
189 static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
192 unsigned int count = 0;
195 while (count < max / 4) {
196 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
197 SPFI_INTERRUPT_CLEAR);
198 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
199 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
201 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
208 static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
211 unsigned int count = 0;
214 while (count < max) {
215 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
216 SPFI_INTERRUPT_CLEAR);
217 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
218 if (!(status & SPFI_INTERRUPT_GDEX8BIT))
220 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
227 static int img_spfi_start_pio(struct spi_master *master,
228 struct spi_device *spi,
229 struct spi_transfer *xfer)
231 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
232 unsigned int tx_bytes = 0, rx_bytes = 0;
233 const void *tx_buf = xfer->tx_buf;
234 void *rx_buf = xfer->rx_buf;
235 unsigned long timeout;
239 tx_bytes = xfer->len;
241 rx_bytes = xfer->len;
246 msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
247 while ((tx_bytes > 0 || rx_bytes > 0) &&
248 time_before(jiffies, timeout)) {
249 unsigned int tx_count, rx_count;
252 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
254 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
257 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
259 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
263 tx_bytes -= tx_count;
264 rx_bytes -= rx_count;
269 ret = spfi_wait_all_done(spfi);
273 if (rx_bytes > 0 || tx_bytes > 0) {
274 dev_err(spfi->dev, "PIO transfer timed out\n");
281 static void img_spfi_dma_rx_cb(void *data)
283 struct img_spfi *spfi = data;
286 spfi_wait_all_done(spfi);
288 spin_lock_irqsave(&spfi->lock, flags);
289 spfi->rx_dma_busy = false;
290 if (!spfi->tx_dma_busy)
291 spi_finalize_current_transfer(spfi->master);
292 spin_unlock_irqrestore(&spfi->lock, flags);
295 static void img_spfi_dma_tx_cb(void *data)
297 struct img_spfi *spfi = data;
300 spfi_wait_all_done(spfi);
302 spin_lock_irqsave(&spfi->lock, flags);
303 spfi->tx_dma_busy = false;
304 if (!spfi->rx_dma_busy)
305 spi_finalize_current_transfer(spfi->master);
306 spin_unlock_irqrestore(&spfi->lock, flags);
309 static int img_spfi_start_dma(struct spi_master *master,
310 struct spi_device *spi,
311 struct spi_transfer *xfer)
313 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
314 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
315 struct dma_slave_config rxconf, txconf;
317 spfi->rx_dma_busy = false;
318 spfi->tx_dma_busy = false;
321 rxconf.direction = DMA_DEV_TO_MEM;
322 if (xfer->len % 4 == 0) {
323 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
324 rxconf.src_addr_width = 4;
325 rxconf.src_maxburst = 4;
327 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
328 rxconf.src_addr_width = 1;
329 rxconf.src_maxburst = 4;
331 dmaengine_slave_config(spfi->rx_ch, &rxconf);
333 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
340 rxdesc->callback = img_spfi_dma_rx_cb;
341 rxdesc->callback_param = spfi;
345 txconf.direction = DMA_MEM_TO_DEV;
346 if (xfer->len % 4 == 0) {
347 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
348 txconf.dst_addr_width = 4;
349 txconf.dst_maxburst = 4;
351 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
352 txconf.dst_addr_width = 1;
353 txconf.dst_maxburst = 4;
355 dmaengine_slave_config(spfi->tx_ch, &txconf);
357 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
364 txdesc->callback = img_spfi_dma_tx_cb;
365 txdesc->callback_param = spfi;
369 spfi->rx_dma_busy = true;
370 dmaengine_submit(rxdesc);
371 dma_async_issue_pending(spfi->rx_ch);
377 spfi->tx_dma_busy = true;
378 dmaengine_submit(txdesc);
379 dma_async_issue_pending(spfi->tx_ch);
385 dmaengine_terminate_all(spfi->rx_ch);
386 dmaengine_terminate_all(spfi->tx_ch);
390 static void img_spfi_handle_err(struct spi_master *master,
391 struct spi_message *msg)
393 struct img_spfi *spfi = spi_master_get_devdata(master);
397 * Stop all DMA and reset the controller if the previous transaction
398 * timed-out and never completed it's DMA.
400 spin_lock_irqsave(&spfi->lock, flags);
401 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
402 spfi->tx_dma_busy = false;
403 spfi->rx_dma_busy = false;
405 dmaengine_terminate_all(spfi->tx_ch);
406 dmaengine_terminate_all(spfi->rx_ch);
408 spin_unlock_irqrestore(&spfi->lock, flags);
411 static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
413 struct img_spfi *spfi = spi_master_get_devdata(master);
416 val = spfi_readl(spfi, SPFI_PORT_STATE);
417 if (msg->spi->mode & SPI_CPHA)
418 val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
420 val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
421 if (msg->spi->mode & SPI_CPOL)
422 val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
424 val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
425 spfi_writel(spfi, val, SPFI_PORT_STATE);
430 static int img_spfi_unprepare(struct spi_master *master,
431 struct spi_message *msg)
433 struct img_spfi *spfi = spi_master_get_devdata(master);
440 static int img_spfi_setup(struct spi_device *spi)
444 ret = gpio_request_one(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ?
445 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
446 dev_name(&spi->dev));
448 dev_err(&spi->dev, "can't request chipselect gpio %d\n",
454 static void img_spfi_cleanup(struct spi_device *spi)
456 gpio_free(spi->cs_gpio);
459 static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
460 struct spi_transfer *xfer)
462 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
466 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
467 * power of 2 up to 128
469 div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
470 div = clamp(512 / (1 << get_count_order(div)), 1, 128);
472 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
473 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
474 SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
475 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
476 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
478 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
481 val = spfi_readl(spfi, SPFI_CONTROL);
482 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
484 val |= SPFI_CONTROL_SEND_DMA;
486 val |= SPFI_CONTROL_GET_DMA;
487 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
488 if (xfer->tx_nbits == SPI_NBITS_DUAL &&
489 xfer->rx_nbits == SPI_NBITS_DUAL)
490 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
491 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
492 xfer->rx_nbits == SPI_NBITS_QUAD)
493 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
494 spfi_writel(spfi, val, SPFI_CONTROL);
497 static int img_spfi_transfer_one(struct spi_master *master,
498 struct spi_device *spi,
499 struct spi_transfer *xfer)
501 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
504 if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
506 "Transfer length (%d) is greater than the max supported (%d)",
507 xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
511 img_spfi_config(master, spi, xfer);
512 if (master->can_dma && master->can_dma(master, spi, xfer))
513 ret = img_spfi_start_dma(master, spi, xfer);
515 ret = img_spfi_start_pio(master, spi, xfer);
520 static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
521 struct spi_transfer *xfer)
523 if (xfer->len > SPFI_32BIT_FIFO_SIZE)
528 static irqreturn_t img_spfi_irq(int irq, void *dev_id)
530 struct img_spfi *spfi = (struct img_spfi *)dev_id;
533 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
534 if (status & SPFI_INTERRUPT_IACCESS) {
535 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
536 dev_err(spfi->dev, "Illegal access interrupt");
543 static int img_spfi_probe(struct platform_device *pdev)
545 struct spi_master *master;
546 struct img_spfi *spfi;
547 struct resource *res;
550 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
553 platform_set_drvdata(pdev, master);
555 spfi = spi_master_get_devdata(master);
556 spfi->dev = &pdev->dev;
557 spfi->master = master;
558 spin_lock_init(&spfi->lock);
560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 spfi->regs = devm_ioremap_resource(spfi->dev, res);
562 if (IS_ERR(spfi->regs)) {
563 ret = PTR_ERR(spfi->regs);
566 spfi->phys = res->start;
568 spfi->irq = platform_get_irq(pdev, 0);
573 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
574 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
578 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
579 if (IS_ERR(spfi->sys_clk)) {
580 ret = PTR_ERR(spfi->sys_clk);
583 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
584 if (IS_ERR(spfi->spfi_clk)) {
585 ret = PTR_ERR(spfi->spfi_clk);
589 ret = clk_prepare_enable(spfi->sys_clk);
592 ret = clk_prepare_enable(spfi->spfi_clk);
598 * Only enable the error (IACCESS) interrupt. In PIO mode we'll
599 * poll the status of the FIFOs.
601 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
603 master->auto_runtime_pm = true;
604 master->bus_num = pdev->id;
605 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
606 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
607 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
608 master->dev.of_node = pdev->dev.of_node;
609 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
610 master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
611 master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
613 master->setup = img_spfi_setup;
614 master->cleanup = img_spfi_cleanup;
615 master->transfer_one = img_spfi_transfer_one;
616 master->prepare_message = img_spfi_prepare;
617 master->unprepare_message = img_spfi_unprepare;
618 master->handle_err = img_spfi_handle_err;
620 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
621 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
622 if (!spfi->tx_ch || !spfi->rx_ch) {
624 dma_release_channel(spfi->tx_ch);
626 dma_release_channel(spfi->rx_ch);
627 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
629 master->dma_tx = spfi->tx_ch;
630 master->dma_rx = spfi->rx_ch;
631 master->can_dma = img_spfi_can_dma;
634 pm_runtime_set_active(spfi->dev);
635 pm_runtime_enable(spfi->dev);
637 ret = devm_spi_register_master(spfi->dev, master);
644 pm_runtime_disable(spfi->dev);
646 dma_release_channel(spfi->rx_ch);
648 dma_release_channel(spfi->tx_ch);
649 clk_disable_unprepare(spfi->spfi_clk);
651 clk_disable_unprepare(spfi->sys_clk);
653 spi_master_put(master);
658 static int img_spfi_remove(struct platform_device *pdev)
660 struct spi_master *master = platform_get_drvdata(pdev);
661 struct img_spfi *spfi = spi_master_get_devdata(master);
664 dma_release_channel(spfi->tx_ch);
666 dma_release_channel(spfi->rx_ch);
668 pm_runtime_disable(spfi->dev);
669 if (!pm_runtime_status_suspended(spfi->dev)) {
670 clk_disable_unprepare(spfi->spfi_clk);
671 clk_disable_unprepare(spfi->sys_clk);
674 spi_master_put(master);
680 static int img_spfi_runtime_suspend(struct device *dev)
682 struct spi_master *master = dev_get_drvdata(dev);
683 struct img_spfi *spfi = spi_master_get_devdata(master);
685 clk_disable_unprepare(spfi->spfi_clk);
686 clk_disable_unprepare(spfi->sys_clk);
691 static int img_spfi_runtime_resume(struct device *dev)
693 struct spi_master *master = dev_get_drvdata(dev);
694 struct img_spfi *spfi = spi_master_get_devdata(master);
697 ret = clk_prepare_enable(spfi->sys_clk);
700 ret = clk_prepare_enable(spfi->spfi_clk);
702 clk_disable_unprepare(spfi->sys_clk);
708 #endif /* CONFIG_PM */
710 #ifdef CONFIG_PM_SLEEP
711 static int img_spfi_suspend(struct device *dev)
713 struct spi_master *master = dev_get_drvdata(dev);
715 return spi_master_suspend(master);
718 static int img_spfi_resume(struct device *dev)
720 struct spi_master *master = dev_get_drvdata(dev);
721 struct img_spfi *spfi = spi_master_get_devdata(master);
724 ret = pm_runtime_get_sync(dev);
730 return spi_master_resume(master);
732 #endif /* CONFIG_PM_SLEEP */
734 static const struct dev_pm_ops img_spfi_pm_ops = {
735 SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
737 SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
740 static const struct of_device_id img_spfi_of_match[] = {
741 { .compatible = "img,spfi", },
744 MODULE_DEVICE_TABLE(of, img_spfi_of_match);
746 static struct platform_driver img_spfi_driver = {
749 .pm = &img_spfi_pm_ops,
750 .of_match_table = of_match_ptr(img_spfi_of_match),
752 .probe = img_spfi_probe,
753 .remove = img_spfi_remove,
755 module_platform_driver(img_spfi_driver);
757 MODULE_DESCRIPTION("IMG SPFI controller driver");
758 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
759 MODULE_LICENSE("GPL v2");