2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/clk.h>
24 #include <linux/sizes.h>
25 #include <asm/unaligned.h>
27 #define DRIVER_NAME "orion_spi"
29 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
30 #define SPI_AUTOSUSPEND_TIMEOUT 200
32 /* Some SoCs using this driver support up to 8 chip selects.
33 * It is up to the implementer to only use the chip selects
36 #define ORION_NUM_CHIPSELECTS 8
38 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
40 #define ORION_SPI_IF_CTRL_REG 0x00
41 #define ORION_SPI_IF_CONFIG_REG 0x04
42 #define ORION_SPI_IF_RXLSBF BIT(14)
43 #define ORION_SPI_IF_TXLSBF BIT(13)
44 #define ORION_SPI_DATA_OUT_REG 0x08
45 #define ORION_SPI_DATA_IN_REG 0x0c
46 #define ORION_SPI_INT_CAUSE_REG 0x10
47 #define ORION_SPI_TIMING_PARAMS_REG 0x18
49 /* Register for the "Direct Mode" */
50 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
52 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
53 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
54 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
56 #define ORION_SPI_MODE_CPOL (1 << 11)
57 #define ORION_SPI_MODE_CPHA (1 << 12)
58 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
59 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
60 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
61 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
63 #define ORION_SPI_CS_MASK 0x1C
64 #define ORION_SPI_CS_SHIFT 2
65 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
73 struct orion_spi_dev {
74 enum orion_spi_type typ;
76 * min_divisor and max_hz should be exclusive, the only we can
77 * have both is for managing the armada-370-spi case with old
81 unsigned int min_divisor;
82 unsigned int max_divisor;
84 bool is_errata_50mhz_ac;
87 struct orion_direct_acc {
93 struct spi_master *master;
96 const struct orion_spi_dev *devdata;
98 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS];
101 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
103 return orion_spi->base + reg;
107 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
109 void __iomem *reg_addr = spi_reg(orion_spi, reg);
112 val = readl(reg_addr);
114 writel(val, reg_addr);
118 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
120 void __iomem *reg_addr = spi_reg(orion_spi, reg);
123 val = readl(reg_addr);
125 writel(val, reg_addr);
128 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
134 struct orion_spi *orion_spi;
135 const struct orion_spi_dev *devdata;
137 orion_spi = spi_master_get_devdata(spi->master);
138 devdata = orion_spi->devdata;
140 tclk_hz = clk_get_rate(orion_spi->clk);
142 if (devdata->typ == ARMADA_SPI) {
144 * Given the core_clk (tclk_hz) and the target rate (speed) we
145 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
148 * core_clk / (SPR * 2 ** SPPR)
150 * is as big as possible but not bigger than speed.
153 /* best integer divider: */
154 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
158 /* This is the easy case, divider is less than 16 */
163 unsigned two_pow_sppr;
165 * Find the highest bit set in divider. This and the
166 * three next bits define SPR (apart from rounding).
167 * SPPR is then the number of zero bits that must be
170 sppr = fls(divider) - 4;
173 * As SPR only has 4 bits, we have to round divider up
174 * to the next multiple of 2 ** sppr.
176 two_pow_sppr = 1 << sppr;
177 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
180 * recalculate sppr as rounding up divider might have
181 * increased it enough to change the position of the
182 * highest set bit. In this case the bit that now
183 * doesn't make it into SPR is 0, so there is no need to
186 sppr = fls(divider) - 4;
187 spr = divider >> sppr;
190 * Now do range checking. SPR is constructed to have a
191 * width of 4 bits, so this is fine for sure. So we
192 * still need to check for sppr to fit into 3 bits:
198 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
201 * the supported rates are: 4,6,8...30
202 * round up as we look for equal or less speed
204 rate = DIV_ROUND_UP(tclk_hz, speed);
205 rate = roundup(rate, 2);
207 /* check if requested speed is too small */
214 /* Convert the rate to SPI clock divisor value. */
215 prescale = 0x10 + rate/2;
218 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
219 reg = ((reg & ~devdata->prescale_mask) | prescale);
220 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
226 orion_spi_mode_set(struct spi_device *spi)
229 struct orion_spi *orion_spi;
231 orion_spi = spi_master_get_devdata(spi->master);
233 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
234 reg &= ~ORION_SPI_MODE_MASK;
235 if (spi->mode & SPI_CPOL)
236 reg |= ORION_SPI_MODE_CPOL;
237 if (spi->mode & SPI_CPHA)
238 reg |= ORION_SPI_MODE_CPHA;
239 if (spi->mode & SPI_LSB_FIRST)
240 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
242 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
244 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
248 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
251 struct orion_spi *orion_spi;
253 orion_spi = spi_master_get_devdata(spi->master);
256 * Erratum description: (Erratum NO. FE-9144572) The device
257 * SPI interface supports frequencies of up to 50 MHz.
258 * However, due to this erratum, when the device core clock is
259 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
260 * clock and CPOL=CPHA=1 there might occur data corruption on
261 * reads from the SPI device.
262 * Erratum Workaround:
263 * Work in one of the following configurations:
264 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
266 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
267 * Register" before setting the interface.
269 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
270 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
272 if (clk_get_rate(orion_spi->clk) == 250000000 &&
273 speed == 50000000 && spi->mode & SPI_CPOL &&
274 spi->mode & SPI_CPHA)
275 reg |= ORION_SPI_TMISO_SAMPLE_2;
277 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
279 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
283 * called only when no transfer is active on the bus
286 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
288 struct orion_spi *orion_spi;
289 unsigned int speed = spi->max_speed_hz;
290 unsigned int bits_per_word = spi->bits_per_word;
293 orion_spi = spi_master_get_devdata(spi->master);
295 if ((t != NULL) && t->speed_hz)
298 if ((t != NULL) && t->bits_per_word)
299 bits_per_word = t->bits_per_word;
301 orion_spi_mode_set(spi);
303 if (orion_spi->devdata->is_errata_50mhz_ac)
304 orion_spi_50mhz_ac_timing_erratum(spi, speed);
306 rc = orion_spi_baudrate_set(spi, speed);
310 if (bits_per_word == 16)
311 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
312 ORION_SPI_IF_8_16_BIT_MODE);
314 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
315 ORION_SPI_IF_8_16_BIT_MODE);
320 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
322 struct orion_spi *orion_spi;
324 orion_spi = spi_master_get_devdata(spi->master);
326 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
327 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
328 ORION_SPI_CS(spi->chip_select));
330 /* Chip select logic is inverted from spi_set_cs */
332 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
334 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
337 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
341 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
342 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
352 orion_spi_write_read_8bit(struct spi_device *spi,
353 const u8 **tx_buf, u8 **rx_buf)
355 void __iomem *tx_reg, *rx_reg, *int_reg;
356 struct orion_spi *orion_spi;
358 orion_spi = spi_master_get_devdata(spi->master);
359 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
360 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
361 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
363 /* clear the interrupt cause register */
364 writel(0x0, int_reg);
366 if (tx_buf && *tx_buf)
367 writel(*(*tx_buf)++, tx_reg);
371 if (orion_spi_wait_till_ready(orion_spi) < 0) {
372 dev_err(&spi->dev, "TXS timed out\n");
376 if (rx_buf && *rx_buf)
377 *(*rx_buf)++ = readl(rx_reg);
383 orion_spi_write_read_16bit(struct spi_device *spi,
384 const u16 **tx_buf, u16 **rx_buf)
386 void __iomem *tx_reg, *rx_reg, *int_reg;
387 struct orion_spi *orion_spi;
389 orion_spi = spi_master_get_devdata(spi->master);
390 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
391 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
392 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
394 /* clear the interrupt cause register */
395 writel(0x0, int_reg);
397 if (tx_buf && *tx_buf)
398 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
402 if (orion_spi_wait_till_ready(orion_spi) < 0) {
403 dev_err(&spi->dev, "TXS timed out\n");
407 if (rx_buf && *rx_buf)
408 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
414 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
418 struct orion_spi *orion_spi;
419 int cs = spi->chip_select;
421 word_len = spi->bits_per_word;
424 orion_spi = spi_master_get_devdata(spi->master);
427 * Use SPI direct write mode if base address is available. Otherwise
428 * fall back to PIO mode for this transfer.
430 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) &&
432 unsigned int cnt = count / 4;
433 unsigned int rem = count % 4;
436 * Send the TX-data to the SPI device via the direct
437 * mapped address window
439 iowrite32_rep(orion_spi->direct_access[cs].vaddr,
442 u32 *buf = (u32 *)xfer->tx_buf;
444 iowrite8_rep(orion_spi->direct_access[cs].vaddr,
452 const u8 *tx = xfer->tx_buf;
453 u8 *rx = xfer->rx_buf;
456 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
460 } else if (word_len == 16) {
461 const u16 *tx = xfer->tx_buf;
462 u16 *rx = xfer->rx_buf;
465 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
472 return xfer->len - count;
475 static int orion_spi_transfer_one(struct spi_master *master,
476 struct spi_device *spi,
477 struct spi_transfer *t)
481 status = orion_spi_setup_transfer(spi, t);
486 orion_spi_write_read(spi, t);
491 static int orion_spi_setup(struct spi_device *spi)
493 return orion_spi_setup_transfer(spi, NULL);
496 static int orion_spi_reset(struct orion_spi *orion_spi)
498 /* Verify that the CS is deasserted */
499 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
501 /* Don't deassert CS between the direct mapped SPI transfers */
502 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
507 static const struct orion_spi_dev orion_spi_dev_data = {
511 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
514 static const struct orion_spi_dev armada_370_spi_dev_data = {
519 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
522 static const struct orion_spi_dev armada_xp_spi_dev_data = {
526 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
529 static const struct orion_spi_dev armada_375_spi_dev_data = {
533 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
536 static const struct orion_spi_dev armada_380_spi_dev_data = {
540 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
541 .is_errata_50mhz_ac = true,
544 static const struct of_device_id orion_spi_of_match_table[] = {
546 .compatible = "marvell,orion-spi",
547 .data = &orion_spi_dev_data,
550 .compatible = "marvell,armada-370-spi",
551 .data = &armada_370_spi_dev_data,
554 .compatible = "marvell,armada-375-spi",
555 .data = &armada_375_spi_dev_data,
558 .compatible = "marvell,armada-380-spi",
559 .data = &armada_380_spi_dev_data,
562 .compatible = "marvell,armada-390-spi",
563 .data = &armada_xp_spi_dev_data,
566 .compatible = "marvell,armada-xp-spi",
567 .data = &armada_xp_spi_dev_data,
572 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
574 static int orion_spi_probe(struct platform_device *pdev)
576 const struct of_device_id *of_id;
577 const struct orion_spi_dev *devdata;
578 struct spi_master *master;
579 struct orion_spi *spi;
581 unsigned long tclk_hz;
583 struct device_node *np;
585 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
586 if (master == NULL) {
587 dev_dbg(&pdev->dev, "master allocation failed\n");
592 master->bus_num = pdev->id;
593 if (pdev->dev.of_node) {
596 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
598 master->bus_num = cell_index;
601 /* we support all 4 SPI modes and LSB first option */
602 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
603 master->set_cs = orion_spi_set_cs;
604 master->transfer_one = orion_spi_transfer_one;
605 master->num_chipselect = ORION_NUM_CHIPSELECTS;
606 master->setup = orion_spi_setup;
607 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
608 master->auto_runtime_pm = true;
610 platform_set_drvdata(pdev, master);
612 spi = spi_master_get_devdata(master);
613 spi->master = master;
615 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
616 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
617 spi->devdata = devdata;
619 spi->clk = devm_clk_get(&pdev->dev, NULL);
620 if (IS_ERR(spi->clk)) {
621 status = PTR_ERR(spi->clk);
625 status = clk_prepare_enable(spi->clk);
629 tclk_hz = clk_get_rate(spi->clk);
632 * With old device tree, armada-370-spi could be used with
633 * Armada XP, however for this SoC the maximum frequency is
634 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
635 * higher than 200MHz. So, in order to be able to handle both
636 * SoCs, we can take the minimum of 50MHz and tclk/4.
638 if (of_device_is_compatible(pdev->dev.of_node,
639 "marvell,armada-370-spi"))
640 master->max_speed_hz = min(devdata->max_hz,
641 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
642 else if (devdata->min_divisor)
643 master->max_speed_hz =
644 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
646 master->max_speed_hz = devdata->max_hz;
647 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
649 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 spi->base = devm_ioremap_resource(&pdev->dev, r);
651 if (IS_ERR(spi->base)) {
652 status = PTR_ERR(spi->base);
656 /* Scan all SPI devices of this controller for direct mapped devices */
657 for_each_available_child_of_node(pdev->dev.of_node, np) {
660 /* Get chip-select number from the "reg" property */
661 status = of_property_read_u32(np, "reg", &cs);
664 "%s has no valid 'reg' property (%d)\n",
665 np->full_name, status);
671 * Check if an address is configured for this SPI device. If
672 * not, the MBus mapping via the 'ranges' property in the 'soc'
673 * node is not configured and this device should not use the
674 * direct mode. In this case, just continue with the next
677 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
682 * Only map one page for direct access. This is enough for the
683 * simple TX transfer which only writes to the first word.
684 * This needs to get extended for the direct SPI-NOR / SPI-NAND
685 * support, once this gets implemented.
687 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev,
690 if (!spi->direct_access[cs].vaddr) {
694 spi->direct_access[cs].size = PAGE_SIZE;
696 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
699 pm_runtime_set_active(&pdev->dev);
700 pm_runtime_use_autosuspend(&pdev->dev);
701 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
702 pm_runtime_enable(&pdev->dev);
704 status = orion_spi_reset(spi);
708 pm_runtime_mark_last_busy(&pdev->dev);
709 pm_runtime_put_autosuspend(&pdev->dev);
711 master->dev.of_node = pdev->dev.of_node;
712 status = spi_register_master(master);
719 pm_runtime_disable(&pdev->dev);
721 clk_disable_unprepare(spi->clk);
723 spi_master_put(master);
728 static int orion_spi_remove(struct platform_device *pdev)
730 struct spi_master *master = platform_get_drvdata(pdev);
731 struct orion_spi *spi = spi_master_get_devdata(master);
733 pm_runtime_get_sync(&pdev->dev);
734 clk_disable_unprepare(spi->clk);
736 spi_unregister_master(master);
737 pm_runtime_disable(&pdev->dev);
742 MODULE_ALIAS("platform:" DRIVER_NAME);
745 static int orion_spi_runtime_suspend(struct device *dev)
747 struct spi_master *master = dev_get_drvdata(dev);
748 struct orion_spi *spi = spi_master_get_devdata(master);
750 clk_disable_unprepare(spi->clk);
754 static int orion_spi_runtime_resume(struct device *dev)
756 struct spi_master *master = dev_get_drvdata(dev);
757 struct orion_spi *spi = spi_master_get_devdata(master);
759 return clk_prepare_enable(spi->clk);
763 static const struct dev_pm_ops orion_spi_pm_ops = {
764 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
765 orion_spi_runtime_resume,
769 static struct platform_driver orion_spi_driver = {
772 .pm = &orion_spi_pm_ops,
773 .of_match_table = of_match_ptr(orion_spi_of_match_table),
775 .probe = orion_spi_probe,
776 .remove = orion_spi_remove,
779 module_platform_driver(orion_spi_driver);
781 MODULE_DESCRIPTION("Orion SPI driver");
782 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
783 MODULE_LICENSE("GPL");