2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
20 #include <linux/clk.h>
21 #include <linux/sizes.h>
22 #include <asm/unaligned.h>
24 #define DRIVER_NAME "orion_spi"
26 #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
27 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
29 #define ORION_SPI_IF_CTRL_REG 0x00
30 #define ORION_SPI_IF_CONFIG_REG 0x04
31 #define ORION_SPI_DATA_OUT_REG 0x08
32 #define ORION_SPI_DATA_IN_REG 0x0c
33 #define ORION_SPI_INT_CAUSE_REG 0x10
35 #define ORION_SPI_MODE_CPOL (1 << 11)
36 #define ORION_SPI_MODE_CPHA (1 << 12)
37 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
38 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
39 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
43 struct spi_master *master;
48 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
50 return orion_spi->base + reg;
54 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
56 void __iomem *reg_addr = spi_reg(orion_spi, reg);
59 val = readl(reg_addr);
61 writel(val, reg_addr);
65 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
67 void __iomem *reg_addr = spi_reg(orion_spi, reg);
70 val = readl(reg_addr);
72 writel(val, reg_addr);
75 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
81 struct orion_spi *orion_spi;
83 orion_spi = spi_master_get_devdata(spi->master);
85 tclk_hz = clk_get_rate(orion_spi->clk);
88 * the supported rates are: 4,6,8...30
89 * round up as we look for equal or less speed
91 rate = DIV_ROUND_UP(tclk_hz, speed);
92 rate = roundup(rate, 2);
94 /* check if requested speed is too small */
101 /* Convert the rate to SPI clock divisor value. */
102 prescale = 0x10 + rate/2;
104 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
105 reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
106 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
112 orion_spi_mode_set(struct spi_device *spi)
115 struct orion_spi *orion_spi;
117 orion_spi = spi_master_get_devdata(spi->master);
119 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
120 reg &= ~ORION_SPI_MODE_MASK;
121 if (spi->mode & SPI_CPOL)
122 reg |= ORION_SPI_MODE_CPOL;
123 if (spi->mode & SPI_CPHA)
124 reg |= ORION_SPI_MODE_CPHA;
125 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
129 * called only when no transfer is active on the bus
132 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
134 struct orion_spi *orion_spi;
135 unsigned int speed = spi->max_speed_hz;
136 unsigned int bits_per_word = spi->bits_per_word;
139 orion_spi = spi_master_get_devdata(spi->master);
141 if ((t != NULL) && t->speed_hz)
144 if ((t != NULL) && t->bits_per_word)
145 bits_per_word = t->bits_per_word;
147 orion_spi_mode_set(spi);
149 rc = orion_spi_baudrate_set(spi, speed);
153 if (bits_per_word == 16)
154 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
155 ORION_SPI_IF_8_16_BIT_MODE);
157 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
158 ORION_SPI_IF_8_16_BIT_MODE);
163 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
166 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
168 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
171 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
175 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
176 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
186 orion_spi_write_read_8bit(struct spi_device *spi,
187 const u8 **tx_buf, u8 **rx_buf)
189 void __iomem *tx_reg, *rx_reg, *int_reg;
190 struct orion_spi *orion_spi;
192 orion_spi = spi_master_get_devdata(spi->master);
193 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
194 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
195 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
197 /* clear the interrupt cause register */
198 writel(0x0, int_reg);
200 if (tx_buf && *tx_buf)
201 writel(*(*tx_buf)++, tx_reg);
205 if (orion_spi_wait_till_ready(orion_spi) < 0) {
206 dev_err(&spi->dev, "TXS timed out\n");
210 if (rx_buf && *rx_buf)
211 *(*rx_buf)++ = readl(rx_reg);
217 orion_spi_write_read_16bit(struct spi_device *spi,
218 const u16 **tx_buf, u16 **rx_buf)
220 void __iomem *tx_reg, *rx_reg, *int_reg;
221 struct orion_spi *orion_spi;
223 orion_spi = spi_master_get_devdata(spi->master);
224 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
225 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
226 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
228 /* clear the interrupt cause register */
229 writel(0x0, int_reg);
231 if (tx_buf && *tx_buf)
232 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
236 if (orion_spi_wait_till_ready(orion_spi) < 0) {
237 dev_err(&spi->dev, "TXS timed out\n");
241 if (rx_buf && *rx_buf)
242 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
248 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
253 word_len = spi->bits_per_word;
257 const u8 *tx = xfer->tx_buf;
258 u8 *rx = xfer->rx_buf;
261 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
265 } else if (word_len == 16) {
266 const u16 *tx = xfer->tx_buf;
267 u16 *rx = xfer->rx_buf;
270 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
277 return xfer->len - count;
281 static int orion_spi_transfer_one_message(struct spi_master *master,
282 struct spi_message *m)
284 struct orion_spi *orion_spi = spi_master_get_devdata(master);
285 struct spi_device *spi = m->spi;
286 struct spi_transfer *t = NULL;
287 int par_override = 0;
292 status = orion_spi_setup_transfer(spi, NULL);
297 list_for_each_entry(t, &m->transfers, transfer_list) {
298 if (par_override || t->speed_hz || t->bits_per_word) {
300 status = orion_spi_setup_transfer(spi, t);
303 if (!t->speed_hz && !t->bits_per_word)
308 orion_spi_set_cs(orion_spi, 1);
313 m->actual_length += orion_spi_write_read(spi, t);
316 udelay(t->delay_usecs);
319 orion_spi_set_cs(orion_spi, 0);
326 orion_spi_set_cs(orion_spi, 0);
329 spi_finalize_current_message(master);
334 static int orion_spi_reset(struct orion_spi *orion_spi)
336 /* Verify that the CS is deasserted */
337 orion_spi_set_cs(orion_spi, 0);
342 static int orion_spi_probe(struct platform_device *pdev)
344 struct spi_master *master;
345 struct orion_spi *spi;
347 unsigned long tclk_hz;
352 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
353 if (master == NULL) {
354 dev_dbg(&pdev->dev, "master allocation failed\n");
359 master->bus_num = pdev->id;
360 if (pdev->dev.of_node) {
361 iprop = of_get_property(pdev->dev.of_node, "cell-index",
363 if (iprop && size == sizeof(*iprop))
364 master->bus_num = *iprop;
367 /* we support only mode 0, and no options */
368 master->mode_bits = SPI_CPHA | SPI_CPOL;
370 master->transfer_one_message = orion_spi_transfer_one_message;
371 master->num_chipselect = ORION_NUM_CHIPSELECTS;
372 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
374 platform_set_drvdata(pdev, master);
376 spi = spi_master_get_devdata(master);
377 spi->master = master;
379 spi->clk = devm_clk_get(&pdev->dev, NULL);
380 if (IS_ERR(spi->clk)) {
381 status = PTR_ERR(spi->clk);
385 clk_prepare(spi->clk);
386 clk_enable(spi->clk);
387 tclk_hz = clk_get_rate(spi->clk);
388 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
389 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
391 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
392 spi->base = devm_ioremap_resource(&pdev->dev, r);
393 if (IS_ERR(spi->base)) {
394 status = PTR_ERR(spi->base);
398 if (orion_spi_reset(spi) < 0)
401 master->dev.of_node = pdev->dev.of_node;
402 status = devm_spi_register_master(&pdev->dev, master);
409 clk_disable_unprepare(spi->clk);
411 spi_master_put(master);
416 static int orion_spi_remove(struct platform_device *pdev)
418 struct spi_master *master;
419 struct orion_spi *spi;
421 master = platform_get_drvdata(pdev);
422 spi = spi_master_get_devdata(master);
424 clk_disable_unprepare(spi->clk);
429 MODULE_ALIAS("platform:" DRIVER_NAME);
431 static const struct of_device_id orion_spi_of_match_table[] = {
432 { .compatible = "marvell,orion-spi", },
435 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
437 static struct platform_driver orion_spi_driver = {
440 .owner = THIS_MODULE,
441 .of_match_table = of_match_ptr(orion_spi_of_match_table),
443 .probe = orion_spi_probe,
444 .remove = orion_spi_remove,
447 module_platform_driver(orion_spi_driver);
449 MODULE_DESCRIPTION("Orion SPI driver");
450 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
451 MODULE_LICENSE("GPL");