4 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2011 Renesas Solutions Corp.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/list.h>
29 #include <linux/workqueue.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
33 #include <linux/clk.h>
34 #include <linux/spi/spi.h>
36 #define RSPI_SPCR 0x00
37 #define RSPI_SSLP 0x01
38 #define RSPI_SPPCR 0x02
39 #define RSPI_SPSR 0x03
40 #define RSPI_SPDR 0x04
41 #define RSPI_SPSCR 0x08
42 #define RSPI_SPSSR 0x09
43 #define RSPI_SPBR 0x0a
44 #define RSPI_SPDCR 0x0b
45 #define RSPI_SPCKD 0x0c
46 #define RSPI_SSLND 0x0d
47 #define RSPI_SPND 0x0e
48 #define RSPI_SPCR2 0x0f
49 #define RSPI_SPCMD0 0x10
50 #define RSPI_SPCMD1 0x12
51 #define RSPI_SPCMD2 0x14
52 #define RSPI_SPCMD3 0x16
53 #define RSPI_SPCMD4 0x18
54 #define RSPI_SPCMD5 0x1a
55 #define RSPI_SPCMD6 0x1c
56 #define RSPI_SPCMD7 0x1e
59 #define SPCR_SPRIE 0x80
61 #define SPCR_SPTIE 0x20
62 #define SPCR_SPEIE 0x10
63 #define SPCR_MSTR 0x08
64 #define SPCR_MODFEN 0x04
65 #define SPCR_TXMD 0x02
66 #define SPCR_SPMS 0x01
69 #define SSLP_SSL1P 0x02
70 #define SSLP_SSL0P 0x01
73 #define SPPCR_MOIFE 0x20
74 #define SPPCR_MOIFV 0x10
75 #define SPPCR_SPOM 0x04
76 #define SPPCR_SPLP2 0x02
77 #define SPPCR_SPLP 0x01
80 #define SPSR_SPRF 0x80
81 #define SPSR_SPTEF 0x20
82 #define SPSR_PERF 0x08
83 #define SPSR_MODF 0x04
84 #define SPSR_IDLNF 0x02
85 #define SPSR_OVRF 0x01
88 #define SPSCR_SPSLN_MASK 0x07
91 #define SPSSR_SPECM_MASK 0x70
92 #define SPSSR_SPCP_MASK 0x07
95 #define SPDCR_SPLW 0x20
96 #define SPDCR_SPRDTD 0x10
97 #define SPDCR_SLSEL1 0x08
98 #define SPDCR_SLSEL0 0x04
99 #define SPDCR_SLSEL_MASK 0x0c
100 #define SPDCR_SPFC1 0x02
101 #define SPDCR_SPFC0 0x01
104 #define SPCKD_SCKDL_MASK 0x07
107 #define SSLND_SLNDL_MASK 0x07
110 #define SPND_SPNDL_MASK 0x07
113 #define SPCR2_PTE 0x08
114 #define SPCR2_SPIE 0x04
115 #define SPCR2_SPOE 0x02
116 #define SPCR2_SPPE 0x01
119 #define SPCMD_SCKDEN 0x8000
120 #define SPCMD_SLNDEN 0x4000
121 #define SPCMD_SPNDEN 0x2000
122 #define SPCMD_LSBF 0x1000
123 #define SPCMD_SPB_MASK 0x0f00
124 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
125 #define SPCMD_SPB_20BIT 0x0000
126 #define SPCMD_SPB_24BIT 0x0100
127 #define SPCMD_SPB_32BIT 0x0200
128 #define SPCMD_SSLKP 0x0080
129 #define SPCMD_SSLA_MASK 0x0030
130 #define SPCMD_BRDV_MASK 0x000c
131 #define SPCMD_CPOL 0x0002
132 #define SPCMD_CPHA 0x0001
137 struct spi_master *master;
138 struct list_head queue;
139 struct work_struct ws;
140 wait_queue_head_t wait;
146 static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
148 iowrite8(data, rspi->addr + offset);
151 static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
153 iowrite16(data, rspi->addr + offset);
156 static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
158 return ioread8(rspi->addr + offset);
161 static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
163 return ioread16(rspi->addr + offset);
166 static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
171 tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
172 spbr = clamp(tmp, 0, 255);
177 static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
179 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
182 static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
184 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
187 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
192 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
193 rspi_enable_irq(rspi, enable_bit);
194 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
195 if (ret == 0 && !(rspi->spsr & wait_mask))
201 static void rspi_assert_ssl(struct rspi_data *rspi)
203 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
206 static void rspi_negate_ssl(struct rspi_data *rspi)
208 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
211 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
213 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
214 rspi_write8(rspi, 0x00, RSPI_SPPCR);
216 /* Sets transfer bit rate */
217 rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
219 /* Sets number of frames to be used: 1 frame */
220 rspi_write8(rspi, 0x00, RSPI_SPDCR);
222 /* Sets RSPCK, SSL, next-access delay value */
223 rspi_write8(rspi, 0x00, RSPI_SPCKD);
224 rspi_write8(rspi, 0x00, RSPI_SSLND);
225 rspi_write8(rspi, 0x00, RSPI_SPND);
227 /* Sets parity, interrupt mask */
228 rspi_write8(rspi, 0x00, RSPI_SPCR2);
231 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
235 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
240 static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
241 struct spi_transfer *t)
246 data = (u8 *)t->tx_buf;
248 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
251 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
252 dev_err(&rspi->master->dev,
253 "%s: tx empty timeout\n", __func__);
257 rspi_write16(rspi, *data, RSPI_SPDR);
262 /* Waiting for the last transmition */
263 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
268 static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
269 struct spi_transfer *t)
275 spsr = rspi_read8(rspi, RSPI_SPSR);
276 if (spsr & SPSR_SPRF)
277 rspi_read16(rspi, RSPI_SPDR); /* dummy read */
278 if (spsr & SPSR_OVRF)
279 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
282 data = (u8 *)t->rx_buf;
284 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
287 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
288 dev_err(&rspi->master->dev,
289 "%s: tx empty timeout\n", __func__);
292 /* dummy write for generate clock */
293 rspi_write16(rspi, 0x00, RSPI_SPDR);
295 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
296 dev_err(&rspi->master->dev,
297 "%s: receive timeout\n", __func__);
300 /* SPDR allows 16 or 32-bit access only */
301 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
310 static void rspi_work(struct work_struct *work)
312 struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
313 struct spi_message *mesg;
314 struct spi_transfer *t;
318 spin_lock_irqsave(&rspi->lock, flags);
319 while (!list_empty(&rspi->queue)) {
320 mesg = list_entry(rspi->queue.next, struct spi_message, queue);
321 list_del_init(&mesg->queue);
322 spin_unlock_irqrestore(&rspi->lock, flags);
324 rspi_assert_ssl(rspi);
326 list_for_each_entry(t, &mesg->transfers, transfer_list) {
328 ret = rspi_send_pio(rspi, mesg, t);
333 ret = rspi_receive_pio(rspi, mesg, t);
337 mesg->actual_length += t->len;
339 rspi_negate_ssl(rspi);
342 mesg->complete(mesg->context);
344 spin_lock_irqsave(&rspi->lock, flags);
351 mesg->complete(mesg->context);
354 static int rspi_setup(struct spi_device *spi)
356 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
358 if (!spi->bits_per_word)
359 spi->bits_per_word = 8;
360 rspi->max_speed_hz = spi->max_speed_hz;
362 rspi_set_config_register(rspi, 8);
367 static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
369 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
372 mesg->actual_length = 0;
373 mesg->status = -EINPROGRESS;
375 spin_lock_irqsave(&rspi->lock, flags);
376 list_add_tail(&mesg->queue, &rspi->queue);
377 schedule_work(&rspi->ws);
378 spin_unlock_irqrestore(&rspi->lock, flags);
383 static void rspi_cleanup(struct spi_device *spi)
387 static irqreturn_t rspi_irq(int irq, void *_sr)
389 struct rspi_data *rspi = (struct rspi_data *)_sr;
391 irqreturn_t ret = IRQ_NONE;
392 unsigned char disable_irq = 0;
394 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (spsr & SPSR_SPRF)
396 disable_irq |= SPCR_SPRIE;
397 if (spsr & SPSR_SPTEF)
398 disable_irq |= SPCR_SPTIE;
402 rspi_disable_irq(rspi, disable_irq);
403 wake_up(&rspi->wait);
409 static int __devexit rspi_remove(struct platform_device *pdev)
411 struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
413 spi_unregister_master(rspi->master);
414 free_irq(platform_get_irq(pdev, 0), rspi);
417 spi_master_put(rspi->master);
422 static int __devinit rspi_probe(struct platform_device *pdev)
424 struct resource *res;
425 struct spi_master *master;
426 struct rspi_data *rspi;
431 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432 if (unlikely(res == NULL)) {
433 dev_err(&pdev->dev, "invalid resource\n");
437 irq = platform_get_irq(pdev, 0);
439 dev_err(&pdev->dev, "platform_get_irq error\n");
443 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
444 if (master == NULL) {
445 dev_err(&pdev->dev, "spi_alloc_master error.\n");
449 rspi = spi_master_get_devdata(master);
450 dev_set_drvdata(&pdev->dev, rspi);
452 rspi->master = master;
453 rspi->addr = ioremap(res->start, resource_size(res));
454 if (rspi->addr == NULL) {
455 dev_err(&pdev->dev, "ioremap error.\n");
460 snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
461 rspi->clk = clk_get(&pdev->dev, clk_name);
462 if (IS_ERR(rspi->clk)) {
463 dev_err(&pdev->dev, "cannot get clock\n");
464 ret = PTR_ERR(rspi->clk);
467 clk_enable(rspi->clk);
469 INIT_LIST_HEAD(&rspi->queue);
470 spin_lock_init(&rspi->lock);
471 INIT_WORK(&rspi->ws, rspi_work);
472 init_waitqueue_head(&rspi->wait);
474 master->num_chipselect = 2;
475 master->bus_num = pdev->id;
476 master->setup = rspi_setup;
477 master->transfer = rspi_transfer;
478 master->cleanup = rspi_cleanup;
480 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
482 dev_err(&pdev->dev, "request_irq error\n");
486 ret = spi_register_master(master);
488 dev_err(&pdev->dev, "spi_register_master error.\n");
492 dev_info(&pdev->dev, "probed\n");
503 spi_master_put(master);
508 static struct platform_driver rspi_driver = {
510 .remove = __devexit_p(rspi_remove),
513 .owner = THIS_MODULE,
516 module_platform_driver(rspi_driver);
518 MODULE_DESCRIPTION("Renesas RSPI bus driver");
519 MODULE_LICENSE("GPL v2");
520 MODULE_AUTHOR("Yoshihiro Shimoda");
521 MODULE_ALIAS("platform:rspi");