4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
8 * Copyright (C) 2011 Renesas Solutions Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
32 #include <linux/clk.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sh_dma.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/rspi.h>
41 #define RSPI_SPCR 0x00 /* Control Register */
42 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
43 #define RSPI_SPPCR 0x02 /* Pin Control Register */
44 #define RSPI_SPSR 0x03 /* Status Register */
45 #define RSPI_SPDR 0x04 /* Data Register */
46 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
47 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
48 #define RSPI_SPBR 0x0a /* Bit Rate Register */
49 #define RSPI_SPDCR 0x0b /* Data Control Register */
50 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
51 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
52 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
53 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
54 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
55 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
56 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
57 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
58 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
59 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
60 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
61 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
62 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63 #define RSPI_NUM_SPCMD 8
64 #define RSPI_RZ_NUM_SPCMD 4
65 #define QSPI_NUM_SPCMD 4
68 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
69 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
72 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
73 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
74 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
75 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
76 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
77 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
80 /* SPCR - Control Register */
81 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
82 #define SPCR_SPE 0x40 /* Function Enable */
83 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
84 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
85 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
86 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
88 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
89 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
90 /* QSPI on R-Car Gen2 only */
91 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
92 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
94 /* SSLP - Slave Select Polarity Register */
95 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
96 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
98 /* SPPCR - Pin Control Register */
99 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM 0x04
102 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
105 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
108 /* SPSR - Status Register */
109 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
110 #define SPSR_TEND 0x40 /* Transmit End */
111 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF 0x08 /* Parity Error Flag */
113 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
114 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
115 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
122 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD SPDCR_SPLW1
130 #define SPDCR_SPLBYTE SPDCR_SPLW0
131 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1 0x08
134 #define SPDCR_SLSEL0 0x04
135 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1 0x02
137 #define SPDCR_SPFC0 0x01
138 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
151 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
152 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE 0x01 /* Parity Enable */
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
159 #define SPCMD_LSBF 0x1000 /* LSB First */
160 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
163 #define SPCMD_SPB_16BIT 0x0100
164 #define SPCMD_SPB_20BIT 0x0000
165 #define SPCMD_SPB_24BIT 0x0100
166 #define SPCMD_SPB_32BIT 0x0200
167 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1 0x0040
170 #define SPCMD_SPIMOD0 0x0020
171 #define SPCMD_SPIMOD_SINGLE 0
172 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
174 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
177 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
178 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
189 struct spi_master *master;
190 wait_queue_head_t wait;
196 const struct spi_ops *ops;
198 unsigned dma_callbacked:1;
199 unsigned byte_access:1;
202 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
204 iowrite8(data, rspi->addr + offset);
207 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
209 iowrite16(data, rspi->addr + offset);
212 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
214 iowrite32(data, rspi->addr + offset);
217 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
219 return ioread8(rspi->addr + offset);
222 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
224 return ioread16(rspi->addr + offset);
227 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
229 if (rspi->byte_access)
230 rspi_write8(rspi, data, RSPI_SPDR);
232 rspi_write16(rspi, data, RSPI_SPDR);
235 static u16 rspi_read_data(const struct rspi_data *rspi)
237 if (rspi->byte_access)
238 return rspi_read8(rspi, RSPI_SPDR);
240 return rspi_read16(rspi, RSPI_SPDR);
243 /* optional functions */
245 int (*set_config_register)(struct rspi_data *rspi, int access_size);
246 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
247 struct spi_transfer *xfer);
254 * functions for RSPI on legacy SH
256 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
260 /* Sets output mode, MOSI signal, and (optionally) loopback */
261 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
263 /* Sets transfer bit rate */
264 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
265 2 * rspi->max_speed_hz) - 1;
266 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
268 /* Disable dummy transmission, set 16-bit word access, 1 frame */
269 rspi_write8(rspi, 0, RSPI_SPDCR);
270 rspi->byte_access = 0;
272 /* Sets RSPCK, SSL, next-access delay value */
273 rspi_write8(rspi, 0x00, RSPI_SPCKD);
274 rspi_write8(rspi, 0x00, RSPI_SSLND);
275 rspi_write8(rspi, 0x00, RSPI_SPND);
277 /* Sets parity, interrupt mask */
278 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
282 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
285 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
291 * functions for RSPI on RZ
293 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
297 /* Sets output mode, MOSI signal, and (optionally) loopback */
298 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
300 /* Sets transfer bit rate */
301 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
302 2 * rspi->max_speed_hz) - 1;
303 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
305 /* Disable dummy transmission, set byte access */
306 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
307 rspi->byte_access = 1;
309 /* Sets RSPCK, SSL, next-access delay value */
310 rspi_write8(rspi, 0x00, RSPI_SPCKD);
311 rspi_write8(rspi, 0x00, RSPI_SSLND);
312 rspi_write8(rspi, 0x00, RSPI_SPND);
315 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
316 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
319 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
327 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
331 /* Sets output mode, MOSI signal, and (optionally) loopback */
332 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
334 /* Sets transfer bit rate */
335 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
336 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
338 /* Disable dummy transmission, set byte access */
339 rspi_write8(rspi, 0, RSPI_SPDCR);
340 rspi->byte_access = 1;
342 /* Sets RSPCK, SSL, next-access delay value */
343 rspi_write8(rspi, 0x00, RSPI_SPCKD);
344 rspi_write8(rspi, 0x00, RSPI_SSLND);
345 rspi_write8(rspi, 0x00, RSPI_SPND);
347 /* Data Length Setting */
348 if (access_size == 8)
349 rspi->spcmd |= SPCMD_SPB_8BIT;
350 else if (access_size == 16)
351 rspi->spcmd |= SPCMD_SPB_16BIT;
353 rspi->spcmd |= SPCMD_SPB_32BIT;
355 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
357 /* Resets transfer data length */
358 rspi_write32(rspi, 0, QSPI_SPBMUL0);
360 /* Resets transmit and receive buffer */
361 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
362 /* Sets buffer to allow normal operation */
363 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
366 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
368 /* Enables SPI function in master mode */
369 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
374 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
376 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
378 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
381 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
383 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
386 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
391 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
392 if (rspi->spsr & wait_mask)
395 rspi_enable_irq(rspi, enable_bit);
396 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
397 if (ret == 0 && !(rspi->spsr & wait_mask))
403 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
405 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
408 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
410 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
413 static int rspi_data_out(struct rspi_data *rspi, u8 data)
415 int error = rspi_wait_for_tx_empty(rspi);
417 dev_err(&rspi->master->dev, "transmit timeout\n");
420 rspi_write_data(rspi, data);
424 static int rspi_data_in(struct rspi_data *rspi)
429 error = rspi_wait_for_rx_full(rspi);
431 dev_err(&rspi->master->dev, "receive timeout\n");
434 data = rspi_read_data(rspi);
438 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
443 int ret = rspi_data_out(rspi, *tx++);
448 int ret = rspi_data_in(rspi);
458 static void rspi_dma_complete(void *arg)
460 struct rspi_data *rspi = arg;
462 rspi->dma_callbacked = 1;
463 wake_up_interruptible(&rspi->wait);
466 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
469 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
471 unsigned int other_irq = 0;
475 /* First prepare and submit the DMA request(s), as this may fail */
477 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
478 rx->sgl, rx->nents, DMA_FROM_DEVICE,
479 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 desc_rx->callback = rspi_dma_complete;
486 desc_rx->callback_param = rspi;
487 cookie = dmaengine_submit(desc_rx);
488 if (dma_submit_error(cookie)) {
493 irq_mask |= SPCR_SPRIE;
497 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
498 tx->sgl, tx->nents, DMA_TO_DEVICE,
499 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
507 desc_tx->callback = NULL;
509 desc_tx->callback = rspi_dma_complete;
510 desc_tx->callback_param = rspi;
512 cookie = dmaengine_submit(desc_tx);
513 if (dma_submit_error(cookie)) {
518 irq_mask |= SPCR_SPTIE;
522 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
523 * called. So, this driver disables the IRQ while DMA transfer.
526 disable_irq(other_irq = rspi->tx_irq);
527 if (rx && rspi->rx_irq != other_irq)
528 disable_irq(rspi->rx_irq);
530 rspi_enable_irq(rspi, irq_mask);
531 rspi->dma_callbacked = 0;
535 dma_async_issue_pending(rspi->master->dma_rx);
537 dma_async_issue_pending(rspi->master->dma_tx);
539 ret = wait_event_interruptible_timeout(rspi->wait,
540 rspi->dma_callbacked, HZ);
541 if (ret > 0 && rspi->dma_callbacked)
544 dev_err(&rspi->master->dev, "DMA timeout\n");
547 dmaengine_terminate_all(rspi->master->dma_tx);
549 dmaengine_terminate_all(rspi->master->dma_rx);
552 rspi_disable_irq(rspi, irq_mask);
555 enable_irq(rspi->tx_irq);
556 if (rx && rspi->rx_irq != other_irq)
557 enable_irq(rspi->rx_irq);
563 dmaengine_terminate_all(rspi->master->dma_rx);
565 if (ret == -EAGAIN) {
566 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
567 dev_driver_string(&rspi->master->dev),
568 dev_name(&rspi->master->dev));
573 static void rspi_receive_init(const struct rspi_data *rspi)
577 spsr = rspi_read8(rspi, RSPI_SPSR);
578 if (spsr & SPSR_SPRF)
579 rspi_read_data(rspi); /* dummy read */
580 if (spsr & SPSR_OVRF)
581 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
585 static void rspi_rz_receive_init(const struct rspi_data *rspi)
587 rspi_receive_init(rspi);
588 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
589 rspi_write8(rspi, 0, RSPI_SPBFCR);
592 static void qspi_receive_init(const struct rspi_data *rspi)
596 spsr = rspi_read8(rspi, RSPI_SPSR);
597 if (spsr & SPSR_SPRF)
598 rspi_read_data(rspi); /* dummy read */
599 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
600 rspi_write8(rspi, 0, QSPI_SPBFCR);
603 static bool __rspi_can_dma(const struct rspi_data *rspi,
604 const struct spi_transfer *xfer)
606 return xfer->len > rspi->ops->fifo_size;
609 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
610 struct spi_transfer *xfer)
612 struct rspi_data *rspi = spi_master_get_devdata(master);
614 return __rspi_can_dma(rspi, xfer);
617 static int rspi_common_transfer(struct rspi_data *rspi,
618 struct spi_transfer *xfer)
622 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
623 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
624 ret = rspi_dma_transfer(rspi, &xfer->tx_sg,
625 xfer->rx_buf ? &xfer->rx_sg : NULL);
630 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
634 /* Wait for the last transmission */
635 rspi_wait_for_tx_empty(rspi);
640 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
641 struct spi_transfer *xfer)
643 struct rspi_data *rspi = spi_master_get_devdata(master);
646 spcr = rspi_read8(rspi, RSPI_SPCR);
648 rspi_receive_init(rspi);
653 rspi_write8(rspi, spcr, RSPI_SPCR);
655 return rspi_common_transfer(rspi, xfer);
658 static int rspi_rz_transfer_one(struct spi_master *master,
659 struct spi_device *spi,
660 struct spi_transfer *xfer)
662 struct rspi_data *rspi = spi_master_get_devdata(master);
664 rspi_rz_receive_init(rspi);
666 return rspi_common_transfer(rspi, xfer);
669 static int qspi_transfer_out_in(struct rspi_data *rspi,
670 struct spi_transfer *xfer)
672 qspi_receive_init(rspi);
674 return rspi_common_transfer(rspi, xfer);
677 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
681 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
682 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
687 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
691 /* Wait for the last transmission */
692 rspi_wait_for_tx_empty(rspi);
697 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
699 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
700 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
705 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
708 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
709 struct spi_transfer *xfer)
711 struct rspi_data *rspi = spi_master_get_devdata(master);
713 if (spi->mode & SPI_LOOP) {
714 return qspi_transfer_out_in(rspi, xfer);
715 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
716 /* Quad or Dual SPI Write */
717 return qspi_transfer_out(rspi, xfer);
718 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
719 /* Quad or Dual SPI Read */
720 return qspi_transfer_in(rspi, xfer);
722 /* Single SPI Transfer */
723 return qspi_transfer_out_in(rspi, xfer);
727 static int rspi_setup(struct spi_device *spi)
729 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
731 rspi->max_speed_hz = spi->max_speed_hz;
733 rspi->spcmd = SPCMD_SSLKP;
734 if (spi->mode & SPI_CPOL)
735 rspi->spcmd |= SPCMD_CPOL;
736 if (spi->mode & SPI_CPHA)
737 rspi->spcmd |= SPCMD_CPHA;
739 /* CMOS output mode and MOSI signal from previous transfer */
741 if (spi->mode & SPI_LOOP)
742 rspi->sppcr |= SPPCR_SPLP;
744 set_config_register(rspi, 8);
749 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
752 switch (xfer->tx_nbits) {
754 return SPCMD_SPIMOD_QUAD;
756 return SPCMD_SPIMOD_DUAL;
761 switch (xfer->rx_nbits) {
763 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
765 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
773 static int qspi_setup_sequencer(struct rspi_data *rspi,
774 const struct spi_message *msg)
776 const struct spi_transfer *xfer;
777 unsigned int i = 0, len = 0;
778 u16 current_mode = 0xffff, mode;
780 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
781 mode = qspi_transfer_mode(xfer);
782 if (mode == current_mode) {
787 /* Transfer mode change */
789 /* Set transfer data length of previous transfer */
790 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
793 if (i >= QSPI_NUM_SPCMD) {
794 dev_err(&msg->spi->dev,
795 "Too many different transfer modes");
799 /* Program transfer mode for this transfer */
800 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
806 /* Set final transfer data length and sequence length */
807 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
808 rspi_write8(rspi, i - 1, RSPI_SPSCR);
814 static int rspi_prepare_message(struct spi_master *master,
815 struct spi_message *msg)
817 struct rspi_data *rspi = spi_master_get_devdata(master);
821 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
822 /* Setup sequencer for messages with multiple transfer modes */
823 ret = qspi_setup_sequencer(rspi, msg);
828 /* Enable SPI function in master mode */
829 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
833 static int rspi_unprepare_message(struct spi_master *master,
834 struct spi_message *msg)
836 struct rspi_data *rspi = spi_master_get_devdata(master);
838 /* Disable SPI function */
839 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
841 /* Reset sequencer for Single SPI Transfers */
842 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
843 rspi_write8(rspi, 0, RSPI_SPSCR);
847 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
849 struct rspi_data *rspi = _sr;
851 irqreturn_t ret = IRQ_NONE;
854 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
855 if (spsr & SPSR_SPRF)
856 disable_irq |= SPCR_SPRIE;
857 if (spsr & SPSR_SPTEF)
858 disable_irq |= SPCR_SPTIE;
862 rspi_disable_irq(rspi, disable_irq);
863 wake_up(&rspi->wait);
869 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
871 struct rspi_data *rspi = _sr;
874 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
875 if (spsr & SPSR_SPRF) {
876 rspi_disable_irq(rspi, SPCR_SPRIE);
877 wake_up(&rspi->wait);
884 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
886 struct rspi_data *rspi = _sr;
889 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
890 if (spsr & SPSR_SPTEF) {
891 rspi_disable_irq(rspi, SPCR_SPTIE);
892 wake_up(&rspi->wait);
899 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
900 enum dma_transfer_direction dir,
902 dma_addr_t port_addr)
905 struct dma_chan *chan;
906 struct dma_slave_config cfg;
910 dma_cap_set(DMA_SLAVE, mask);
912 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
913 (void *)(unsigned long)id, dev,
914 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
916 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
920 memset(&cfg, 0, sizeof(cfg));
923 if (dir == DMA_MEM_TO_DEV) {
924 cfg.dst_addr = port_addr;
925 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
927 cfg.src_addr = port_addr;
928 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
931 ret = dmaengine_slave_config(chan, &cfg);
933 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
934 dma_release_channel(chan);
941 static int rspi_request_dma(struct device *dev, struct spi_master *master,
942 const struct resource *res)
944 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
945 unsigned int dma_tx_id, dma_rx_id;
948 /* In the OF case we will get the slave IDs from the DT */
951 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
952 dma_tx_id = rspi_pd->dma_tx_id;
953 dma_rx_id = rspi_pd->dma_rx_id;
955 /* The driver assumes no error. */
959 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
960 res->start + RSPI_SPDR);
964 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
965 res->start + RSPI_SPDR);
966 if (!master->dma_rx) {
967 dma_release_channel(master->dma_tx);
968 master->dma_tx = NULL;
972 master->can_dma = rspi_can_dma;
973 dev_info(dev, "DMA available");
977 static void rspi_release_dma(struct spi_master *master)
980 dma_release_channel(master->dma_tx);
982 dma_release_channel(master->dma_rx);
985 static int rspi_remove(struct platform_device *pdev)
987 struct rspi_data *rspi = platform_get_drvdata(pdev);
989 rspi_release_dma(rspi->master);
990 pm_runtime_disable(&pdev->dev);
995 static const struct spi_ops rspi_ops = {
996 .set_config_register = rspi_set_config_register,
997 .transfer_one = rspi_transfer_one,
998 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
999 .flags = SPI_MASTER_MUST_TX,
1003 static const struct spi_ops rspi_rz_ops = {
1004 .set_config_register = rspi_rz_set_config_register,
1005 .transfer_one = rspi_rz_transfer_one,
1006 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1007 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1008 .fifo_size = 8, /* 8 for TX, 32 for RX */
1011 static const struct spi_ops qspi_ops = {
1012 .set_config_register = qspi_set_config_register,
1013 .transfer_one = qspi_transfer_one,
1014 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1015 SPI_TX_DUAL | SPI_TX_QUAD |
1016 SPI_RX_DUAL | SPI_RX_QUAD,
1017 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1022 static const struct of_device_id rspi_of_match[] = {
1023 /* RSPI on legacy SH */
1024 { .compatible = "renesas,rspi", .data = &rspi_ops },
1025 /* RSPI on RZ/A1H */
1026 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1027 /* QSPI on R-Car Gen2 */
1028 { .compatible = "renesas,qspi", .data = &qspi_ops },
1032 MODULE_DEVICE_TABLE(of, rspi_of_match);
1034 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1039 /* Parse DT properties */
1040 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1042 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1046 master->num_chipselect = num_cs;
1050 #define rspi_of_match NULL
1051 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1055 #endif /* CONFIG_OF */
1057 static int rspi_request_irq(struct device *dev, unsigned int irq,
1058 irq_handler_t handler, const char *suffix,
1061 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1062 dev_name(dev), suffix);
1066 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1069 static int rspi_probe(struct platform_device *pdev)
1071 struct resource *res;
1072 struct spi_master *master;
1073 struct rspi_data *rspi;
1075 const struct of_device_id *of_id;
1076 const struct rspi_plat_data *rspi_pd;
1077 const struct spi_ops *ops;
1079 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1080 if (master == NULL) {
1081 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1085 of_id = of_match_device(rspi_of_match, &pdev->dev);
1088 ret = rspi_parse_dt(&pdev->dev, master);
1092 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1093 rspi_pd = dev_get_platdata(&pdev->dev);
1094 if (rspi_pd && rspi_pd->num_chipselect)
1095 master->num_chipselect = rspi_pd->num_chipselect;
1097 master->num_chipselect = 2; /* default */
1100 /* ops parameter check */
1101 if (!ops->set_config_register) {
1102 dev_err(&pdev->dev, "there is no set_config_register\n");
1107 rspi = spi_master_get_devdata(master);
1108 platform_set_drvdata(pdev, rspi);
1110 rspi->master = master;
1112 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1113 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1114 if (IS_ERR(rspi->addr)) {
1115 ret = PTR_ERR(rspi->addr);
1119 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1120 if (IS_ERR(rspi->clk)) {
1121 dev_err(&pdev->dev, "cannot get clock\n");
1122 ret = PTR_ERR(rspi->clk);
1126 pm_runtime_enable(&pdev->dev);
1128 init_waitqueue_head(&rspi->wait);
1130 master->bus_num = pdev->id;
1131 master->setup = rspi_setup;
1132 master->auto_runtime_pm = true;
1133 master->transfer_one = ops->transfer_one;
1134 master->prepare_message = rspi_prepare_message;
1135 master->unprepare_message = rspi_unprepare_message;
1136 master->mode_bits = ops->mode_bits;
1137 master->flags = ops->flags;
1138 master->dev.of_node = pdev->dev.of_node;
1140 ret = platform_get_irq_byname(pdev, "rx");
1142 ret = platform_get_irq_byname(pdev, "mux");
1144 ret = platform_get_irq(pdev, 0);
1146 rspi->rx_irq = rspi->tx_irq = ret;
1149 ret = platform_get_irq_byname(pdev, "tx");
1154 dev_err(&pdev->dev, "platform_get_irq error\n");
1158 if (rspi->rx_irq == rspi->tx_irq) {
1159 /* Single multiplexed interrupt */
1160 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1163 /* Multi-interrupt mode, only SPRI and SPTI are used */
1164 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1167 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1168 rspi_irq_tx, "tx", rspi);
1171 dev_err(&pdev->dev, "request_irq error\n");
1175 ret = rspi_request_dma(&pdev->dev, master, res);
1177 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1179 ret = devm_spi_register_master(&pdev->dev, master);
1181 dev_err(&pdev->dev, "spi_register_master error.\n");
1185 dev_info(&pdev->dev, "probed\n");
1190 rspi_release_dma(master);
1192 pm_runtime_disable(&pdev->dev);
1194 spi_master_put(master);
1199 static struct platform_device_id spi_driver_ids[] = {
1200 { "rspi", (kernel_ulong_t)&rspi_ops },
1201 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1202 { "qspi", (kernel_ulong_t)&qspi_ops },
1206 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1208 static struct platform_driver rspi_driver = {
1209 .probe = rspi_probe,
1210 .remove = rspi_remove,
1211 .id_table = spi_driver_ids,
1213 .name = "renesas_spi",
1214 .owner = THIS_MODULE,
1215 .of_match_table = of_match_ptr(rspi_of_match),
1218 module_platform_driver(rspi_driver);
1220 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1221 MODULE_LICENSE("GPL v2");
1222 MODULE_AUTHOR("Yoshihiro Shimoda");
1223 MODULE_ALIAS("platform:rspi");