drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of.h>
  32 #include <linux/of_gpio.h>
  33
  34 #include <mach/dma.h>
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #define MAX_SPI_PORTS           3
  38
  39 /* Registers and bit-fields */
  40
  41 #define S3C64XX_SPI_CH_CFG              0x00
  42 #define S3C64XX_SPI_CLK_CFG             0x04
  43 #define S3C64XX_SPI_MODE_CFG    0x08
  44 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  45 #define S3C64XX_SPI_INT_EN              0x10
  46 #define S3C64XX_SPI_STATUS              0x14
  47 #define S3C64XX_SPI_TX_DATA             0x18
  48 #define S3C64XX_SPI_RX_DATA             0x1C
  49 #define S3C64XX_SPI_PACKET_CNT  0x20
  50 #define S3C64XX_SPI_PENDING_CLR 0x24
  51 #define S3C64XX_SPI_SWAP_CFG    0x28
  52 #define S3C64XX_SPI_FB_CLK              0x2C
  53
  54 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  55 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  56 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  57 #define S3C64XX_SPI_CPOL_L              (1<<3)
  58 #define S3C64XX_SPI_CPHA_B              (1<<2)
  59 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  60 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  61
  62 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  63 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  64 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  65 #define S3C64XX_SPI_PSR_MASK            0xff
  66
  67 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  69 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  70 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  73 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  74 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  75 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  76 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  77 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  78
  79 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  80 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  81
  82 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  83 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  84 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  85 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  86 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  87 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  88 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  89
  90 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  91 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  92 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  93 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  94 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  95 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  96
  97 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  98
  99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 103 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 104
 105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 106 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 107 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 108 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 110 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 111 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 112 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 113
 114 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 115
 116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 118                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 121                                         FIFO_LVL_MASK(i))
 122
 123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 124 #define S3C64XX_SPI_TRAILCNT_OFF        19
 125
 126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 127
 128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         unsigned                ch;
 135         enum dma_transfer_direction direction;
 136         enum dma_ch     dmach;
 137 };
 138
 139 /**
 140  * struct s3c64xx_spi_info - SPI Controller hardware info
 141  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 142  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 143  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 144  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 145  * @clk_from_cmu: True, if the controller does not include a clock mux and
 146  *      prescaler unit.
 147  *
 148  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 149  * differ in some aspects such as the size of the fifo and spi bus clock
 150  * setup. Such differences are specified to the driver using this structure
 151  * which is provided as driver data to the driver.
 152  */
 153 struct s3c64xx_spi_port_config {
 154         int     fifo_lvl_mask[MAX_SPI_PORTS];
 155         int     rx_lvl_offset;
 156         int     tx_st_done;
 157         bool    high_speed;
 158         bool    clk_from_cmu;
 159 };
 160
 161 /**
 162  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 163  * @clk: Pointer to the spi clock.
 164  * @src_clk: Pointer to the clock used to generate SPI signals.
 165  * @master: Pointer to the SPI Protocol master.
 166  * @cntrlr_info: Platform specific data for the controller this driver manages.
 167  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 168  * @queue: To log SPI xfer requests.
 169  * @lock: Controller specific lock.
 170  * @state: Set of FLAGS to indicate status.
 171  * @rx_dmach: Controller's DMA channel for Rx.
 172  * @tx_dmach: Controller's DMA channel for Tx.
 173  * @sfr_start: BUS address of SPI controller regs.
 174  * @regs: Pointer to ioremap'ed controller registers.
 175  * @irq: interrupt
 176  * @xfer_completion: To indicate completion of xfer task.
 177  * @cur_mode: Stores the active configuration of the controller.
 178  * @cur_bpw: Stores the active bits per word settings.
 179  * @cur_speed: Stores the active xfer clock speed.
 180  */
 181 struct s3c64xx_spi_driver_data {
 182         void __iomem                    *regs;
 183         struct clk                      *clk;
 184         struct clk                      *src_clk;
 185         struct platform_device          *pdev;
 186         struct spi_master               *master;
 187         struct s3c64xx_spi_info  *cntrlr_info;
 188         struct spi_device               *tgl_spi;
 189         struct list_head                queue;
 190         spinlock_t                      lock;
 191         unsigned long                   sfr_start;
 192         struct completion               xfer_completion;
 193         unsigned                        state;
 194         unsigned                        cur_mode, cur_bpw;
 195         unsigned                        cur_speed;
 196         struct s3c64xx_spi_dma_data     rx_dma;
 197         struct s3c64xx_spi_dma_data     tx_dma;
 198         struct samsung_dma_ops          *ops;
 199         struct s3c64xx_spi_port_config  *port_conf;
 200         unsigned int                    port_id;
 201         unsigned long                   gpios[4];
 202 };
 203
 204 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 205         .name = "samsung-spi-dma",
 206 };
 207
 208 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 209 {
 210         void __iomem *regs = sdd->regs;
 211         unsigned long loops;
 212         u32 val;
 213
 214         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 215
 216         val = readl(regs + S3C64XX_SPI_CH_CFG);
 217         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 218         writel(val, regs + S3C64XX_SPI_CH_CFG);
 219
 220         val = readl(regs + S3C64XX_SPI_CH_CFG);
 221         val |= S3C64XX_SPI_CH_SW_RST;
 222         val &= ~S3C64XX_SPI_CH_HS_EN;
 223         writel(val, regs + S3C64XX_SPI_CH_CFG);
 224
 225         /* Flush TxFIFO*/
 226         loops = msecs_to_loops(1);
 227         do {
 228                 val = readl(regs + S3C64XX_SPI_STATUS);
 229         } while (TX_FIFO_LVL(val, sdd) && loops--);
 230
 231         if (loops == 0)
 232                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 233
 234         /* Flush RxFIFO*/
 235         loops = msecs_to_loops(1);
 236         do {
 237                 val = readl(regs + S3C64XX_SPI_STATUS);
 238                 if (RX_FIFO_LVL(val, sdd))
 239                         readl(regs + S3C64XX_SPI_RX_DATA);
 240                 else
 241                         break;
 242         } while (loops--);
 243
 244         if (loops == 0)
 245                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 246
 247         val = readl(regs + S3C64XX_SPI_CH_CFG);
 248         val &= ~S3C64XX_SPI_CH_SW_RST;
 249         writel(val, regs + S3C64XX_SPI_CH_CFG);
 250
 251         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 252         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 253         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 254 }
 255
 256 static void s3c64xx_spi_dmacb(void *data)
 257 {
 258         struct s3c64xx_spi_driver_data *sdd;
 259         struct s3c64xx_spi_dma_data *dma = data;
 260         unsigned long flags;
 261
 262         if (dma->direction == DMA_DEV_TO_MEM)
 263                 sdd = container_of(data,
 264                         struct s3c64xx_spi_driver_data, rx_dma);
 265         else
 266                 sdd = container_of(data,
 267                         struct s3c64xx_spi_driver_data, tx_dma);
 268
 269         spin_lock_irqsave(&sdd->lock, flags);
 270
 271         if (dma->direction == DMA_DEV_TO_MEM) {
 272                 sdd->state &= ~RXBUSY;
 273                 if (!(sdd->state & TXBUSY))
 274                         complete(&sdd->xfer_completion);
 275         } else {
 276                 sdd->state &= ~TXBUSY;
 277                 if (!(sdd->state & RXBUSY))
 278                         complete(&sdd->xfer_completion);
 279         }
 280
 281         spin_unlock_irqrestore(&sdd->lock, flags);
 282 }
 283
 284 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 285                                         unsigned len, dma_addr_t buf)
 286 {
 287         struct s3c64xx_spi_driver_data *sdd;
 288         struct samsung_dma_prep info;
 289         struct samsung_dma_config config;
 290
 291         if (dma->direction == DMA_DEV_TO_MEM) {
 292                 sdd = container_of((void *)dma,
 293                         struct s3c64xx_spi_driver_data, rx_dma);
 294                 config.direction = sdd->rx_dma.direction;
 295                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 296                 config.width = sdd->cur_bpw / 8;
 297                 sdd->ops->config(sdd->rx_dma.ch, &config);
 298         } else {
 299                 sdd = container_of((void *)dma,
 300                         struct s3c64xx_spi_driver_data, tx_dma);
 301                 config.direction =  sdd->tx_dma.direction;
 302                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 303                 config.width = sdd->cur_bpw / 8;
 304                 sdd->ops->config(sdd->tx_dma.ch, &config);
 305         }
 306
 307         info.cap = DMA_SLAVE;
 308         info.len = len;
 309         info.fp = s3c64xx_spi_dmacb;
 310         info.fp_param = dma;
 311         info.direction = dma->direction;
 312         info.buf = buf;
 313
 314         sdd->ops->prepare(dma->ch, &info);
 315         sdd->ops->trigger(dma->ch);
 316 }
 317
 318 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 319 {
 320         struct samsung_dma_req req;
 321         struct device *dev = &sdd->pdev->dev;
 322
 323         sdd->ops = samsung_dma_get_ops();
 324
 325         req.cap = DMA_SLAVE;
 326         req.client = &s3c64xx_spi_dma_client;
 327
 328         sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
 329         sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
 330
 331         return 1;
 332 }
 333
 334 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 335                                 struct spi_device *spi,
 336                                 struct spi_transfer *xfer, int dma_mode)
 337 {
 338         void __iomem *regs = sdd->regs;
 339         u32 modecfg, chcfg;
 340
 341         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 342         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 343
 344         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 345         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 346
 347         if (dma_mode) {
 348                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 349         } else {
 350                 /* Always shift in data in FIFO, even if xfer is Tx only,
 351                  * this helps setting PCKT_CNT value for generating clocks
 352                  * as exactly needed.
 353                  */
 354                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 355                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 356                                         | S3C64XX_SPI_PACKET_CNT_EN,
 357                                         regs + S3C64XX_SPI_PACKET_CNT);
 358         }
 359
 360         if (xfer->tx_buf != NULL) {
 361                 sdd->state |= TXBUSY;
 362                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 363                 if (dma_mode) {
 364                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 365                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 366                 } else {
 367                         switch (sdd->cur_bpw) {
 368                         case 32:
 369                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 370                                         xfer->tx_buf, xfer->len / 4);
 371                                 break;
 372                         case 16:
 373                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 374                                         xfer->tx_buf, xfer->len / 2);
 375                                 break;
 376                         default:
 377                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 378                                         xfer->tx_buf, xfer->len);
 379                                 break;
 380                         }
 381                 }
 382         }
 383
 384         if (xfer->rx_buf != NULL) {
 385                 sdd->state |= RXBUSY;
 386
 387                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 388                                         && !(sdd->cur_mode & SPI_CPHA))
 389                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 390
 391                 if (dma_mode) {
 392                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 393                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 394                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 395                                         | S3C64XX_SPI_PACKET_CNT_EN,
 396                                         regs + S3C64XX_SPI_PACKET_CNT);
 397                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 398                 }
 399         }
 400
 401         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 402         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 403 }
 404
 405 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 406                                                 struct spi_device *spi)
 407 {
 408         struct s3c64xx_spi_csinfo *cs;
 409
 410         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 411                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 412                         /* Deselect the last toggled device */
 413                         cs = sdd->tgl_spi->controller_data;
 414                         gpio_set_value(cs->line,
 415                                 spi->mode & SPI_CS_HIGH ? 0 : 1);
 416                 }
 417                 sdd->tgl_spi = NULL;
 418         }
 419
 420         cs = spi->controller_data;
 421         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 422 }
 423
 424 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 425                                 struct spi_transfer *xfer, int dma_mode)
 426 {
 427         void __iomem *regs = sdd->regs;
 428         unsigned long val;
 429         int ms;
 430
 431         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 432         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 433         ms += 10; /* some tolerance */
 434
 435         if (dma_mode) {
 436                 val = msecs_to_jiffies(ms) + 10;
 437                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 438         } else {
 439                 u32 status;
 440                 val = msecs_to_loops(ms);
 441                 do {
 442                         status = readl(regs + S3C64XX_SPI_STATUS);
 443                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 444         }
 445
 446         if (!val)
 447                 return -EIO;
 448
 449         if (dma_mode) {
 450                 u32 status;
 451
 452                 /*
 453                  * DmaTx returns after simply writing data in the FIFO,
 454                  * w/o waiting for real transmission on the bus to finish.
 455                  * DmaRx returns only after Dma read data from FIFO which
 456                  * needs bus transmission to finish, so we don't worry if
 457                  * Xfer involved Rx(with or without Tx).
 458                  */
 459                 if (xfer->rx_buf == NULL) {
 460                         val = msecs_to_loops(10);
 461                         status = readl(regs + S3C64XX_SPI_STATUS);
 462                         while ((TX_FIFO_LVL(status, sdd)
 463                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 464                                         && --val) {
 465                                 cpu_relax();
 466                                 status = readl(regs + S3C64XX_SPI_STATUS);
 467                         }
 468
 469                         if (!val)
 470                                 return -EIO;
 471                 }
 472         } else {
 473                 /* If it was only Tx */
 474                 if (xfer->rx_buf == NULL) {
 475                         sdd->state &= ~TXBUSY;
 476                         return 0;
 477                 }
 478
 479                 switch (sdd->cur_bpw) {
 480                 case 32:
 481                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 482                                 xfer->rx_buf, xfer->len / 4);
 483                         break;
 484                 case 16:
 485                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 486                                 xfer->rx_buf, xfer->len / 2);
 487                         break;
 488                 default:
 489                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 490                                 xfer->rx_buf, xfer->len);
 491                         break;
 492                 }
 493                 sdd->state &= ~RXBUSY;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 500                                                 struct spi_device *spi)
 501 {
 502         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 503
 504         if (sdd->tgl_spi == spi)
 505                 sdd->tgl_spi = NULL;
 506
 507         gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 508 }
 509
 510 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 511 {
 512         void __iomem *regs = sdd->regs;
 513         u32 val;
 514
 515         /* Disable Clock */
 516         if (sdd->port_conf->clk_from_cmu) {
 517                 clk_disable_unprepare(sdd->src_clk);
 518         } else {
 519                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 520                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 521                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 522         }
 523
 524         /* Set Polarity and Phase */
 525         val = readl(regs + S3C64XX_SPI_CH_CFG);
 526         val &= ~(S3C64XX_SPI_CH_SLAVE |
 527                         S3C64XX_SPI_CPOL_L |
 528                         S3C64XX_SPI_CPHA_B);
 529
 530         if (sdd->cur_mode & SPI_CPOL)
 531                 val |= S3C64XX_SPI_CPOL_L;
 532
 533         if (sdd->cur_mode & SPI_CPHA)
 534                 val |= S3C64XX_SPI_CPHA_B;
 535
 536         writel(val, regs + S3C64XX_SPI_CH_CFG);
 537
 538         /* Set Channel & DMA Mode */
 539         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 540         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 541                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 542
 543         switch (sdd->cur_bpw) {
 544         case 32:
 545                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 546                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 547                 break;
 548         case 16:
 549                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 550                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 551                 break;
 552         default:
 553                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 554                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 555                 break;
 556         }
 557
 558         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 559
 560         if (sdd->port_conf->clk_from_cmu) {
 561                 /* Configure Clock */
 562                 /* There is half-multiplier before the SPI */
 563                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 564                 /* Enable Clock */
 565                 clk_prepare_enable(sdd->src_clk);
 566         } else {
 567                 /* Configure Clock */
 568                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 569                 val &= ~S3C64XX_SPI_PSR_MASK;
 570                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 571                                 & S3C64XX_SPI_PSR_MASK);
 572                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 573
 574                 /* Enable Clock */
 575                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 576                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 577                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 578         }
 579 }
 580
 581 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 582
 583 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 584                                                 struct spi_message *msg)
 585 {
 586         struct device *dev = &sdd->pdev->dev;
 587         struct spi_transfer *xfer;
 588
 589         if (msg->is_dma_mapped)
 590                 return 0;
 591
 592         /* First mark all xfer unmapped */
 593         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 594                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 595                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 596         }
 597
 598         /* Map until end or first fail */
 599         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 600
 601                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 602                         continue;
 603
 604                 if (xfer->tx_buf != NULL) {
 605                         xfer->tx_dma = dma_map_single(dev,
 606                                         (void *)xfer->tx_buf, xfer->len,
 607                                         DMA_TO_DEVICE);
 608                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 609                                 dev_err(dev, "dma_map_single Tx failed\n");
 610                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 611                                 return -ENOMEM;
 612                         }
 613                 }
 614
 615                 if (xfer->rx_buf != NULL) {
 616                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 617                                                 xfer->len, DMA_FROM_DEVICE);
 618                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 619                                 dev_err(dev, "dma_map_single Rx failed\n");
 620                                 dma_unmap_single(dev, xfer->tx_dma,
 621                                                 xfer->len, DMA_TO_DEVICE);
 622                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 623                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 624                                 return -ENOMEM;
 625                         }
 626                 }
 627         }
 628
 629         return 0;
 630 }
 631
 632 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 633                                                 struct spi_message *msg)
 634 {
 635         struct device *dev = &sdd->pdev->dev;
 636         struct spi_transfer *xfer;
 637
 638         if (msg->is_dma_mapped)
 639                 return;
 640
 641         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 642
 643                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 644                         continue;
 645
 646                 if (xfer->rx_buf != NULL
 647                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 648                         dma_unmap_single(dev, xfer->rx_dma,
 649                                                 xfer->len, DMA_FROM_DEVICE);
 650
 651                 if (xfer->tx_buf != NULL
 652                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 653                         dma_unmap_single(dev, xfer->tx_dma,
 654                                                 xfer->len, DMA_TO_DEVICE);
 655         }
 656 }
 657
 658 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 659                                             struct spi_message *msg)
 660 {
 661         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 662         struct spi_device *spi = msg->spi;
 663         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 664         struct spi_transfer *xfer;
 665         int status = 0, cs_toggle = 0;
 666         u32 speed;
 667         u8 bpw;
 668
 669         /* If Master's(controller) state differs from that needed by Slave */
 670         if (sdd->cur_speed != spi->max_speed_hz
 671                         || sdd->cur_mode != spi->mode
 672                         || sdd->cur_bpw != spi->bits_per_word) {
 673                 sdd->cur_bpw = spi->bits_per_word;
 674                 sdd->cur_speed = spi->max_speed_hz;
 675                 sdd->cur_mode = spi->mode;
 676                 s3c64xx_spi_config(sdd);
 677         }
 678
 679         /* Map all the transfers if needed */
 680         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 681                 dev_err(&spi->dev,
 682                         "Xfer: Unable to map message buffers!\n");
 683                 status = -ENOMEM;
 684                 goto out;
 685         }
 686
 687         /* Configure feedback delay */
 688         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 689
 690         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 691
 692                 unsigned long flags;
 693                 int use_dma;
 694
 695                 INIT_COMPLETION(sdd->xfer_completion);
 696
 697                 /* Only BPW and Speed may change across transfers */
 698                 bpw = xfer->bits_per_word;
 699                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 700
 701                 if (xfer->len % (bpw / 8)) {
 702                         dev_err(&spi->dev,
 703                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 704                                 xfer->len, bpw / 8);
 705                         status = -EIO;
 706                         goto out;
 707                 }
 708
 709                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 710                         sdd->cur_bpw = bpw;
 711                         sdd->cur_speed = speed;
 712                         s3c64xx_spi_config(sdd);
 713                 }
 714
 715                 /* Polling method for xfers not bigger than FIFO capacity */
 716                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 717                         use_dma = 0;
 718                 else
 719                         use_dma = 1;
 720
 721                 spin_lock_irqsave(&sdd->lock, flags);
 722
 723                 /* Pending only which is to be done */
 724                 sdd->state &= ~RXBUSY;
 725                 sdd->state &= ~TXBUSY;
 726
 727                 enable_datapath(sdd, spi, xfer, use_dma);
 728
 729                 /* Slave Select */
 730                 enable_cs(sdd, spi);
 731
 732                 /* Start the signals */
 733                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 734
 735                 spin_unlock_irqrestore(&sdd->lock, flags);
 736
 737                 status = wait_for_xfer(sdd, xfer, use_dma);
 738
 739                 /* Quiese the signals */
 740                 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 741                        sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 742
 743                 if (status) {
 744                         dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 745                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 746                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 747                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 748                                 xfer->len);
 749
 750                         if (use_dma) {
 751                                 if (xfer->tx_buf != NULL
 752                                                 && (sdd->state & TXBUSY))
 753                                         sdd->ops->stop(sdd->tx_dma.ch);
 754                                 if (xfer->rx_buf != NULL
 755                                                 && (sdd->state & RXBUSY))
 756                                         sdd->ops->stop(sdd->rx_dma.ch);
 757                         }
 758
 759                         goto out;
 760                 }
 761
 762                 if (xfer->delay_usecs)
 763                         udelay(xfer->delay_usecs);
 764
 765                 if (xfer->cs_change) {
 766                         /* Hint that the next mssg is gonna be
 767                            for the same device */
 768                         if (list_is_last(&xfer->transfer_list,
 769                                                 &msg->transfers))
 770                                 cs_toggle = 1;
 771                 }
 772
 773                 msg->actual_length += xfer->len;
 774
 775                 flush_fifo(sdd);
 776         }
 777
 778 out:
 779         if (!cs_toggle || status)
 780                 disable_cs(sdd, spi);
 781         else
 782                 sdd->tgl_spi = spi;
 783
 784         s3c64xx_spi_unmap_mssg(sdd, msg);
 785
 786         msg->status = status;
 787
 788         spi_finalize_current_message(master);
 789
 790         return 0;
 791 }
 792
 793 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 794 {
 795         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 796
 797         /* Acquire DMA channels */
 798         while (!acquire_dma(sdd))
 799                 usleep_range(10000, 11000);
 800
 801         pm_runtime_get_sync(&sdd->pdev->dev);
 802
 803         return 0;
 804 }
 805
 806 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 807 {
 808         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 809
 810         /* Free DMA channels */
 811         sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
 812         sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
 813
 814         pm_runtime_put(&sdd->pdev->dev);
 815
 816         return 0;
 817 }
 818
 819 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 820                                 struct s3c64xx_spi_driver_data *sdd,
 821                                 struct spi_device *spi)
 822 {
 823         struct s3c64xx_spi_csinfo *cs;
 824         struct device_node *slave_np, *data_np = NULL;
 825         u32 fb_delay = 0;
 826
 827         slave_np = spi->dev.of_node;
 828         if (!slave_np) {
 829                 dev_err(&spi->dev, "device node not found\n");
 830                 return ERR_PTR(-EINVAL);
 831         }
 832
 833         data_np = of_get_child_by_name(slave_np, "controller-data");
 834         if (!data_np) {
 835                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 836                 return ERR_PTR(-EINVAL);
 837         }
 838
 839         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 840         if (!cs) {
 841                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
 842                 of_node_put(data_np);
 843                 return ERR_PTR(-ENOMEM);
 844         }
 845
 846         cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 847         if (!gpio_is_valid(cs->line)) {
 848                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
 849                 kfree(cs);
 850                 of_node_put(data_np);
 851                 return ERR_PTR(-EINVAL);
 852         }
 853
 854         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 855         cs->fb_delay = fb_delay;
 856         of_node_put(data_np);
 857         return cs;
 858 }
 859
 860 /*
 861  * Here we only check the validity of requested configuration
 862  * and save the configuration in a local data-structure.
 863  * The controller is actually configured only just before we
 864  * get a message to transfer.
 865  */
 866 static int s3c64xx_spi_setup(struct spi_device *spi)
 867 {
 868         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 869         struct s3c64xx_spi_driver_data *sdd;
 870         struct s3c64xx_spi_info *sci;
 871         struct spi_message *msg;
 872         unsigned long flags;
 873         int err;
 874
 875         sdd = spi_master_get_devdata(spi->master);
 876         if (!cs && spi->dev.of_node) {
 877                 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
 878                 spi->controller_data = cs;
 879         }
 880
 881         if (IS_ERR_OR_NULL(cs)) {
 882                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 883                 return -ENODEV;
 884         }
 885
 886         if (!spi_get_ctldata(spi)) {
 887                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
 888                                        dev_name(&spi->dev));
 889                 if (err) {
 890                         dev_err(&spi->dev,
 891                                 "Failed to get /CS gpio [%d]: %d\n",
 892                                 cs->line, err);
 893                         goto err_gpio_req;
 894                 }
 895                 spi_set_ctldata(spi, cs);
 896         }
 897
 898         sci = sdd->cntrlr_info;
 899
 900         spin_lock_irqsave(&sdd->lock, flags);
 901
 902         list_for_each_entry(msg, &sdd->queue, queue) {
 903                 /* Is some mssg is already queued for this device */
 904                 if (msg->spi == spi) {
 905                         dev_err(&spi->dev,
 906                                 "setup: attempt while mssg in queue!\n");
 907                         spin_unlock_irqrestore(&sdd->lock, flags);
 908                         err = -EBUSY;
 909                         goto err_msgq;
 910                 }
 911         }
 912
 913         spin_unlock_irqrestore(&sdd->lock, flags);
 914
 915         if (spi->bits_per_word != 8
 916                         && spi->bits_per_word != 16
 917                         && spi->bits_per_word != 32) {
 918                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 919                                                         spi->bits_per_word);
 920                 err = -EINVAL;
 921                 goto setup_exit;
 922         }
 923
 924         pm_runtime_get_sync(&sdd->pdev->dev);
 925
 926         /* Check if we can provide the requested rate */
 927         if (!sdd->port_conf->clk_from_cmu) {
 928                 u32 psr, speed;
 929
 930                 /* Max possible */
 931                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 932
 933                 if (spi->max_speed_hz > speed)
 934                         spi->max_speed_hz = speed;
 935
 936                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 937                 psr &= S3C64XX_SPI_PSR_MASK;
 938                 if (psr == S3C64XX_SPI_PSR_MASK)
 939                         psr--;
 940
 941                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 942                 if (spi->max_speed_hz < speed) {
 943                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 944                                 psr++;
 945                         } else {
 946                                 err = -EINVAL;
 947                                 goto setup_exit;
 948                         }
 949                 }
 950
 951                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 952                 if (spi->max_speed_hz >= speed) {
 953                         spi->max_speed_hz = speed;
 954                 } else {
 955                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 956                                 spi->max_speed_hz);
 957                         err = -EINVAL;
 958                         goto setup_exit;
 959                 }
 960         }
 961
 962         pm_runtime_put(&sdd->pdev->dev);
 963         disable_cs(sdd, spi);
 964         return 0;
 965
 966 setup_exit:
 967         /* setup() returns with device de-selected */
 968         disable_cs(sdd, spi);
 969
 970 err_msgq:
 971         gpio_free(cs->line);
 972         spi_set_ctldata(spi, NULL);
 973
 974 err_gpio_req:
 975         if (spi->dev.of_node)
 976                 kfree(cs);
 977
 978         return err;
 979 }
 980
 981 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 982 {
 983         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 984
 985         if (cs) {
 986                 gpio_free(cs->line);
 987                 if (spi->dev.of_node)
 988                         kfree(cs);
 989         }
 990         spi_set_ctldata(spi, NULL);
 991 }
 992
 993 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 994 {
 995         struct s3c64xx_spi_driver_data *sdd = data;
 996         struct spi_master *spi = sdd->master;
 997         unsigned int val, clr = 0;
 998
 999         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1000
1001         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1002                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1003                 dev_err(&spi->dev, "RX overrun\n");
1004         }
1005         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1006                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1007                 dev_err(&spi->dev, "RX underrun\n");
1008         }
1009         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1010                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1011                 dev_err(&spi->dev, "TX overrun\n");
1012         }
1013         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1014                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1015                 dev_err(&spi->dev, "TX underrun\n");
1016         }
1017
1018         /* Clear the pending irq by setting and then clearing it */
1019         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1020         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1021
1022         return IRQ_HANDLED;
1023 }
1024
1025 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1026 {
1027         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1028         void __iomem *regs = sdd->regs;
1029         unsigned int val;
1030
1031         sdd->cur_speed = 0;
1032
1033         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1034
1035         /* Disable Interrupts - we use Polling if not DMA mode */
1036         writel(0, regs + S3C64XX_SPI_INT_EN);
1037
1038         if (!sdd->port_conf->clk_from_cmu)
1039                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1040                                 regs + S3C64XX_SPI_CLK_CFG);
1041         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1042         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1043
1044         /* Clear any irq pending bits, should set and clear the bits */
1045         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1046                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1047                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1048                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1049         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1050         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1051
1052         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1053
1054         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1055         val &= ~S3C64XX_SPI_MODE_4BURST;
1056         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1057         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1058         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1059
1060         flush_fifo(sdd);
1061 }
1062
1063 #ifdef CONFIG_OF
1064 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1065 {
1066         struct device *dev = &sdd->pdev->dev;
1067         int idx, gpio, ret;
1068
1069         /* find gpios for mosi, miso and clock lines */
1070         for (idx = 0; idx < 3; idx++) {
1071                 gpio = of_get_gpio(dev->of_node, idx);
1072                 if (!gpio_is_valid(gpio)) {
1073                         dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1074                         goto free_gpio;
1075                 }
1076                 sdd->gpios[idx] = gpio;
1077                 ret = gpio_request(gpio, "spi-bus");
1078                 if (ret) {
1079                         dev_err(dev, "gpio [%d] request failed: %d\n",
1080                                 gpio, ret);
1081                         goto free_gpio;
1082                 }
1083         }
1084         return 0;
1085
1086 free_gpio:
1087         while (--idx >= 0)
1088                 gpio_free(sdd->gpios[idx]);
1089         return -EINVAL;
1090 }
1091
1092 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1093 {
1094         unsigned int idx;
1095         for (idx = 0; idx < 3; idx++)
1096                 gpio_free(sdd->gpios[idx]);
1097 }
1098
1099 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1100 {
1101         struct s3c64xx_spi_info *sci;
1102         u32 temp;
1103
1104         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1105         if (!sci) {
1106                 dev_err(dev, "memory allocation for spi_info failed\n");
1107                 return ERR_PTR(-ENOMEM);
1108         }
1109
1110         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1111                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1112                 sci->src_clk_nr = 0;
1113         } else {
1114                 sci->src_clk_nr = temp;
1115         }
1116
1117         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1118                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1119                 sci->num_cs = 1;
1120         } else {
1121                 sci->num_cs = temp;
1122         }
1123
1124         return sci;
1125 }
1126 #else
1127 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1128 {
1129         return dev->platform_data;
1130 }
1131
1132 static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1133 {
1134         return -EINVAL;
1135 }
1136
1137 static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1138 {
1139 }
1140 #endif
1141
1142 static const struct of_device_id s3c64xx_spi_dt_match[];
1143
1144 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1145                                                 struct platform_device *pdev)
1146 {
1147 #ifdef CONFIG_OF
1148         if (pdev->dev.of_node) {
1149                 const struct of_device_id *match;
1150                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1151                 return (struct s3c64xx_spi_port_config *)match->data;
1152         }
1153 #endif
1154         return (struct s3c64xx_spi_port_config *)
1155                          platform_get_device_id(pdev)->driver_data;
1156 }
1157
1158 static int s3c64xx_spi_probe(struct platform_device *pdev)
1159 {
1160         struct resource *mem_res;
1161         struct resource *res;
1162         struct s3c64xx_spi_driver_data *sdd;
1163         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1164         struct spi_master *master;
1165         int ret, irq;
1166         char clk_name[16];
1167
1168         if (!sci && pdev->dev.of_node) {
1169                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1170                 if (IS_ERR(sci))
1171                         return PTR_ERR(sci);
1172         }
1173
1174         if (!sci) {
1175                 dev_err(&pdev->dev, "platform_data missing!\n");
1176                 return -ENODEV;
1177         }
1178
1179         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180         if (mem_res == NULL) {
1181                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1182                 return -ENXIO;
1183         }
1184
1185         irq = platform_get_irq(pdev, 0);
1186         if (irq < 0) {
1187                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1188                 return irq;
1189         }
1190
1191         master = spi_alloc_master(&pdev->dev,
1192                                 sizeof(struct s3c64xx_spi_driver_data));
1193         if (master == NULL) {
1194                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1195                 return -ENOMEM;
1196         }
1197
1198         platform_set_drvdata(pdev, master);
1199
1200         sdd = spi_master_get_devdata(master);
1201         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1202         sdd->master = master;
1203         sdd->cntrlr_info = sci;
1204         sdd->pdev = pdev;
1205         sdd->sfr_start = mem_res->start;
1206         if (pdev->dev.of_node) {
1207                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1208                 if (ret < 0) {
1209                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1210                                 ret);
1211                         goto err0;
1212                 }
1213                 sdd->port_id = ret;
1214         } else {
1215                 sdd->port_id = pdev->id;
1216         }
1217
1218         sdd->cur_bpw = 8;
1219
1220         if (!sdd->pdev->dev.of_node) {
1221                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1222                 if (!res) {
1223                         dev_err(&pdev->dev, "Unable to get SPI tx dma "
1224                                         "resource\n");
1225                         return -ENXIO;
1226                 }
1227                 sdd->tx_dma.dmach = res->start;
1228
1229                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1230                 if (!res) {
1231                         dev_err(&pdev->dev, "Unable to get SPI rx dma "
1232                                         "resource\n");
1233                         return -ENXIO;
1234                 }
1235                 sdd->rx_dma.dmach = res->start;
1236         }
1237
1238         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1239         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1240
1241         master->dev.of_node = pdev->dev.of_node;
1242         master->bus_num = sdd->port_id;
1243         master->setup = s3c64xx_spi_setup;
1244         master->cleanup = s3c64xx_spi_cleanup;
1245         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1246         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1247         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1248         master->num_chipselect = sci->num_cs;
1249         master->dma_alignment = 8;
1250         /* the spi->mode bits understood by this driver: */
1251         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1252
1253         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1254         if (IS_ERR(sdd->regs)) {
1255                 ret = PTR_ERR(sdd->regs);
1256                 goto err0;
1257         }
1258
1259         if (!sci->cfg_gpio && pdev->dev.of_node) {
1260                 if (s3c64xx_spi_parse_dt_gpio(sdd))
1261                         return -EBUSY;
1262         } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
1263                 dev_err(&pdev->dev, "Unable to config gpio\n");
1264                 ret = -EBUSY;
1265                 goto err0;
1266         }
1267
1268         /* Setup clocks */
1269         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1270         if (IS_ERR(sdd->clk)) {
1271                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1272                 ret = PTR_ERR(sdd->clk);
1273                 goto err1;
1274         }
1275
1276         if (clk_prepare_enable(sdd->clk)) {
1277                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1278                 ret = -EBUSY;
1279                 goto err1;
1280         }
1281
1282         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1283         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1284         if (IS_ERR(sdd->src_clk)) {
1285                 dev_err(&pdev->dev,
1286                         "Unable to acquire clock '%s'\n", clk_name);
1287                 ret = PTR_ERR(sdd->src_clk);
1288                 goto err2;
1289         }
1290
1291         if (clk_prepare_enable(sdd->src_clk)) {
1292                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1293                 ret = -EBUSY;
1294                 goto err2;
1295         }
1296
1297         /* Setup Deufult Mode */
1298         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1299
1300         spin_lock_init(&sdd->lock);
1301         init_completion(&sdd->xfer_completion);
1302         INIT_LIST_HEAD(&sdd->queue);
1303
1304         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1305                                 "spi-s3c64xx", sdd);
1306         if (ret != 0) {
1307                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1308                         irq, ret);
1309                 goto err3;
1310         }
1311
1312         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1313                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1314                sdd->regs + S3C64XX_SPI_INT_EN);
1315
1316         if (spi_register_master(master)) {
1317                 dev_err(&pdev->dev, "cannot register SPI master\n");
1318                 ret = -EBUSY;
1319                 goto err3;
1320         }
1321
1322         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1323                                         sdd->port_id, master->num_chipselect);
1324         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1325                                         mem_res->end, mem_res->start,
1326                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1327
1328         pm_runtime_enable(&pdev->dev);
1329
1330         return 0;
1331
1332 err3:
1333         clk_disable_unprepare(sdd->src_clk);
1334 err2:
1335         clk_disable_unprepare(sdd->clk);
1336 err1:
1337         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1338                 s3c64xx_spi_dt_gpio_free(sdd);
1339 err0:
1340         platform_set_drvdata(pdev, NULL);
1341         spi_master_put(master);
1342
1343         return ret;
1344 }
1345
1346 static int s3c64xx_spi_remove(struct platform_device *pdev)
1347 {
1348         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1349         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1350
1351         pm_runtime_disable(&pdev->dev);
1352
1353         spi_unregister_master(master);
1354
1355         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1356
1357         clk_disable_unprepare(sdd->src_clk);
1358
1359         clk_disable_unprepare(sdd->clk);
1360
1361         if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1362                 s3c64xx_spi_dt_gpio_free(sdd);
1363
1364         platform_set_drvdata(pdev, NULL);
1365         spi_master_put(master);
1366
1367         return 0;
1368 }
1369
1370 #ifdef CONFIG_PM
1371 static int s3c64xx_spi_suspend(struct device *dev)
1372 {
1373         struct spi_master *master = dev_get_drvdata(dev);
1374         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1375
1376         spi_master_suspend(master);
1377
1378         /* Disable the clock */
1379         clk_disable_unprepare(sdd->src_clk);
1380         clk_disable_unprepare(sdd->clk);
1381
1382         if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1383                 s3c64xx_spi_dt_gpio_free(sdd);
1384
1385         sdd->cur_speed = 0; /* Output Clock is stopped */
1386
1387         return 0;
1388 }
1389
1390 static int s3c64xx_spi_resume(struct device *dev)
1391 {
1392         struct spi_master *master = dev_get_drvdata(dev);
1393         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1394         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1395
1396         if (!sci->cfg_gpio && dev->of_node)
1397                 s3c64xx_spi_parse_dt_gpio(sdd);
1398         else
1399                 sci->cfg_gpio();
1400
1401         /* Enable the clock */
1402         clk_prepare_enable(sdd->src_clk);
1403         clk_prepare_enable(sdd->clk);
1404
1405         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1406
1407         spi_master_resume(master);
1408
1409         return 0;
1410 }
1411 #endif /* CONFIG_PM */
1412
1413 #ifdef CONFIG_PM_RUNTIME
1414 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1415 {
1416         struct spi_master *master = dev_get_drvdata(dev);
1417         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1418
1419         clk_disable_unprepare(sdd->clk);
1420         clk_disable_unprepare(sdd->src_clk);
1421
1422         return 0;
1423 }
1424
1425 static int s3c64xx_spi_runtime_resume(struct device *dev)
1426 {
1427         struct spi_master *master = dev_get_drvdata(dev);
1428         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1429
1430         clk_prepare_enable(sdd->src_clk);
1431         clk_prepare_enable(sdd->clk);
1432
1433         return 0;
1434 }
1435 #endif /* CONFIG_PM_RUNTIME */
1436
1437 static const struct dev_pm_ops s3c64xx_spi_pm = {
1438         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1439         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1440                            s3c64xx_spi_runtime_resume, NULL)
1441 };
1442
1443 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1444         .fifo_lvl_mask  = { 0x7f },
1445         .rx_lvl_offset  = 13,
1446         .tx_st_done     = 21,
1447         .high_speed     = true,
1448 };
1449
1450 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1451         .fifo_lvl_mask  = { 0x7f, 0x7F },
1452         .rx_lvl_offset  = 13,
1453         .tx_st_done     = 21,
1454 };
1455
1456 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1457         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1458         .rx_lvl_offset  = 15,
1459         .tx_st_done     = 25,
1460 };
1461
1462 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1463         .fifo_lvl_mask  = { 0x7f, 0x7F },
1464         .rx_lvl_offset  = 13,
1465         .tx_st_done     = 21,
1466         .high_speed     = true,
1467 };
1468
1469 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1470         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1471         .rx_lvl_offset  = 15,
1472         .tx_st_done     = 25,
1473         .high_speed     = true,
1474 };
1475
1476 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1477         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1478         .rx_lvl_offset  = 15,
1479         .tx_st_done     = 25,
1480         .high_speed     = true,
1481         .clk_from_cmu   = true,
1482 };
1483
1484 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1485         {
1486                 .name           = "s3c2443-spi",
1487                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1488         }, {
1489                 .name           = "s3c6410-spi",
1490                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1491         }, {
1492                 .name           = "s5p64x0-spi",
1493                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1494         }, {
1495                 .name           = "s5pc100-spi",
1496                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1497         }, {
1498                 .name           = "s5pv210-spi",
1499                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1500         }, {
1501                 .name           = "exynos4210-spi",
1502                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1503         },
1504         { },
1505 };
1506
1507 #ifdef CONFIG_OF
1508 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1509         { .compatible = "samsung,exynos4210-spi",
1510                         .data = (void *)&exynos4_spi_port_config,
1511         },
1512         { },
1513 };
1514 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1515 #endif /* CONFIG_OF */
1516
1517 static struct platform_driver s3c64xx_spi_driver = {
1518         .driver = {
1519                 .name   = "s3c64xx-spi",
1520                 .owner = THIS_MODULE,
1521                 .pm = &s3c64xx_spi_pm,
1522                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1523         },
1524         .remove = s3c64xx_spi_remove,
1525         .id_table = s3c64xx_spi_driver_ids,
1526 };
1527 MODULE_ALIAS("platform:s3c64xx-spi");
1528
1529 static int __init s3c64xx_spi_init(void)
1530 {
1531         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1532 }
1533 subsys_initcall(s3c64xx_spi_init);
1534
1535 static void __exit s3c64xx_spi_exit(void)
1536 {
1537         platform_driver_unregister(&s3c64xx_spi_driver);
1538 }
1539 module_exit(s3c64xx_spi_exit);
1540
1541 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1542 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1543 MODULE_LICENSE("GPL");