2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/workqueue.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spi/spi.h>
31 #include <linux/gpio.h>
33 #include <linux/of_gpio.h>
35 #include <linux/platform_data/spi-s3c64xx.h>
37 #define MAX_SPI_PORTS 3
38 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
40 /* Registers and bit-fields */
42 #define S3C64XX_SPI_CH_CFG 0x00
43 #define S3C64XX_SPI_CLK_CFG 0x04
44 #define S3C64XX_SPI_MODE_CFG 0x08
45 #define S3C64XX_SPI_SLAVE_SEL 0x0C
46 #define S3C64XX_SPI_INT_EN 0x10
47 #define S3C64XX_SPI_STATUS 0x14
48 #define S3C64XX_SPI_TX_DATA 0x18
49 #define S3C64XX_SPI_RX_DATA 0x1C
50 #define S3C64XX_SPI_PACKET_CNT 0x20
51 #define S3C64XX_SPI_PENDING_CLR 0x24
52 #define S3C64XX_SPI_SWAP_CFG 0x28
53 #define S3C64XX_SPI_FB_CLK 0x2C
55 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
56 #define S3C64XX_SPI_CH_SW_RST (1<<5)
57 #define S3C64XX_SPI_CH_SLAVE (1<<4)
58 #define S3C64XX_SPI_CPOL_L (1<<3)
59 #define S3C64XX_SPI_CPHA_B (1<<2)
60 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
61 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
63 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
64 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
65 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
66 #define S3C64XX_SPI_PSR_MASK 0xff
68 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
69 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
70 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
71 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
73 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
74 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
75 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
76 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
77 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
78 #define S3C64XX_SPI_MODE_4BURST (1<<0)
80 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
81 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
83 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
84 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
85 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
86 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
87 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
88 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
89 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
91 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
92 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
93 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
94 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
95 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
96 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
98 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
100 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
101 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
102 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
103 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
104 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
106 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
107 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
108 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
109 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
110 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
111 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
112 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
113 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
115 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
117 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
119 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
120 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
121 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
124 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
125 #define S3C64XX_SPI_TRAILCNT_OFF 19
127 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
129 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
130 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
132 #define RXBUSY (1<<2)
133 #define TXBUSY (1<<3)
135 struct s3c64xx_spi_dma_data {
137 enum dma_transfer_direction direction;
142 * struct s3c64xx_spi_info - SPI Controller hardware info
143 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
144 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
145 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
146 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
147 * @clk_from_cmu: True, if the controller does not include a clock mux and
150 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
151 * differ in some aspects such as the size of the fifo and spi bus clock
152 * setup. Such differences are specified to the driver using this structure
153 * which is provided as driver data to the driver.
155 struct s3c64xx_spi_port_config {
156 int fifo_lvl_mask[MAX_SPI_PORTS];
165 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
166 * @clk: Pointer to the spi clock.
167 * @src_clk: Pointer to the clock used to generate SPI signals.
168 * @master: Pointer to the SPI Protocol master.
169 * @cntrlr_info: Platform specific data for the controller this driver manages.
170 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
171 * @lock: Controller specific lock.
172 * @state: Set of FLAGS to indicate status.
173 * @rx_dmach: Controller's DMA channel for Rx.
174 * @tx_dmach: Controller's DMA channel for Tx.
175 * @sfr_start: BUS address of SPI controller regs.
176 * @regs: Pointer to ioremap'ed controller registers.
178 * @xfer_completion: To indicate completion of xfer task.
179 * @cur_mode: Stores the active configuration of the controller.
180 * @cur_bpw: Stores the active bits per word settings.
181 * @cur_speed: Stores the active xfer clock speed.
183 struct s3c64xx_spi_driver_data {
187 struct platform_device *pdev;
188 struct spi_master *master;
189 struct s3c64xx_spi_info *cntrlr_info;
190 struct spi_device *tgl_spi;
192 unsigned long sfr_start;
193 struct completion xfer_completion;
195 unsigned cur_mode, cur_bpw;
197 struct s3c64xx_spi_dma_data rx_dma;
198 struct s3c64xx_spi_dma_data tx_dma;
199 struct s3c64xx_spi_port_config *port_conf;
200 unsigned int port_id;
204 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
206 void __iomem *regs = sdd->regs;
210 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
212 val = readl(regs + S3C64XX_SPI_CH_CFG);
213 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
214 writel(val, regs + S3C64XX_SPI_CH_CFG);
216 val = readl(regs + S3C64XX_SPI_CH_CFG);
217 val |= S3C64XX_SPI_CH_SW_RST;
218 val &= ~S3C64XX_SPI_CH_HS_EN;
219 writel(val, regs + S3C64XX_SPI_CH_CFG);
222 loops = msecs_to_loops(1);
224 val = readl(regs + S3C64XX_SPI_STATUS);
225 } while (TX_FIFO_LVL(val, sdd) && loops--);
228 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
231 loops = msecs_to_loops(1);
233 val = readl(regs + S3C64XX_SPI_STATUS);
234 if (RX_FIFO_LVL(val, sdd))
235 readl(regs + S3C64XX_SPI_RX_DATA);
241 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
243 val = readl(regs + S3C64XX_SPI_CH_CFG);
244 val &= ~S3C64XX_SPI_CH_SW_RST;
245 writel(val, regs + S3C64XX_SPI_CH_CFG);
247 val = readl(regs + S3C64XX_SPI_MODE_CFG);
248 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
249 writel(val, regs + S3C64XX_SPI_MODE_CFG);
252 static void s3c64xx_spi_dmacb(void *data)
254 struct s3c64xx_spi_driver_data *sdd;
255 struct s3c64xx_spi_dma_data *dma = data;
258 if (dma->direction == DMA_DEV_TO_MEM)
259 sdd = container_of(data,
260 struct s3c64xx_spi_driver_data, rx_dma);
262 sdd = container_of(data,
263 struct s3c64xx_spi_driver_data, tx_dma);
265 spin_lock_irqsave(&sdd->lock, flags);
267 if (dma->direction == DMA_DEV_TO_MEM) {
268 sdd->state &= ~RXBUSY;
269 if (!(sdd->state & TXBUSY))
270 complete(&sdd->xfer_completion);
272 sdd->state &= ~TXBUSY;
273 if (!(sdd->state & RXBUSY))
274 complete(&sdd->xfer_completion);
277 spin_unlock_irqrestore(&sdd->lock, flags);
280 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
281 struct sg_table *sgt)
283 struct s3c64xx_spi_driver_data *sdd;
284 struct dma_slave_config config;
285 struct dma_async_tx_descriptor *desc;
287 memset(&config, 0, sizeof(config));
289 if (dma->direction == DMA_DEV_TO_MEM) {
290 sdd = container_of((void *)dma,
291 struct s3c64xx_spi_driver_data, rx_dma);
292 config.direction = dma->direction;
293 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
294 config.src_addr_width = sdd->cur_bpw / 8;
295 config.src_maxburst = 1;
296 dmaengine_slave_config(dma->ch, &config);
298 sdd = container_of((void *)dma,
299 struct s3c64xx_spi_driver_data, tx_dma);
300 config.direction = dma->direction;
301 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
302 config.dst_addr_width = sdd->cur_bpw / 8;
303 config.dst_maxburst = 1;
304 dmaengine_slave_config(dma->ch, &config);
307 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
308 dma->direction, DMA_PREP_INTERRUPT);
310 desc->callback = s3c64xx_spi_dmacb;
311 desc->callback_param = dma;
313 dmaengine_submit(desc);
314 dma_async_issue_pending(dma->ch);
317 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
319 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
320 dma_filter_fn filter = sdd->cntrlr_info->filter;
321 struct device *dev = &sdd->pdev->dev;
325 if (!is_polling(sdd)) {
327 dma_cap_set(DMA_SLAVE, mask);
329 /* Acquire DMA channels */
330 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
331 (void *)sdd->rx_dma.dmach, dev, "rx");
332 if (!sdd->rx_dma.ch) {
333 dev_err(dev, "Failed to get RX DMA channel\n");
337 spi->dma_rx = sdd->rx_dma.ch;
339 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
340 (void *)sdd->tx_dma.dmach, dev, "tx");
341 if (!sdd->tx_dma.ch) {
342 dev_err(dev, "Failed to get TX DMA channel\n");
346 spi->dma_tx = sdd->tx_dma.ch;
349 ret = pm_runtime_get_sync(&sdd->pdev->dev);
351 dev_err(dev, "Failed to enable device: %d\n", ret);
358 dma_release_channel(sdd->tx_dma.ch);
360 dma_release_channel(sdd->rx_dma.ch);
365 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
367 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
369 /* Free DMA channels */
370 if (!is_polling(sdd)) {
371 dma_release_channel(sdd->rx_dma.ch);
372 dma_release_channel(sdd->tx_dma.ch);
375 pm_runtime_put(&sdd->pdev->dev);
379 static bool s3c64xx_spi_can_dma(struct spi_master *master,
380 struct spi_device *spi,
381 struct spi_transfer *xfer)
383 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
385 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
388 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
389 struct spi_device *spi,
390 struct spi_transfer *xfer, int dma_mode)
392 void __iomem *regs = sdd->regs;
395 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
396 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
398 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
399 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
402 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
404 /* Always shift in data in FIFO, even if xfer is Tx only,
405 * this helps setting PCKT_CNT value for generating clocks
408 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
409 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
410 | S3C64XX_SPI_PACKET_CNT_EN,
411 regs + S3C64XX_SPI_PACKET_CNT);
414 if (xfer->tx_buf != NULL) {
415 sdd->state |= TXBUSY;
416 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
418 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
419 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
421 switch (sdd->cur_bpw) {
423 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
424 xfer->tx_buf, xfer->len / 4);
427 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
428 xfer->tx_buf, xfer->len / 2);
431 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
432 xfer->tx_buf, xfer->len);
438 if (xfer->rx_buf != NULL) {
439 sdd->state |= RXBUSY;
441 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
442 && !(sdd->cur_mode & SPI_CPHA))
443 chcfg |= S3C64XX_SPI_CH_HS_EN;
446 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
447 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
448 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
449 | S3C64XX_SPI_PACKET_CNT_EN,
450 regs + S3C64XX_SPI_PACKET_CNT);
451 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
455 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
456 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
459 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
462 void __iomem *regs = sdd->regs;
463 unsigned long val = 1;
466 /* max fifo depth available */
467 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
470 val = msecs_to_loops(timeout_ms);
473 status = readl(regs + S3C64XX_SPI_STATUS);
474 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
476 /* return the actual received data length */
477 return RX_FIFO_LVL(status, sdd);
480 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
481 struct spi_transfer *xfer)
483 void __iomem *regs = sdd->regs;
488 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
489 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
490 ms += 10; /* some tolerance */
492 val = msecs_to_jiffies(ms) + 10;
493 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
496 * If the previous xfer was completed within timeout, then
497 * proceed further else return -EIO.
498 * DmaTx returns after simply writing data in the FIFO,
499 * w/o waiting for real transmission on the bus to finish.
500 * DmaRx returns only after Dma read data from FIFO which
501 * needs bus transmission to finish, so we don't worry if
502 * Xfer involved Rx(with or without Tx).
504 if (val && !xfer->rx_buf) {
505 val = msecs_to_loops(10);
506 status = readl(regs + S3C64XX_SPI_STATUS);
507 while ((TX_FIFO_LVL(status, sdd)
508 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
511 status = readl(regs + S3C64XX_SPI_STATUS);
516 /* If timed out while checking rx/tx status return error */
523 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
524 struct spi_transfer *xfer)
526 void __iomem *regs = sdd->regs;
534 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
535 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
536 ms += 10; /* some tolerance */
538 val = msecs_to_loops(ms);
540 status = readl(regs + S3C64XX_SPI_STATUS);
541 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
544 /* If it was only Tx */
546 sdd->state &= ~TXBUSY;
551 * If the receive length is bigger than the controller fifo
552 * size, calculate the loops and read the fifo as many times.
553 * loops = length / max fifo size (calculated by using the
555 * For any size less than the fifo size the below code is
556 * executed atleast once.
558 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
561 /* wait for data to be received in the fifo */
562 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
565 switch (sdd->cur_bpw) {
567 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
571 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
575 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
582 sdd->state &= ~RXBUSY;
587 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
589 void __iomem *regs = sdd->regs;
593 if (sdd->port_conf->clk_from_cmu) {
594 clk_disable_unprepare(sdd->src_clk);
596 val = readl(regs + S3C64XX_SPI_CLK_CFG);
597 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
598 writel(val, regs + S3C64XX_SPI_CLK_CFG);
601 /* Set Polarity and Phase */
602 val = readl(regs + S3C64XX_SPI_CH_CFG);
603 val &= ~(S3C64XX_SPI_CH_SLAVE |
607 if (sdd->cur_mode & SPI_CPOL)
608 val |= S3C64XX_SPI_CPOL_L;
610 if (sdd->cur_mode & SPI_CPHA)
611 val |= S3C64XX_SPI_CPHA_B;
613 writel(val, regs + S3C64XX_SPI_CH_CFG);
615 /* Set Channel & DMA Mode */
616 val = readl(regs + S3C64XX_SPI_MODE_CFG);
617 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
618 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
620 switch (sdd->cur_bpw) {
622 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
623 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
626 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
627 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
630 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
631 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
635 writel(val, regs + S3C64XX_SPI_MODE_CFG);
637 if (sdd->port_conf->clk_from_cmu) {
638 /* Configure Clock */
639 /* There is half-multiplier before the SPI */
640 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
642 clk_prepare_enable(sdd->src_clk);
644 /* Configure Clock */
645 val = readl(regs + S3C64XX_SPI_CLK_CFG);
646 val &= ~S3C64XX_SPI_PSR_MASK;
647 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
648 & S3C64XX_SPI_PSR_MASK);
649 writel(val, regs + S3C64XX_SPI_CLK_CFG);
652 val = readl(regs + S3C64XX_SPI_CLK_CFG);
653 val |= S3C64XX_SPI_ENCLK_ENABLE;
654 writel(val, regs + S3C64XX_SPI_CLK_CFG);
658 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
660 static int s3c64xx_spi_prepare_message(struct spi_master *master,
661 struct spi_message *msg)
663 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
664 struct spi_device *spi = msg->spi;
665 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
667 /* If Master's(controller) state differs from that needed by Slave */
668 if (sdd->cur_speed != spi->max_speed_hz
669 || sdd->cur_mode != spi->mode
670 || sdd->cur_bpw != spi->bits_per_word) {
671 sdd->cur_bpw = spi->bits_per_word;
672 sdd->cur_speed = spi->max_speed_hz;
673 sdd->cur_mode = spi->mode;
674 s3c64xx_spi_config(sdd);
677 /* Configure feedback delay */
678 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
683 static int s3c64xx_spi_transfer_one(struct spi_master *master,
684 struct spi_device *spi,
685 struct spi_transfer *xfer)
687 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
694 reinit_completion(&sdd->xfer_completion);
696 /* Only BPW and Speed may change across transfers */
697 bpw = xfer->bits_per_word;
698 speed = xfer->speed_hz ? : spi->max_speed_hz;
700 if (xfer->len % (bpw / 8)) {
702 "Xfer length(%u) not a multiple of word size(%u)\n",
707 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
709 sdd->cur_speed = speed;
710 s3c64xx_spi_config(sdd);
713 /* Polling method for xfers not bigger than FIFO capacity */
715 if (!is_polling(sdd) &&
716 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
717 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
720 spin_lock_irqsave(&sdd->lock, flags);
722 /* Pending only which is to be done */
723 sdd->state &= ~RXBUSY;
724 sdd->state &= ~TXBUSY;
726 enable_datapath(sdd, spi, xfer, use_dma);
728 /* Start the signals */
729 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
731 spin_unlock_irqrestore(&sdd->lock, flags);
734 status = wait_for_dma(sdd, xfer);
736 status = wait_for_pio(sdd, xfer);
739 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
740 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
741 (sdd->state & RXBUSY) ? 'f' : 'p',
742 (sdd->state & TXBUSY) ? 'f' : 'p',
746 if (xfer->tx_buf != NULL
747 && (sdd->state & TXBUSY))
748 dmaengine_terminate_all(sdd->tx_dma.ch);
749 if (xfer->rx_buf != NULL
750 && (sdd->state & RXBUSY))
751 dmaengine_terminate_all(sdd->rx_dma.ch);
760 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
761 struct spi_device *spi)
763 struct s3c64xx_spi_csinfo *cs;
764 struct device_node *slave_np, *data_np = NULL;
765 struct s3c64xx_spi_driver_data *sdd;
768 sdd = spi_master_get_devdata(spi->master);
769 slave_np = spi->dev.of_node;
771 dev_err(&spi->dev, "device node not found\n");
772 return ERR_PTR(-EINVAL);
775 data_np = of_get_child_by_name(slave_np, "controller-data");
777 dev_err(&spi->dev, "child node 'controller-data' not found\n");
778 return ERR_PTR(-EINVAL);
781 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
783 dev_err(&spi->dev, "could not allocate memory for controller data\n");
784 of_node_put(data_np);
785 return ERR_PTR(-ENOMEM);
788 /* The CS line is asserted/deasserted by the gpio pin */
790 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
792 if (!gpio_is_valid(cs->line)) {
793 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
795 of_node_put(data_np);
796 return ERR_PTR(-EINVAL);
799 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
800 cs->fb_delay = fb_delay;
801 of_node_put(data_np);
806 * Here we only check the validity of requested configuration
807 * and save the configuration in a local data-structure.
808 * The controller is actually configured only just before we
809 * get a message to transfer.
811 static int s3c64xx_spi_setup(struct spi_device *spi)
813 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
814 struct s3c64xx_spi_driver_data *sdd;
815 struct s3c64xx_spi_info *sci;
818 sdd = spi_master_get_devdata(spi->master);
819 if (!cs && spi->dev.of_node) {
820 cs = s3c64xx_get_slave_ctrldata(spi);
821 spi->controller_data = cs;
824 if (IS_ERR_OR_NULL(cs)) {
825 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
829 if (!spi_get_ctldata(spi)) {
830 /* Request gpio only if cs line is asserted by gpio pins */
832 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
833 dev_name(&spi->dev));
836 "Failed to get /CS gpio [%d]: %d\n",
841 spi->cs_gpio = cs->line;
844 spi_set_ctldata(spi, cs);
847 sci = sdd->cntrlr_info;
849 pm_runtime_get_sync(&sdd->pdev->dev);
851 /* Check if we can provide the requested rate */
852 if (!sdd->port_conf->clk_from_cmu) {
856 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
858 if (spi->max_speed_hz > speed)
859 spi->max_speed_hz = speed;
861 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
862 psr &= S3C64XX_SPI_PSR_MASK;
863 if (psr == S3C64XX_SPI_PSR_MASK)
866 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
867 if (spi->max_speed_hz < speed) {
868 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
876 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
877 if (spi->max_speed_hz >= speed) {
878 spi->max_speed_hz = speed;
880 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
887 pm_runtime_put(&sdd->pdev->dev);
888 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
892 pm_runtime_put(&sdd->pdev->dev);
893 /* setup() returns with device de-selected */
894 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
897 spi_set_ctldata(spi, NULL);
900 if (spi->dev.of_node)
906 static void s3c64xx_spi_cleanup(struct spi_device *spi)
908 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
909 struct s3c64xx_spi_driver_data *sdd;
911 sdd = spi_master_get_devdata(spi->master);
913 gpio_free(spi->cs_gpio);
914 if (spi->dev.of_node)
917 spi_set_ctldata(spi, NULL);
920 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
922 struct s3c64xx_spi_driver_data *sdd = data;
923 struct spi_master *spi = sdd->master;
924 unsigned int val, clr = 0;
926 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
928 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
929 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
930 dev_err(&spi->dev, "RX overrun\n");
932 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
933 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
934 dev_err(&spi->dev, "RX underrun\n");
936 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
937 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
938 dev_err(&spi->dev, "TX overrun\n");
940 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
941 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
942 dev_err(&spi->dev, "TX underrun\n");
945 /* Clear the pending irq by setting and then clearing it */
946 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
947 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
952 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
954 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
955 void __iomem *regs = sdd->regs;
960 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
962 /* Disable Interrupts - we use Polling if not DMA mode */
963 writel(0, regs + S3C64XX_SPI_INT_EN);
965 if (!sdd->port_conf->clk_from_cmu)
966 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
967 regs + S3C64XX_SPI_CLK_CFG);
968 writel(0, regs + S3C64XX_SPI_MODE_CFG);
969 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
971 /* Clear any irq pending bits, should set and clear the bits */
972 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
973 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
974 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
975 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
976 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
977 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
979 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
981 val = readl(regs + S3C64XX_SPI_MODE_CFG);
982 val &= ~S3C64XX_SPI_MODE_4BURST;
983 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
984 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
985 writel(val, regs + S3C64XX_SPI_MODE_CFG);
991 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
993 struct s3c64xx_spi_info *sci;
996 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
998 dev_err(dev, "memory allocation for spi_info failed\n");
999 return ERR_PTR(-ENOMEM);
1002 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1003 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1004 sci->src_clk_nr = 0;
1006 sci->src_clk_nr = temp;
1009 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1010 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1019 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1021 return dev_get_platdata(dev);
1025 static const struct of_device_id s3c64xx_spi_dt_match[];
1027 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1028 struct platform_device *pdev)
1031 if (pdev->dev.of_node) {
1032 const struct of_device_id *match;
1033 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1034 return (struct s3c64xx_spi_port_config *)match->data;
1037 return (struct s3c64xx_spi_port_config *)
1038 platform_get_device_id(pdev)->driver_data;
1041 static int s3c64xx_spi_probe(struct platform_device *pdev)
1043 struct resource *mem_res;
1044 struct resource *res;
1045 struct s3c64xx_spi_driver_data *sdd;
1046 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1047 struct spi_master *master;
1051 if (!sci && pdev->dev.of_node) {
1052 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1054 return PTR_ERR(sci);
1058 dev_err(&pdev->dev, "platform_data missing!\n");
1062 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1063 if (mem_res == NULL) {
1064 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1068 irq = platform_get_irq(pdev, 0);
1070 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1074 master = spi_alloc_master(&pdev->dev,
1075 sizeof(struct s3c64xx_spi_driver_data));
1076 if (master == NULL) {
1077 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1081 platform_set_drvdata(pdev, master);
1083 sdd = spi_master_get_devdata(master);
1084 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1085 sdd->master = master;
1086 sdd->cntrlr_info = sci;
1088 sdd->sfr_start = mem_res->start;
1089 sdd->cs_gpio = true;
1090 if (pdev->dev.of_node) {
1091 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1092 sdd->cs_gpio = false;
1094 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1096 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1102 sdd->port_id = pdev->id;
1107 if (!sdd->pdev->dev.of_node) {
1108 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1110 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1111 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1113 sdd->tx_dma.dmach = res->start;
1115 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1117 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1118 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1120 sdd->rx_dma.dmach = res->start;
1123 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1124 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1126 master->dev.of_node = pdev->dev.of_node;
1127 master->bus_num = sdd->port_id;
1128 master->setup = s3c64xx_spi_setup;
1129 master->cleanup = s3c64xx_spi_cleanup;
1130 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1131 master->prepare_message = s3c64xx_spi_prepare_message;
1132 master->transfer_one = s3c64xx_spi_transfer_one;
1133 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1134 master->num_chipselect = sci->num_cs;
1135 master->dma_alignment = 8;
1136 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1138 /* the spi->mode bits understood by this driver: */
1139 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1140 master->auto_runtime_pm = true;
1141 if (!is_polling(sdd))
1142 master->can_dma = s3c64xx_spi_can_dma;
1144 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1145 if (IS_ERR(sdd->regs)) {
1146 ret = PTR_ERR(sdd->regs);
1150 if (sci->cfg_gpio && sci->cfg_gpio()) {
1151 dev_err(&pdev->dev, "Unable to config gpio\n");
1157 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1158 if (IS_ERR(sdd->clk)) {
1159 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1160 ret = PTR_ERR(sdd->clk);
1164 if (clk_prepare_enable(sdd->clk)) {
1165 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1170 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1171 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1172 if (IS_ERR(sdd->src_clk)) {
1174 "Unable to acquire clock '%s'\n", clk_name);
1175 ret = PTR_ERR(sdd->src_clk);
1179 if (clk_prepare_enable(sdd->src_clk)) {
1180 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1185 /* Setup Deufult Mode */
1186 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1188 spin_lock_init(&sdd->lock);
1189 init_completion(&sdd->xfer_completion);
1191 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1192 "spi-s3c64xx", sdd);
1194 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1199 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1200 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1201 sdd->regs + S3C64XX_SPI_INT_EN);
1203 pm_runtime_set_active(&pdev->dev);
1204 pm_runtime_enable(&pdev->dev);
1206 ret = devm_spi_register_master(&pdev->dev, master);
1208 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1212 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1213 sdd->port_id, master->num_chipselect);
1214 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1216 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1221 clk_disable_unprepare(sdd->src_clk);
1223 clk_disable_unprepare(sdd->clk);
1225 spi_master_put(master);
1230 static int s3c64xx_spi_remove(struct platform_device *pdev)
1232 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1233 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1235 pm_runtime_disable(&pdev->dev);
1237 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1239 clk_disable_unprepare(sdd->src_clk);
1241 clk_disable_unprepare(sdd->clk);
1246 #ifdef CONFIG_PM_SLEEP
1247 static int s3c64xx_spi_suspend(struct device *dev)
1249 struct spi_master *master = dev_get_drvdata(dev);
1250 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1252 int ret = spi_master_suspend(master);
1256 if (!pm_runtime_suspended(dev)) {
1257 clk_disable_unprepare(sdd->clk);
1258 clk_disable_unprepare(sdd->src_clk);
1261 sdd->cur_speed = 0; /* Output Clock is stopped */
1266 static int s3c64xx_spi_resume(struct device *dev)
1268 struct spi_master *master = dev_get_drvdata(dev);
1269 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1270 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1275 if (!pm_runtime_suspended(dev)) {
1276 clk_prepare_enable(sdd->src_clk);
1277 clk_prepare_enable(sdd->clk);
1280 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1282 return spi_master_resume(master);
1284 #endif /* CONFIG_PM_SLEEP */
1286 #ifdef CONFIG_PM_RUNTIME
1287 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1289 struct spi_master *master = dev_get_drvdata(dev);
1290 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1292 clk_disable_unprepare(sdd->clk);
1293 clk_disable_unprepare(sdd->src_clk);
1298 static int s3c64xx_spi_runtime_resume(struct device *dev)
1300 struct spi_master *master = dev_get_drvdata(dev);
1301 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1304 ret = clk_prepare_enable(sdd->src_clk);
1308 ret = clk_prepare_enable(sdd->clk);
1310 clk_disable_unprepare(sdd->src_clk);
1316 #endif /* CONFIG_PM_RUNTIME */
1318 static const struct dev_pm_ops s3c64xx_spi_pm = {
1319 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1320 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1321 s3c64xx_spi_runtime_resume, NULL)
1324 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1325 .fifo_lvl_mask = { 0x7f },
1326 .rx_lvl_offset = 13,
1331 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1332 .fifo_lvl_mask = { 0x7f, 0x7F },
1333 .rx_lvl_offset = 13,
1337 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1338 .fifo_lvl_mask = { 0x1ff, 0x7F },
1339 .rx_lvl_offset = 15,
1343 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1344 .fifo_lvl_mask = { 0x7f, 0x7F },
1345 .rx_lvl_offset = 13,
1350 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1351 .fifo_lvl_mask = { 0x1ff, 0x7F },
1352 .rx_lvl_offset = 15,
1357 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1358 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1359 .rx_lvl_offset = 15,
1362 .clk_from_cmu = true,
1365 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1366 .fifo_lvl_mask = { 0x1ff },
1367 .rx_lvl_offset = 15,
1370 .clk_from_cmu = true,
1371 .quirks = S3C64XX_SPI_QUIRK_POLL,
1374 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1376 .name = "s3c2443-spi",
1377 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1379 .name = "s3c6410-spi",
1380 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1382 .name = "s5p64x0-spi",
1383 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1385 .name = "s5pc100-spi",
1386 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1388 .name = "s5pv210-spi",
1389 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1391 .name = "exynos4210-spi",
1392 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1397 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1398 { .compatible = "samsung,s3c2443-spi",
1399 .data = (void *)&s3c2443_spi_port_config,
1401 { .compatible = "samsung,s3c6410-spi",
1402 .data = (void *)&s3c6410_spi_port_config,
1404 { .compatible = "samsung,s5pc100-spi",
1405 .data = (void *)&s5pc100_spi_port_config,
1407 { .compatible = "samsung,s5pv210-spi",
1408 .data = (void *)&s5pv210_spi_port_config,
1410 { .compatible = "samsung,exynos4210-spi",
1411 .data = (void *)&exynos4_spi_port_config,
1413 { .compatible = "samsung,exynos5440-spi",
1414 .data = (void *)&exynos5440_spi_port_config,
1418 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1420 static struct platform_driver s3c64xx_spi_driver = {
1422 .name = "s3c64xx-spi",
1423 .owner = THIS_MODULE,
1424 .pm = &s3c64xx_spi_pm,
1425 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1427 .probe = s3c64xx_spi_probe,
1428 .remove = s3c64xx_spi_remove,
1429 .id_table = s3c64xx_spi_driver_ids,
1431 MODULE_ALIAS("platform:s3c64xx-spi");
1433 module_platform_driver(s3c64xx_spi_driver);
1435 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1436 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1437 MODULE_LICENSE("GPL");