drivers/spi/spi-tegra114.c

   1 /*
   2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/clk/tegra.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmapool.h>
  26 #include <linux/err.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kernel.h>
  31 #include <linux/kthread.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/spi/spi.h>
  38
  39 #define SPI_COMMAND1                            0x000
  40 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
  41 #define SPI_PACKED                              (1 << 5)
  42 #define SPI_TX_EN                               (1 << 11)
  43 #define SPI_RX_EN                               (1 << 12)
  44 #define SPI_BOTH_EN_BYTE                        (1 << 13)
  45 #define SPI_BOTH_EN_BIT                         (1 << 14)
  46 #define SPI_LSBYTE_FE                           (1 << 15)
  47 #define SPI_LSBIT_FE                            (1 << 16)
  48 #define SPI_BIDIROE                             (1 << 17)
  49 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
  50 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
  51 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
  52 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
  53 #define SPI_IDLE_SDA_MASK                       (3 << 18)
  54 #define SPI_CS_SS_VAL                           (1 << 20)
  55 #define SPI_CS_SW_HW                            (1 << 21)
  56 /* SPI_CS_POL_INACTIVE bits are default high */
  57 #define SPI_CS_POL_INACTIVE                     22
  58 #define SPI_CS_POL_INACTIVE_0                   (1 << 22)
  59 #define SPI_CS_POL_INACTIVE_1                   (1 << 23)
  60 #define SPI_CS_POL_INACTIVE_2                   (1 << 24)
  61 #define SPI_CS_POL_INACTIVE_3                   (1 << 25)
  62 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
  63
  64 #define SPI_CS_SEL_0                            (0 << 26)
  65 #define SPI_CS_SEL_1                            (1 << 26)
  66 #define SPI_CS_SEL_2                            (2 << 26)
  67 #define SPI_CS_SEL_3                            (3 << 26)
  68 #define SPI_CS_SEL_MASK                         (3 << 26)
  69 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
  70 #define SPI_CONTROL_MODE_0                      (0 << 28)
  71 #define SPI_CONTROL_MODE_1                      (1 << 28)
  72 #define SPI_CONTROL_MODE_2                      (2 << 28)
  73 #define SPI_CONTROL_MODE_3                      (3 << 28)
  74 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
  75 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
  76 #define SPI_M_S                                 (1 << 30)
  77 #define SPI_PIO                                 (1 << 31)
  78
  79 #define SPI_COMMAND2                            0x004
  80 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
  81 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
  82
  83 #define SPI_CS_TIMING1                          0x008
  84 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
  85 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
  86                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
  87                 ((reg) & ~(0xFFu << ((cs) * 8))))
  88
  89 #define SPI_CS_TIMING2                          0x00C
  90 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
  91 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
  92 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
  93 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
  94 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
  95 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
  96 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
  97 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
  98 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
  99                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
 100                         ((reg) & ~(1 << ((cs) * 8 + 5))))
 101 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
 102                 (reg = (((val) & 0xF) << ((cs) * 8)) |          \
 103                         ((reg) & ~(0xF << ((cs) * 8))))
 104
 105 #define SPI_TRANS_STATUS                        0x010
 106 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
 107 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
 108 #define SPI_RDY                                 (1 << 30)
 109
 110 #define SPI_FIFO_STATUS                         0x014
 111 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
 112 #define SPI_RX_FIFO_FULL                        (1 << 1)
 113 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
 114 #define SPI_TX_FIFO_FULL                        (1 << 3)
 115 #define SPI_RX_FIFO_UNF                         (1 << 4)
 116 #define SPI_RX_FIFO_OVF                         (1 << 5)
 117 #define SPI_TX_FIFO_UNF                         (1 << 6)
 118 #define SPI_TX_FIFO_OVF                         (1 << 7)
 119 #define SPI_ERR                                 (1 << 8)
 120 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
 121 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
 122 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
 123 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
 124 #define SPI_FRAME_END                           (1 << 30)
 125 #define SPI_CS_INACTIVE                         (1 << 31)
 126
 127 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
 128                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 129 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 130
 131 #define SPI_TX_DATA                             0x018
 132 #define SPI_RX_DATA                             0x01C
 133
 134 #define SPI_DMA_CTL                             0x020
 135 #define SPI_TX_TRIG_1                           (0 << 15)
 136 #define SPI_TX_TRIG_4                           (1 << 15)
 137 #define SPI_TX_TRIG_8                           (2 << 15)
 138 #define SPI_TX_TRIG_16                          (3 << 15)
 139 #define SPI_TX_TRIG_MASK                        (3 << 15)
 140 #define SPI_RX_TRIG_1                           (0 << 19)
 141 #define SPI_RX_TRIG_4                           (1 << 19)
 142 #define SPI_RX_TRIG_8                           (2 << 19)
 143 #define SPI_RX_TRIG_16                          (3 << 19)
 144 #define SPI_RX_TRIG_MASK                        (3 << 19)
 145 #define SPI_IE_TX                               (1 << 28)
 146 #define SPI_IE_RX                               (1 << 29)
 147 #define SPI_CONT                                (1 << 30)
 148 #define SPI_DMA                                 (1 << 31)
 149 #define SPI_DMA_EN                              SPI_DMA
 150
 151 #define SPI_DMA_BLK                             0x024
 152 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
 153
 154 #define SPI_TX_FIFO                             0x108
 155 #define SPI_RX_FIFO                             0x188
 156 #define MAX_CHIP_SELECT                         4
 157 #define SPI_FIFO_DEPTH                          64
 158 #define DATA_DIR_TX                             (1 << 0)
 159 #define DATA_DIR_RX                             (1 << 1)
 160
 161 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(1000))
 162 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
 163 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
 164 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
 165 #define MAX_HOLD_CYCLES                         16
 166 #define SPI_DEFAULT_SPEED                       25000000
 167
 168 #define MAX_CHIP_SELECT                         4
 169 #define SPI_FIFO_DEPTH                          64
 170
 171 struct tegra_spi_data {
 172         struct device                           *dev;
 173         struct spi_master                       *master;
 174         spinlock_t                              lock;
 175
 176         struct clk                              *clk;
 177         void __iomem                            *base;
 178         phys_addr_t                             phys;
 179         unsigned                                irq;
 180         int                                     dma_req_sel;
 181         u32                                     spi_max_frequency;
 182         u32                                     cur_speed;
 183
 184         struct spi_device                       *cur_spi;
 185         struct spi_device                       *cs_control;
 186         unsigned                                cur_pos;
 187         unsigned                                cur_len;
 188         unsigned                                words_per_32bit;
 189         unsigned                                bytes_per_word;
 190         unsigned                                curr_dma_words;
 191         unsigned                                cur_direction;
 192
 193         unsigned                                cur_rx_pos;
 194         unsigned                                cur_tx_pos;
 195
 196         unsigned                                dma_buf_size;
 197         unsigned                                max_buf_size;
 198         bool                                    is_curr_dma_xfer;
 199
 200         struct completion                       rx_dma_complete;
 201         struct completion                       tx_dma_complete;
 202
 203         u32                                     tx_status;
 204         u32                                     rx_status;
 205         u32                                     status_reg;
 206         bool                                    is_packed;
 207         unsigned long                           packed_size;
 208
 209         u32                                     command1_reg;
 210         u32                                     dma_control_reg;
 211         u32                                     def_command1_reg;
 212         u32                                     spi_cs_timing;
 213
 214         struct completion                       xfer_completion;
 215         struct spi_transfer                     *curr_xfer;
 216         struct dma_chan                         *rx_dma_chan;
 217         u32                                     *rx_dma_buf;
 218         dma_addr_t                              rx_dma_phys;
 219         struct dma_async_tx_descriptor          *rx_dma_desc;
 220
 221         struct dma_chan                         *tx_dma_chan;
 222         u32                                     *tx_dma_buf;
 223         dma_addr_t                              tx_dma_phys;
 224         struct dma_async_tx_descriptor          *tx_dma_desc;
 225 };
 226
 227 static int tegra_spi_runtime_suspend(struct device *dev);
 228 static int tegra_spi_runtime_resume(struct device *dev);
 229
 230 static inline unsigned long tegra_spi_readl(struct tegra_spi_data *tspi,
 231                 unsigned long reg)
 232 {
 233         return readl(tspi->base + reg);
 234 }
 235
 236 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 237                 unsigned long val, unsigned long reg)
 238 {
 239         writel(val, tspi->base + reg);
 240
 241         /* Read back register to make sure that register writes completed */
 242         if (reg != SPI_TX_FIFO)
 243                 readl(tspi->base + SPI_COMMAND1);
 244 }
 245
 246 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 247 {
 248         unsigned long val;
 249
 250         /* Write 1 to clear status register */
 251         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 252         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 253
 254         /* Clear fifo status error if any */
 255         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 256         if (val & SPI_ERR)
 257                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 258                                 SPI_FIFO_STATUS);
 259 }
 260
 261 static unsigned tegra_spi_calculate_curr_xfer_param(
 262         struct spi_device *spi, struct tegra_spi_data *tspi,
 263         struct spi_transfer *t)
 264 {
 265         unsigned remain_len = t->len - tspi->cur_pos;
 266         unsigned max_word;
 267         unsigned bits_per_word = t->bits_per_word;
 268         unsigned max_len;
 269         unsigned total_fifo_words;
 270
 271         tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
 272
 273         if (bits_per_word == 8 || bits_per_word == 16) {
 274                 tspi->is_packed = 1;
 275                 tspi->words_per_32bit = 32/bits_per_word;
 276         } else {
 277                 tspi->is_packed = 0;
 278                 tspi->words_per_32bit = 1;
 279         }
 280
 281         if (tspi->is_packed) {
 282                 max_len = min(remain_len, tspi->max_buf_size);
 283                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 284                 total_fifo_words = (max_len + 3) / 4;
 285         } else {
 286                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 287                 max_word = min(max_word, tspi->max_buf_size/4);
 288                 tspi->curr_dma_words = max_word;
 289                 total_fifo_words = max_word;
 290         }
 291         return total_fifo_words;
 292 }
 293
 294 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 295         struct tegra_spi_data *tspi, struct spi_transfer *t)
 296 {
 297         unsigned nbytes;
 298         unsigned tx_empty_count;
 299         unsigned long fifo_status;
 300         unsigned max_n_32bit;
 301         unsigned i, count;
 302         unsigned long x;
 303         unsigned int written_words;
 304         unsigned fifo_words_left;
 305         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 306
 307         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 308         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
 309
 310         if (tspi->is_packed) {
 311                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 312                 written_words = min(fifo_words_left, tspi->curr_dma_words);
 313                 nbytes = written_words * tspi->bytes_per_word;
 314                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 315                 for (count = 0; count < max_n_32bit; count++) {
 316                         x = 0;
 317                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 318                                 x |= (*tx_buf++) << (i*8);
 319                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 320                 }
 321         } else {
 322                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 323                 written_words = max_n_32bit;
 324                 nbytes = written_words * tspi->bytes_per_word;
 325                 for (count = 0; count < max_n_32bit; count++) {
 326                         x = 0;
 327                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
 328                                                         i++, nbytes--)
 329                                 x |= ((*tx_buf++) << i*8);
 330                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 331                 }
 332         }
 333         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 334         return written_words;
 335 }
 336
 337 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 338                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 339 {
 340         unsigned rx_full_count;
 341         unsigned long fifo_status;
 342         unsigned i, count;
 343         unsigned long x;
 344         unsigned int read_words = 0;
 345         unsigned len;
 346         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 347
 348         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 349         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 350         if (tspi->is_packed) {
 351                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 352                 for (count = 0; count < rx_full_count; count++) {
 353                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 354                         for (i = 0; len && (i < 4); i++, len--)
 355                                 *rx_buf++ = (x >> i*8) & 0xFF;
 356                 }
 357                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 358                 read_words += tspi->curr_dma_words;
 359         } else {
 360                 unsigned int rx_mask;
 361                 unsigned int bits_per_word = t->bits_per_word;
 362
 363                 rx_mask = (1 << bits_per_word) - 1;
 364                 for (count = 0; count < rx_full_count; count++) {
 365                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 366                         x &= rx_mask;
 367                         for (i = 0; (i < tspi->bytes_per_word); i++)
 368                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 369                 }
 370                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
 371                 read_words += rx_full_count;
 372         }
 373         return read_words;
 374 }
 375
 376 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 377                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 378 {
 379         unsigned len;
 380
 381         /* Make the dma buffer to read by cpu */
 382         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 383                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 384
 385         if (tspi->is_packed) {
 386                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 387                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 388         } else {
 389                 unsigned int i;
 390                 unsigned int count;
 391                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 392                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 393                 unsigned int x;
 394
 395                 for (count = 0; count < tspi->curr_dma_words; count++) {
 396                         x = 0;
 397                         for (i = 0; consume && (i < tspi->bytes_per_word);
 398                                                         i++, consume--)
 399                                 x |= ((*tx_buf++) << i * 8);
 400                         tspi->tx_dma_buf[count] = x;
 401                 }
 402         }
 403         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 404
 405         /* Make the dma buffer to read by dma */
 406         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 407                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 408 }
 409
 410 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 411                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 412 {
 413         unsigned len;
 414
 415         /* Make the dma buffer to read by cpu */
 416         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 417                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 418
 419         if (tspi->is_packed) {
 420                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 421                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 422         } else {
 423                 unsigned int i;
 424                 unsigned int count;
 425                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 426                 unsigned int x;
 427                 unsigned int rx_mask;
 428                 unsigned int bits_per_word = t->bits_per_word;
 429
 430                 rx_mask = (1 << bits_per_word) - 1;
 431                 for (count = 0; count < tspi->curr_dma_words; count++) {
 432                         x = tspi->rx_dma_buf[count];
 433                         x &= rx_mask;
 434                         for (i = 0; (i < tspi->bytes_per_word); i++)
 435                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 436                 }
 437         }
 438         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 439
 440         /* Make the dma buffer to read by dma */
 441         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 442                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 443 }
 444
 445 static void tegra_spi_dma_complete(void *args)
 446 {
 447         struct completion *dma_complete = args;
 448
 449         complete(dma_complete);
 450 }
 451
 452 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 453 {
 454         INIT_COMPLETION(tspi->tx_dma_complete);
 455         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 456                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 457                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 458         if (!tspi->tx_dma_desc) {
 459                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
 460                 return -EIO;
 461         }
 462
 463         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 464         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 465
 466         dmaengine_submit(tspi->tx_dma_desc);
 467         dma_async_issue_pending(tspi->tx_dma_chan);
 468         return 0;
 469 }
 470
 471 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 472 {
 473         INIT_COMPLETION(tspi->rx_dma_complete);
 474         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 475                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 476                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 477         if (!tspi->rx_dma_desc) {
 478                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
 479                 return -EIO;
 480         }
 481
 482         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 483         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 484
 485         dmaengine_submit(tspi->rx_dma_desc);
 486         dma_async_issue_pending(tspi->rx_dma_chan);
 487         return 0;
 488 }
 489
 490 static int tegra_spi_start_dma_based_transfer(
 491                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 492 {
 493         unsigned long val;
 494         unsigned int len;
 495         int ret = 0;
 496         unsigned long status;
 497
 498         /* Make sure that Rx and Tx fifo are empty */
 499         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 500         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 501                 dev_err(tspi->dev,
 502                         "Rx/Tx fifo are not empty status 0x%08lx\n", status);
 503                 return -EIO;
 504         }
 505
 506         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 507         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 508
 509         if (tspi->is_packed)
 510                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 511                                         4) * 4;
 512         else
 513                 len = tspi->curr_dma_words * 4;
 514
 515         /* Set attention level based on length of transfer */
 516         if (len & 0xF)
 517                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 518         else if (((len) >> 4) & 0x1)
 519                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 520         else
 521                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 522
 523         if (tspi->cur_direction & DATA_DIR_TX)
 524                 val |= SPI_IE_TX;
 525
 526         if (tspi->cur_direction & DATA_DIR_RX)
 527                 val |= SPI_IE_RX;
 528
 529         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 530         tspi->dma_control_reg = val;
 531
 532         if (tspi->cur_direction & DATA_DIR_TX) {
 533                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 534                 ret = tegra_spi_start_tx_dma(tspi, len);
 535                 if (ret < 0) {
 536                         dev_err(tspi->dev,
 537                                 "Starting tx dma failed, err %d\n", ret);
 538                         return ret;
 539                 }
 540         }
 541
 542         if (tspi->cur_direction & DATA_DIR_RX) {
 543                 /* Make the dma buffer to read by dma */
 544                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 545                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 546
 547                 ret = tegra_spi_start_rx_dma(tspi, len);
 548                 if (ret < 0) {
 549                         dev_err(tspi->dev,
 550                                 "Starting rx dma failed, err %d\n", ret);
 551                         if (tspi->cur_direction & DATA_DIR_TX)
 552                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 553                         return ret;
 554                 }
 555         }
 556         tspi->is_curr_dma_xfer = true;
 557         tspi->dma_control_reg = val;
 558
 559         val |= SPI_DMA_EN;
 560         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 561         return ret;
 562 }
 563
 564 static int tegra_spi_start_cpu_based_transfer(
 565                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 566 {
 567         unsigned long val;
 568         unsigned cur_words;
 569
 570         if (tspi->cur_direction & DATA_DIR_TX)
 571                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 572         else
 573                 cur_words = tspi->curr_dma_words;
 574
 575         val = SPI_DMA_BLK_SET(cur_words - 1);
 576         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 577
 578         val = 0;
 579         if (tspi->cur_direction & DATA_DIR_TX)
 580                 val |= SPI_IE_TX;
 581
 582         if (tspi->cur_direction & DATA_DIR_RX)
 583                 val |= SPI_IE_RX;
 584
 585         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 586         tspi->dma_control_reg = val;
 587
 588         tspi->is_curr_dma_xfer = false;
 589
 590         val |= SPI_DMA_EN;
 591         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 592         return 0;
 593 }
 594
 595 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 596                         bool dma_to_memory)
 597 {
 598         struct dma_chan *dma_chan;
 599         u32 *dma_buf;
 600         dma_addr_t dma_phys;
 601         int ret;
 602         struct dma_slave_config dma_sconfig;
 603         dma_cap_mask_t mask;
 604
 605         dma_cap_zero(mask);
 606         dma_cap_set(DMA_SLAVE, mask);
 607         dma_chan = dma_request_channel(mask, NULL, NULL);
 608         if (!dma_chan) {
 609                 dev_err(tspi->dev,
 610                         "Dma channel is not available, will try later\n");
 611                 return -EPROBE_DEFER;
 612         }
 613
 614         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 615                                 &dma_phys, GFP_KERNEL);
 616         if (!dma_buf) {
 617                 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 618                 dma_release_channel(dma_chan);
 619                 return -ENOMEM;
 620         }
 621
 622         dma_sconfig.slave_id = tspi->dma_req_sel;
 623         if (dma_to_memory) {
 624                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 625                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 626                 dma_sconfig.src_maxburst = 0;
 627         } else {
 628                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 629                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 630                 dma_sconfig.dst_maxburst = 0;
 631         }
 632
 633         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
 634         if (ret)
 635                 goto scrub;
 636         if (dma_to_memory) {
 637                 tspi->rx_dma_chan = dma_chan;
 638                 tspi->rx_dma_buf = dma_buf;
 639                 tspi->rx_dma_phys = dma_phys;
 640         } else {
 641                 tspi->tx_dma_chan = dma_chan;
 642                 tspi->tx_dma_buf = dma_buf;
 643                 tspi->tx_dma_phys = dma_phys;
 644         }
 645         return 0;
 646
 647 scrub:
 648         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 649         dma_release_channel(dma_chan);
 650         return ret;
 651 }
 652
 653 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 654         bool dma_to_memory)
 655 {
 656         u32 *dma_buf;
 657         dma_addr_t dma_phys;
 658         struct dma_chan *dma_chan;
 659
 660         if (dma_to_memory) {
 661                 dma_buf = tspi->rx_dma_buf;
 662                 dma_chan = tspi->rx_dma_chan;
 663                 dma_phys = tspi->rx_dma_phys;
 664                 tspi->rx_dma_chan = NULL;
 665                 tspi->rx_dma_buf = NULL;
 666         } else {
 667                 dma_buf = tspi->tx_dma_buf;
 668                 dma_chan = tspi->tx_dma_chan;
 669                 dma_phys = tspi->tx_dma_phys;
 670                 tspi->tx_dma_buf = NULL;
 671                 tspi->tx_dma_chan = NULL;
 672         }
 673         if (!dma_chan)
 674                 return;
 675
 676         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 677         dma_release_channel(dma_chan);
 678 }
 679
 680 static unsigned long tegra_spi_setup_transfer_one(struct spi_device *spi,
 681                 struct spi_transfer *t, bool is_first_of_msg)
 682 {
 683         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 684         u32 speed = t->speed_hz;
 685         u8 bits_per_word = t->bits_per_word;
 686         unsigned long command1;
 687         int req_mode;
 688
 689         if (speed != tspi->cur_speed) {
 690                 clk_set_rate(tspi->clk, speed);
 691                 tspi->cur_speed = speed;
 692         }
 693
 694         tspi->cur_spi = spi;
 695         tspi->cur_pos = 0;
 696         tspi->cur_rx_pos = 0;
 697         tspi->cur_tx_pos = 0;
 698         tspi->curr_xfer = t;
 699
 700         if (is_first_of_msg) {
 701                 tegra_spi_clear_status(tspi);
 702
 703                 command1 = tspi->def_command1_reg;
 704                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 705
 706                 command1 &= ~SPI_CONTROL_MODE_MASK;
 707                 req_mode = spi->mode & 0x3;
 708                 if (req_mode == SPI_MODE_0)
 709                         command1 |= SPI_CONTROL_MODE_0;
 710                 else if (req_mode == SPI_MODE_1)
 711                         command1 |= SPI_CONTROL_MODE_1;
 712                 else if (req_mode == SPI_MODE_2)
 713                         command1 |= SPI_CONTROL_MODE_2;
 714                 else if (req_mode == SPI_MODE_3)
 715                         command1 |= SPI_CONTROL_MODE_3;
 716
 717                 if (tspi->cs_control) {
 718                         if (tspi->cs_control != spi)
 719                                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 720                         tspi->cs_control = NULL;
 721                 } else
 722                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 723
 724                 command1 |= SPI_CS_SW_HW;
 725                 if (spi->mode & SPI_CS_HIGH)
 726                         command1 |= SPI_CS_SS_VAL;
 727                 else
 728                         command1 &= ~SPI_CS_SS_VAL;
 729
 730                 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
 731         } else {
 732                 command1 = tspi->command1_reg;
 733                 command1 &= ~SPI_BIT_LENGTH(~0);
 734                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 735         }
 736
 737         return command1;
 738 }
 739
 740 static int tegra_spi_start_transfer_one(struct spi_device *spi,
 741                 struct spi_transfer *t, unsigned long command1)
 742 {
 743         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 744         unsigned total_fifo_words;
 745         int ret;
 746
 747         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 748
 749         if (tspi->is_packed)
 750                 command1 |= SPI_PACKED;
 751
 752         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
 753         tspi->cur_direction = 0;
 754         if (t->rx_buf) {
 755                 command1 |= SPI_RX_EN;
 756                 tspi->cur_direction |= DATA_DIR_RX;
 757         }
 758         if (t->tx_buf) {
 759                 command1 |= SPI_TX_EN;
 760                 tspi->cur_direction |= DATA_DIR_TX;
 761         }
 762         command1 |= SPI_CS_SEL(spi->chip_select);
 763         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 764         tspi->command1_reg = command1;
 765
 766         dev_dbg(tspi->dev, "The def 0x%x and written 0x%lx\n",
 767                                 tspi->def_command1_reg, command1);
 768
 769         if (total_fifo_words > SPI_FIFO_DEPTH)
 770                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
 771         else
 772                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
 773         return ret;
 774 }
 775
 776 static int tegra_spi_setup(struct spi_device *spi)
 777 {
 778         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 779         unsigned long val;
 780         unsigned long flags;
 781         int ret;
 782         unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
 783                         SPI_CS_POL_INACTIVE_0,
 784                         SPI_CS_POL_INACTIVE_1,
 785                         SPI_CS_POL_INACTIVE_2,
 786                         SPI_CS_POL_INACTIVE_3,
 787         };
 788
 789         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 790                 spi->bits_per_word,
 791                 spi->mode & SPI_CPOL ? "" : "~",
 792                 spi->mode & SPI_CPHA ? "" : "~",
 793                 spi->max_speed_hz);
 794
 795         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
 796
 797         /* Set speed to the spi max fequency if spi device has not set */
 798         spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
 799
 800         ret = pm_runtime_get_sync(tspi->dev);
 801         if (ret < 0) {
 802                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 803                 return ret;
 804         }
 805
 806         spin_lock_irqsave(&tspi->lock, flags);
 807         val = tspi->def_command1_reg;
 808         if (spi->mode & SPI_CS_HIGH)
 809                 val &= ~cs_pol_bit[spi->chip_select];
 810         else
 811                 val |= cs_pol_bit[spi->chip_select];
 812         tspi->def_command1_reg = val;
 813         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 814         spin_unlock_irqrestore(&tspi->lock, flags);
 815
 816         pm_runtime_put(tspi->dev);
 817         return 0;
 818 }
 819
 820 static void tegra_spi_transfer_delay(int delay)
 821 {
 822         if (!delay)
 823                 return;
 824
 825         if (delay >= 1000)
 826                 mdelay(delay / 1000);
 827
 828         udelay(delay % 1000);
 829 }
 830
 831 static int tegra_spi_transfer_one_message(struct spi_master *master,
 832                         struct spi_message *msg)
 833 {
 834         bool is_first_msg = true;
 835         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
 836         struct spi_transfer *xfer;
 837         struct spi_device *spi = msg->spi;
 838         int ret;
 839         bool skip = false;
 840
 841         msg->status = 0;
 842         msg->actual_length = 0;
 843
 844         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 845                 unsigned long cmd1;
 846
 847                 INIT_COMPLETION(tspi->xfer_completion);
 848
 849                 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
 850
 851                 if (!xfer->len) {
 852                         ret = 0;
 853                         skip = true;
 854                         goto complete_xfer;
 855                 }
 856
 857                 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
 858                 if (ret < 0) {
 859                         dev_err(tspi->dev,
 860                                 "spi can not start transfer, err %d\n", ret);
 861                         goto complete_xfer;
 862                 }
 863
 864                 is_first_msg = false;
 865                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
 866                                                 SPI_DMA_TIMEOUT);
 867                 if (WARN_ON(ret == 0)) {
 868                         dev_err(tspi->dev,
 869                                 "spi trasfer timeout, err %d\n", ret);
 870                         ret = -EIO;
 871                         goto complete_xfer;
 872                 }
 873
 874                 if (tspi->tx_status ||  tspi->rx_status) {
 875                         dev_err(tspi->dev, "Error in Transfer\n");
 876                         ret = -EIO;
 877                         goto complete_xfer;
 878                 }
 879                 msg->actual_length += xfer->len;
 880
 881 complete_xfer:
 882                 if (ret < 0 || skip) {
 883                         tegra_spi_writel(tspi, tspi->def_command1_reg,
 884                                         SPI_COMMAND1);
 885                         tegra_spi_transfer_delay(xfer->delay_usecs);
 886                         goto exit;
 887                 } else if (msg->transfers.prev == &xfer->transfer_list) {
 888                         /* This is the last transfer in message */
 889                         if (xfer->cs_change)
 890                                 tspi->cs_control = spi;
 891                         else {
 892                                 tegra_spi_writel(tspi, tspi->def_command1_reg,
 893                                                 SPI_COMMAND1);
 894                                 tegra_spi_transfer_delay(xfer->delay_usecs);
 895                         }
 896                 } else if (xfer->cs_change) {
 897                         tegra_spi_writel(tspi, tspi->def_command1_reg,
 898                                         SPI_COMMAND1);
 899                         tegra_spi_transfer_delay(xfer->delay_usecs);
 900                 }
 901
 902         }
 903         ret = 0;
 904 exit:
 905         msg->status = ret;
 906         spi_finalize_current_message(master);
 907         return ret;
 908 }
 909
 910 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
 911 {
 912         struct spi_transfer *t = tspi->curr_xfer;
 913         unsigned long flags;
 914
 915         spin_lock_irqsave(&tspi->lock, flags);
 916         if (tspi->tx_status ||  tspi->rx_status) {
 917                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
 918                         tspi->status_reg);
 919                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
 920                         tspi->command1_reg, tspi->dma_control_reg);
 921                 tegra_periph_reset_assert(tspi->clk);
 922                 udelay(2);
 923                 tegra_periph_reset_deassert(tspi->clk);
 924                 complete(&tspi->xfer_completion);
 925                 goto exit;
 926         }
 927
 928         if (tspi->cur_direction & DATA_DIR_RX)
 929                 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
 930
 931         if (tspi->cur_direction & DATA_DIR_TX)
 932                 tspi->cur_pos = tspi->cur_tx_pos;
 933         else
 934                 tspi->cur_pos = tspi->cur_rx_pos;
 935
 936         if (tspi->cur_pos == t->len) {
 937                 complete(&tspi->xfer_completion);
 938                 goto exit;
 939         }
 940
 941         tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
 942         tegra_spi_start_cpu_based_transfer(tspi, t);
 943 exit:
 944         spin_unlock_irqrestore(&tspi->lock, flags);
 945         return IRQ_HANDLED;
 946 }
 947
 948 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
 949 {
 950         struct spi_transfer *t = tspi->curr_xfer;
 951         long wait_status;
 952         int err = 0;
 953         unsigned total_fifo_words;
 954         unsigned long flags;
 955
 956         /* Abort dmas if any error */
 957         if (tspi->cur_direction & DATA_DIR_TX) {
 958                 if (tspi->tx_status) {
 959                         dmaengine_terminate_all(tspi->tx_dma_chan);
 960                         err += 1;
 961                 } else {
 962                         wait_status = wait_for_completion_interruptible_timeout(
 963                                 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
 964                         if (wait_status <= 0) {
 965                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 966                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
 967                                 err += 1;
 968                         }
 969                 }
 970         }
 971
 972         if (tspi->cur_direction & DATA_DIR_RX) {
 973                 if (tspi->rx_status) {
 974                         dmaengine_terminate_all(tspi->rx_dma_chan);
 975                         err += 2;
 976                 } else {
 977                         wait_status = wait_for_completion_interruptible_timeout(
 978                                 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
 979                         if (wait_status <= 0) {
 980                                 dmaengine_terminate_all(tspi->rx_dma_chan);
 981                                 dev_err(tspi->dev, "RxDma Xfer failed\n");
 982                                 err += 2;
 983                         }
 984                 }
 985         }
 986
 987         spin_lock_irqsave(&tspi->lock, flags);
 988         if (err) {
 989                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
 990                         tspi->status_reg);
 991                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
 992                         tspi->command1_reg, tspi->dma_control_reg);
 993                 tegra_periph_reset_assert(tspi->clk);
 994                 udelay(2);
 995                 tegra_periph_reset_deassert(tspi->clk);
 996                 complete(&tspi->xfer_completion);
 997                 spin_unlock_irqrestore(&tspi->lock, flags);
 998                 return IRQ_HANDLED;
 999         }
1000
1001         if (tspi->cur_direction & DATA_DIR_RX)
1002                 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1003
1004         if (tspi->cur_direction & DATA_DIR_TX)
1005                 tspi->cur_pos = tspi->cur_tx_pos;
1006         else
1007                 tspi->cur_pos = tspi->cur_rx_pos;
1008
1009         if (tspi->cur_pos == t->len) {
1010                 complete(&tspi->xfer_completion);
1011                 goto exit;
1012         }
1013
1014         /* Continue transfer in current message */
1015         total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1016                                                         tspi, t);
1017         if (total_fifo_words > SPI_FIFO_DEPTH)
1018                 err = tegra_spi_start_dma_based_transfer(tspi, t);
1019         else
1020                 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1021
1022 exit:
1023         spin_unlock_irqrestore(&tspi->lock, flags);
1024         return IRQ_HANDLED;
1025 }
1026
1027 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1028 {
1029         struct tegra_spi_data *tspi = context_data;
1030
1031         if (!tspi->is_curr_dma_xfer)
1032                 return handle_cpu_based_xfer(tspi);
1033         return handle_dma_based_xfer(tspi);
1034 }
1035
1036 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1037 {
1038         struct tegra_spi_data *tspi = context_data;
1039
1040         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1041         if (tspi->cur_direction & DATA_DIR_TX)
1042                 tspi->tx_status = tspi->status_reg &
1043                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1044
1045         if (tspi->cur_direction & DATA_DIR_RX)
1046                 tspi->rx_status = tspi->status_reg &
1047                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1048         tegra_spi_clear_status(tspi);
1049
1050         return IRQ_WAKE_THREAD;
1051 }
1052
1053 static void tegra_spi_parse_dt(struct platform_device *pdev,
1054         struct tegra_spi_data *tspi)
1055 {
1056         struct device_node *np = pdev->dev.of_node;
1057         u32 of_dma[2];
1058
1059         if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1060                                 of_dma, 2) >= 0)
1061                 tspi->dma_req_sel = of_dma[1];
1062
1063         if (of_property_read_u32(np, "spi-max-frequency",
1064                                 &tspi->spi_max_frequency))
1065                 tspi->spi_max_frequency = 25000000; /* 25MHz */
1066 }
1067
1068 static struct of_device_id tegra_spi_of_match[] = {
1069         { .compatible = "nvidia,tegra114-spi", },
1070         {}
1071 };
1072 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1073
1074 static int tegra_spi_probe(struct platform_device *pdev)
1075 {
1076         struct spi_master       *master;
1077         struct tegra_spi_data   *tspi;
1078         struct resource         *r;
1079         int ret, spi_irq;
1080
1081         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1082         if (!master) {
1083                 dev_err(&pdev->dev, "master allocation failed\n");
1084                 return -ENOMEM;
1085         }
1086         platform_set_drvdata(pdev, master);
1087         tspi = spi_master_get_devdata(master);
1088
1089         /* Parse DT */
1090         tegra_spi_parse_dt(pdev, tspi);
1091
1092         /* the spi->mode bits understood by this driver: */
1093         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1094         master->setup = tegra_spi_setup;
1095         master->transfer_one_message = tegra_spi_transfer_one_message;
1096         master->num_chipselect = MAX_CHIP_SELECT;
1097         master->bus_num = -1;
1098         master->auto_runtime_pm = true;
1099
1100         tspi->master = master;
1101         tspi->dev = &pdev->dev;
1102         spin_lock_init(&tspi->lock);
1103
1104         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1106         if (IS_ERR(tspi->base)) {
1107                 ret = PTR_ERR(tspi->base);
1108                 goto exit_free_master;
1109         }
1110         tspi->phys = r->start;
1111
1112         spi_irq = platform_get_irq(pdev, 0);
1113         tspi->irq = spi_irq;
1114         ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1115                         tegra_spi_isr_thread, IRQF_ONESHOT,
1116                         dev_name(&pdev->dev), tspi);
1117         if (ret < 0) {
1118                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1119                                         tspi->irq);
1120                 goto exit_free_master;
1121         }
1122
1123         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1124         if (IS_ERR(tspi->clk)) {
1125                 dev_err(&pdev->dev, "can not get clock\n");
1126                 ret = PTR_ERR(tspi->clk);
1127                 goto exit_free_irq;
1128         }
1129
1130         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1131         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1132
1133         if (tspi->dma_req_sel) {
1134                 ret = tegra_spi_init_dma_param(tspi, true);
1135                 if (ret < 0) {
1136                         dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
1137                         goto exit_free_irq;
1138                 }
1139
1140                 ret = tegra_spi_init_dma_param(tspi, false);
1141                 if (ret < 0) {
1142                         dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1143                         goto exit_rx_dma_free;
1144                 }
1145                 tspi->max_buf_size = tspi->dma_buf_size;
1146                 init_completion(&tspi->tx_dma_complete);
1147                 init_completion(&tspi->rx_dma_complete);
1148         }
1149
1150         init_completion(&tspi->xfer_completion);
1151
1152         pm_runtime_enable(&pdev->dev);
1153         if (!pm_runtime_enabled(&pdev->dev)) {
1154                 ret = tegra_spi_runtime_resume(&pdev->dev);
1155                 if (ret)
1156                         goto exit_pm_disable;
1157         }
1158
1159         ret = pm_runtime_get_sync(&pdev->dev);
1160         if (ret < 0) {
1161                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1162                 goto exit_pm_disable;
1163         }
1164         tspi->def_command1_reg  = SPI_M_S;
1165         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1166         pm_runtime_put(&pdev->dev);
1167
1168         master->dev.of_node = pdev->dev.of_node;
1169         ret = devm_spi_register_master(&pdev->dev, master);
1170         if (ret < 0) {
1171                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1172                 goto exit_pm_disable;
1173         }
1174         return ret;
1175
1176 exit_pm_disable:
1177         pm_runtime_disable(&pdev->dev);
1178         if (!pm_runtime_status_suspended(&pdev->dev))
1179                 tegra_spi_runtime_suspend(&pdev->dev);
1180         tegra_spi_deinit_dma_param(tspi, false);
1181 exit_rx_dma_free:
1182         tegra_spi_deinit_dma_param(tspi, true);
1183 exit_free_irq:
1184         free_irq(spi_irq, tspi);
1185 exit_free_master:
1186         spi_master_put(master);
1187         return ret;
1188 }
1189
1190 static int tegra_spi_remove(struct platform_device *pdev)
1191 {
1192         struct spi_master *master = platform_get_drvdata(pdev);
1193         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1194
1195         free_irq(tspi->irq, tspi);
1196
1197         if (tspi->tx_dma_chan)
1198                 tegra_spi_deinit_dma_param(tspi, false);
1199
1200         if (tspi->rx_dma_chan)
1201                 tegra_spi_deinit_dma_param(tspi, true);
1202
1203         pm_runtime_disable(&pdev->dev);
1204         if (!pm_runtime_status_suspended(&pdev->dev))
1205                 tegra_spi_runtime_suspend(&pdev->dev);
1206
1207         return 0;
1208 }
1209
1210 #ifdef CONFIG_PM_SLEEP
1211 static int tegra_spi_suspend(struct device *dev)
1212 {
1213         struct spi_master *master = dev_get_drvdata(dev);
1214
1215         return spi_master_suspend(master);
1216 }
1217
1218 static int tegra_spi_resume(struct device *dev)
1219 {
1220         struct spi_master *master = dev_get_drvdata(dev);
1221         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1222         int ret;
1223
1224         ret = pm_runtime_get_sync(dev);
1225         if (ret < 0) {
1226                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1227                 return ret;
1228         }
1229         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1230         pm_runtime_put(dev);
1231
1232         return spi_master_resume(master);
1233 }
1234 #endif
1235
1236 static int tegra_spi_runtime_suspend(struct device *dev)
1237 {
1238         struct spi_master *master = dev_get_drvdata(dev);
1239         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1240
1241         /* Flush all write which are in PPSB queue by reading back */
1242         tegra_spi_readl(tspi, SPI_COMMAND1);
1243
1244         clk_disable_unprepare(tspi->clk);
1245         return 0;
1246 }
1247
1248 static int tegra_spi_runtime_resume(struct device *dev)
1249 {
1250         struct spi_master *master = dev_get_drvdata(dev);
1251         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1252         int ret;
1253
1254         ret = clk_prepare_enable(tspi->clk);
1255         if (ret < 0) {
1256                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1257                 return ret;
1258         }
1259         return 0;
1260 }
1261
1262 static const struct dev_pm_ops tegra_spi_pm_ops = {
1263         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1264                 tegra_spi_runtime_resume, NULL)
1265         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1266 };
1267 static struct platform_driver tegra_spi_driver = {
1268         .driver = {
1269                 .name           = "spi-tegra114",
1270                 .owner          = THIS_MODULE,
1271                 .pm             = &tegra_spi_pm_ops,
1272                 .of_match_table = tegra_spi_of_match,
1273         },
1274         .probe =        tegra_spi_probe,
1275         .remove =       tegra_spi_remove,
1276 };
1277 module_platform_driver(tegra_spi_driver);
1278
1279 MODULE_ALIAS("platform:spi-tegra114");
1280 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1281 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1282 MODULE_LICENSE("GPL v2");