2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
4 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
34 /* Register offsets */
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
41 #define PCH_SRST 0x1C /* SPI reset register */
42 #define PCH_ADDRESS_SIZE 0x20
44 #define PCH_SPSR_TFD 0x000007C0
45 #define PCH_SPSR_RFD 0x0000F800
47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
50 #define PCH_RX_THOLD 7
51 #define PCH_RX_THOLD_MAX 15
53 #define PCH_MAX_BAUDRATE 5000000
54 #define PCH_MAX_FIFO_DEPTH 16
56 #define STATUS_RUNNING 1
57 #define STATUS_EXITING 2
58 #define PCH_SLEEP_TIME 10
61 #define SSN_NO_CONTROL 0x00U
62 #define PCH_MAX_CS 0xFF
63 #define PCI_DEVICE_ID_GE_SPI 0x8816
65 #define SPCR_SPE_BIT (1 << 0)
66 #define SPCR_MSTR_BIT (1 << 1)
67 #define SPCR_LSBF_BIT (1 << 4)
68 #define SPCR_CPHA_BIT (1 << 5)
69 #define SPCR_CPOL_BIT (1 << 6)
70 #define SPCR_TFIE_BIT (1 << 8)
71 #define SPCR_RFIE_BIT (1 << 9)
72 #define SPCR_FIE_BIT (1 << 10)
73 #define SPCR_ORIE_BIT (1 << 11)
74 #define SPCR_MDFIE_BIT (1 << 12)
75 #define SPCR_FICLR_BIT (1 << 24)
76 #define SPSR_TFI_BIT (1 << 0)
77 #define SPSR_RFI_BIT (1 << 1)
78 #define SPSR_FI_BIT (1 << 2)
79 #define SPSR_ORF_BIT (1 << 3)
80 #define SPBRR_SIZE_BIT (1 << 10)
82 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
83 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
85 #define SPCR_RFIC_FIELD 20
86 #define SPCR_TFIC_FIELD 16
88 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
89 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
90 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
92 #define PCH_CLOCK_HZ 50000000
93 #define PCH_MAX_SPBR 1023
95 /* Definition for ML7213 by OKI SEMICONDUCTOR */
96 #define PCI_VENDOR_ID_ROHM 0x10DB
97 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
98 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
101 * Set the number of SPI instance max
102 * Intel EG20T PCH : 1ch
103 * OKI SEMICONDUCTOR ML7213 IOH : 2ch
104 * OKI SEMICONDUCTOR ML7223 IOH : 1ch
106 #define PCH_SPI_MAX_DEV 2
108 #define PCH_BUF_SIZE 4096
109 #define PCH_DMA_TRANS_SIZE 12
111 static int use_dma = 1;
113 struct pch_spi_dma_ctrl {
114 struct dma_async_tx_descriptor *desc_tx;
115 struct dma_async_tx_descriptor *desc_rx;
116 struct pch_dma_slave param_tx;
117 struct pch_dma_slave param_rx;
118 struct dma_chan *chan_tx;
119 struct dma_chan *chan_rx;
120 struct scatterlist *sg_tx_p;
121 struct scatterlist *sg_rx_p;
122 struct scatterlist sg_tx;
123 struct scatterlist sg_rx;
127 dma_addr_t tx_buf_dma;
128 dma_addr_t rx_buf_dma;
131 * struct pch_spi_data - Holds the SPI channel specific details
132 * @io_remap_addr: The remapped PCI base address
133 * @master: Pointer to the SPI master structure
134 * @work: Reference to work queue handler
135 * @wk: Workqueue for carrying out execution of the
137 * @wait: Wait queue for waking up upon receiving an
139 * @transfer_complete: Status of SPI Transfer
140 * @bcurrent_msg_processing: Status flag for message processing
141 * @lock: Lock for protecting this structure
142 * @queue: SPI Message queue
143 * @status: Status of the SPI driver
144 * @bpw_len: Length of data to be transferred in bits per
146 * @transfer_active: Flag showing active transfer
147 * @tx_index: Transmit data count; for bookkeeping during
149 * @rx_index: Receive data count; for bookkeeping during
151 * @tx_buff: Buffer for data to be transmitted
152 * @rx_index: Buffer for Received data
153 * @n_curnt_chip: The chip number that this SPI driver currently
155 * @current_chip: Reference to the current chip that this SPI
156 * driver currently operates on
157 * @current_msg: The current message that this SPI driver is
159 * @cur_trans: The current transfer that this SPI driver is
161 * @board_dat: Reference to the SPI device data structure
162 * @plat_dev: platform_device structure
163 * @ch: SPI channel number
164 * @irq_reg_sts: Status of IRQ registration
166 struct pch_spi_data {
167 void __iomem *io_remap_addr;
168 unsigned long io_base_addr;
169 struct spi_master *master;
170 struct work_struct work;
171 struct workqueue_struct *wk;
172 wait_queue_head_t wait;
173 u8 transfer_complete;
174 u8 bcurrent_msg_processing;
176 struct list_head queue;
185 struct spi_device *current_chip;
186 struct spi_message *current_msg;
187 struct spi_transfer *cur_trans;
188 struct pch_spi_board_data *board_dat;
189 struct platform_device *plat_dev;
191 struct pch_spi_dma_ctrl dma;
197 * struct pch_spi_board_data - Holds the SPI device specific details
198 * @pdev: Pointer to the PCI device
199 * @suspend_sts: Status of suspend
200 * @num: The number of SPI device instance
202 struct pch_spi_board_data {
203 struct pci_dev *pdev;
208 struct pch_pd_dev_save {
210 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
211 struct pch_spi_board_data *board_dat;
214 static struct pci_device_id pch_spi_pcidev_id[] = {
215 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
216 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
217 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
222 * pch_spi_writereg() - Performs register writes
223 * @master: Pointer to struct spi_master.
224 * @idx: Register offset.
225 * @val: Value to be written to register.
227 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
229 struct pch_spi_data *data = spi_master_get_devdata(master);
230 iowrite32(val, (data->io_remap_addr + idx));
234 * pch_spi_readreg() - Performs register reads
235 * @master: Pointer to struct spi_master.
236 * @idx: Register offset.
238 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
240 struct pch_spi_data *data = spi_master_get_devdata(master);
241 return ioread32(data->io_remap_addr + idx);
244 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
247 u32 tmp = pch_spi_readreg(master, idx);
248 tmp = (tmp & ~clr) | set;
249 pch_spi_writereg(master, idx, tmp);
252 static void pch_spi_set_master_mode(struct spi_master *master)
254 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
258 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
259 * @master: Pointer to struct spi_master.
261 static void pch_spi_clear_fifo(struct spi_master *master)
263 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
264 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
267 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
268 void __iomem *io_remap_addr)
270 u32 n_read, tx_index, rx_index, bpw_len;
271 u16 *pkt_rx_buffer, *pkt_tx_buff;
278 spsr = io_remap_addr + PCH_SPSR;
279 iowrite32(reg_spsr_val, spsr);
281 if (data->transfer_active) {
282 rx_index = data->rx_index;
283 tx_index = data->tx_index;
284 bpw_len = data->bpw_len;
285 pkt_rx_buffer = data->pkt_rx_buff;
286 pkt_tx_buff = data->pkt_tx_buff;
288 spdrr = io_remap_addr + PCH_SPDRR;
289 spdwr = io_remap_addr + PCH_SPDWR;
291 n_read = PCH_READABLE(reg_spsr_val);
293 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
294 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
295 if (tx_index < bpw_len)
296 iowrite32(pkt_tx_buff[tx_index++], spdwr);
299 /* disable RFI if not needed */
300 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
301 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
302 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
304 /* reset rx threshold */
305 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
306 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
308 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
312 data->tx_index = tx_index;
313 data->rx_index = rx_index;
317 /* if transfer complete interrupt */
318 if (reg_spsr_val & SPSR_FI_BIT) {
319 if (tx_index < bpw_len)
320 dev_err(&data->master->dev,
321 "%s : Transfer is not completed", __func__);
322 /* disable interrupts */
323 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
325 /* transfer is completed;inform pch_spi_process_messages */
326 data->transfer_complete = true;
327 data->transfer_active = false;
328 wake_up(&data->wait);
333 * pch_spi_handler() - Interrupt handler
334 * @irq: The interrupt number.
335 * @dev_id: Pointer to struct pch_spi_board_data.
337 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
341 void __iomem *io_remap_addr;
342 irqreturn_t ret = IRQ_NONE;
343 struct pch_spi_data *data = dev_id;
344 struct pch_spi_board_data *board_dat = data->board_dat;
346 if (board_dat->suspend_sts) {
347 dev_dbg(&board_dat->pdev->dev,
348 "%s returning due to suspend\n", __func__);
354 io_remap_addr = data->io_remap_addr;
355 spsr = io_remap_addr + PCH_SPSR;
357 reg_spsr_val = ioread32(spsr);
359 if (reg_spsr_val & SPSR_ORF_BIT)
360 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
362 /* Check if the interrupt is for SPI device */
363 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
364 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
368 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
375 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
376 * @master: Pointer to struct spi_master.
377 * @speed_hz: Baud rate.
379 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
381 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
383 /* if baud rate is less than we can support limit it */
384 if (n_spbr > PCH_MAX_SPBR)
385 n_spbr = PCH_MAX_SPBR;
387 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
391 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
392 * @master: Pointer to struct spi_master.
393 * @bits_per_word: Bits per word for SPI transfer.
395 static void pch_spi_set_bits_per_word(struct spi_master *master,
398 if (bits_per_word == 8)
399 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
401 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
405 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
406 * @spi: Pointer to struct spi_device.
408 static void pch_spi_setup_transfer(struct spi_device *spi)
412 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
413 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
415 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
417 /* set bits per word */
418 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
420 if (!(spi->mode & SPI_LSB_FIRST))
421 flags |= SPCR_LSBF_BIT;
422 if (spi->mode & SPI_CPOL)
423 flags |= SPCR_CPOL_BIT;
424 if (spi->mode & SPI_CPHA)
425 flags |= SPCR_CPHA_BIT;
426 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
427 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
429 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
430 pch_spi_clear_fifo(spi->master);
434 * pch_spi_reset() - Clears SPI registers
435 * @master: Pointer to struct spi_master.
437 static void pch_spi_reset(struct spi_master *master)
439 /* write 1 to reset SPI */
440 pch_spi_writereg(master, PCH_SRST, 0x1);
443 pch_spi_writereg(master, PCH_SRST, 0x0);
446 static int pch_spi_setup(struct spi_device *pspi)
448 /* check bits per word */
449 if (pspi->bits_per_word == 0) {
450 pspi->bits_per_word = 8;
451 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
454 if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
455 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
459 /* Check baud rate setting */
460 /* if baud rate of chip is greater than
461 max we can support,return error */
462 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
463 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
465 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
466 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
471 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
474 struct spi_transfer *transfer;
475 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
479 /* validate spi message and baud rate */
480 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
481 dev_err(&pspi->dev, "%s list empty\n", __func__);
486 if (unlikely(pspi->max_speed_hz == 0)) {
487 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
488 __func__, pspi->max_speed_hz);
493 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
494 "Transfer Speed is set.\n", __func__);
496 spin_lock_irqsave(&data->lock, flags);
497 /* validate Tx/Rx buffers and Transfer length */
498 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
499 if (!transfer->tx_buf && !transfer->rx_buf) {
501 "%s Tx and Rx buffer NULL\n", __func__);
503 goto err_return_spinlock;
506 if (!transfer->len) {
507 dev_err(&pspi->dev, "%s Transfer length invalid\n",
510 goto err_return_spinlock;
513 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
514 " valid\n", __func__);
516 /* if baud rate has been specified validate the same */
517 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
518 transfer->speed_hz = PCH_MAX_BAUDRATE;
520 /* if bits per word has been specified validate the same */
521 if (transfer->bits_per_word) {
522 if ((transfer->bits_per_word != 8)
523 && (transfer->bits_per_word != 16)) {
526 "%s Invalid bits per word\n", __func__);
527 goto err_return_spinlock;
531 spin_unlock_irqrestore(&data->lock, flags);
533 /* We won't process any messages if we have been asked to terminate */
534 if (data->status == STATUS_EXITING) {
535 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
540 /* If suspended ,return -EINVAL */
541 if (data->board_dat->suspend_sts) {
542 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
547 /* set status of message */
548 pmsg->actual_length = 0;
549 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
551 pmsg->status = -EINPROGRESS;
552 spin_lock_irqsave(&data->lock, flags);
553 /* add message to queue */
554 list_add_tail(&pmsg->queue, &data->queue);
555 spin_unlock_irqrestore(&data->lock, flags);
557 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
559 /* schedule work queue to run */
560 queue_work(data->wk, &data->work);
561 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
566 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
569 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
570 spin_unlock_irqrestore(&data->lock, flags);
574 static inline void pch_spi_select_chip(struct pch_spi_data *data,
575 struct spi_device *pspi)
577 if (data->current_chip != NULL) {
578 if (pspi->chip_select != data->n_curnt_chip) {
579 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
580 data->current_chip = NULL;
584 data->current_chip = pspi;
586 data->n_curnt_chip = data->current_chip->chip_select;
588 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
589 pch_spi_setup_transfer(pspi);
592 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
597 struct spi_message *pmsg;
601 /* set baud rate if needed */
602 if (data->cur_trans->speed_hz) {
603 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
604 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
607 /* set bits per word if needed */
608 if (data->cur_trans->bits_per_word &&
609 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
610 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
611 pch_spi_set_bits_per_word(data->master,
612 data->cur_trans->bits_per_word);
613 *bpw = data->cur_trans->bits_per_word;
615 *bpw = data->current_msg->spi->bits_per_word;
618 /* reset Tx/Rx index */
622 data->bpw_len = data->cur_trans->len / (*bpw / 8);
624 /* find alloc size */
625 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
627 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
628 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
629 if (data->pkt_tx_buff != NULL) {
630 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
631 if (!data->pkt_rx_buff)
632 kfree(data->pkt_tx_buff);
635 if (!data->pkt_rx_buff) {
636 /* flush queue and set status of all transfers to -ENOMEM */
637 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
638 list_for_each_entry(pmsg, data->queue.next, queue) {
639 pmsg->status = -ENOMEM;
641 if (pmsg->complete != 0)
642 pmsg->complete(pmsg->context);
644 /* delete from queue */
645 list_del_init(&pmsg->queue);
651 if (data->cur_trans->tx_buf != NULL) {
653 tx_buf = data->cur_trans->tx_buf;
654 for (j = 0; j < data->bpw_len; j++)
655 data->pkt_tx_buff[j] = *tx_buf++;
657 tx_sbuf = data->cur_trans->tx_buf;
658 for (j = 0; j < data->bpw_len; j++)
659 data->pkt_tx_buff[j] = *tx_sbuf++;
663 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
664 n_writes = data->bpw_len;
665 if (n_writes > PCH_MAX_FIFO_DEPTH)
666 n_writes = PCH_MAX_FIFO_DEPTH;
668 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
669 "0x2 to SSNXCR\n", __func__);
670 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
672 for (j = 0; j < n_writes; j++)
673 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
675 /* update tx_index */
678 /* reset transfer complete flag */
679 data->transfer_complete = false;
680 data->transfer_active = true;
683 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
685 struct spi_message *pmsg;
686 dev_dbg(&data->master->dev, "%s called\n", __func__);
687 /* Invoke complete callback
688 * [To the spi core..indicating end of transfer] */
689 data->current_msg->status = 0;
691 if (data->current_msg->complete != 0) {
692 dev_dbg(&data->master->dev,
693 "%s:Invoking callback of SPI core\n", __func__);
694 data->current_msg->complete(data->current_msg->context);
697 /* update status in global variable */
698 data->bcurrent_msg_processing = false;
700 dev_dbg(&data->master->dev,
701 "%s:data->bcurrent_msg_processing = false\n", __func__);
703 data->current_msg = NULL;
704 data->cur_trans = NULL;
706 /* check if we have items in list and not suspending
707 * return 1 if list empty */
708 if ((list_empty(&data->queue) == 0) &&
709 (!data->board_dat->suspend_sts) &&
710 (data->status != STATUS_EXITING)) {
711 /* We have some more work to do (either there is more tranint
712 * bpw;sfer requests in the current message or there are
715 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
716 queue_work(data->wk, &data->work);
717 } else if (data->board_dat->suspend_sts ||
718 data->status == STATUS_EXITING) {
719 dev_dbg(&data->master->dev,
720 "%s suspend/remove initiated, flushing queue\n",
722 list_for_each_entry(pmsg, data->queue.next, queue) {
726 pmsg->complete(pmsg->context);
728 /* delete from queue */
729 list_del_init(&pmsg->queue);
734 static void pch_spi_set_ir(struct pch_spi_data *data)
736 /* enable interrupts, set threshold, enable SPI */
737 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
738 /* set receive threshold to PCH_RX_THOLD */
739 pch_spi_setclr_reg(data->master, PCH_SPCR,
740 PCH_RX_THOLD << SPCR_RFIC_FIELD |
741 SPCR_FIE_BIT | SPCR_RFIE_BIT |
742 SPCR_ORIE_BIT | SPCR_SPE_BIT,
743 MASK_RFIC_SPCR_BITS | PCH_ALL);
745 /* set receive threshold to maximum */
746 pch_spi_setclr_reg(data->master, PCH_SPCR,
747 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
748 SPCR_FIE_BIT | SPCR_ORIE_BIT |
750 MASK_RFIC_SPCR_BITS | PCH_ALL);
752 /* Wait until the transfer completes; go to sleep after
753 initiating the transfer. */
754 dev_dbg(&data->master->dev,
755 "%s:waiting for transfer to get over\n", __func__);
757 wait_event_interruptible(data->wait, data->transfer_complete);
759 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
760 dev_dbg(&data->master->dev,
761 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
763 /* clear all interrupts */
764 pch_spi_writereg(data->master, PCH_SPSR,
765 pch_spi_readreg(data->master, PCH_SPSR));
766 /* Disable interrupts and SPI transfer */
767 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
769 pch_spi_clear_fifo(data->master);
772 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
779 if (!data->cur_trans->rx_buf)
783 rx_buf = data->cur_trans->rx_buf;
784 for (j = 0; j < data->bpw_len; j++)
785 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
787 rx_sbuf = data->cur_trans->rx_buf;
788 for (j = 0; j < data->bpw_len; j++)
789 *rx_sbuf++ = data->pkt_rx_buff[j];
793 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
798 const u8 *rx_dma_buf;
799 const u16 *rx_dma_sbuf;
802 if (!data->cur_trans->rx_buf)
806 rx_buf = data->cur_trans->rx_buf;
807 rx_dma_buf = data->dma.rx_buf_virt;
808 for (j = 0; j < data->bpw_len; j++)
809 *rx_buf++ = *rx_dma_buf++ & 0xFF;
811 rx_sbuf = data->cur_trans->rx_buf;
812 rx_dma_sbuf = data->dma.rx_buf_virt;
813 for (j = 0; j < data->bpw_len; j++)
814 *rx_sbuf++ = *rx_dma_sbuf++;
818 static void pch_spi_start_transfer(struct pch_spi_data *data)
820 struct pch_spi_dma_ctrl *dma;
825 spin_lock_irqsave(&data->lock, flags);
827 /* disable interrupts, SPI set enable */
828 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
830 spin_unlock_irqrestore(&data->lock, flags);
832 /* Wait until the transfer completes; go to sleep after
833 initiating the transfer. */
834 dev_dbg(&data->master->dev,
835 "%s:waiting for transfer to get over\n", __func__);
836 wait_event_interruptible(data->wait, data->transfer_complete);
838 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
841 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
843 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
845 async_tx_ack(dma->desc_rx);
846 async_tx_ack(dma->desc_tx);
850 spin_lock_irqsave(&data->lock, flags);
851 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
852 dev_dbg(&data->master->dev,
853 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
855 /* clear fifo threshold, disable interrupts, disable SPI transfer */
856 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
857 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
859 /* clear all interrupts */
860 pch_spi_writereg(data->master, PCH_SPSR,
861 pch_spi_readreg(data->master, PCH_SPSR));
863 pch_spi_clear_fifo(data->master);
865 spin_unlock_irqrestore(&data->lock, flags);
868 static void pch_dma_rx_complete(void *arg)
870 struct pch_spi_data *data = arg;
872 /* transfer is completed;inform pch_spi_process_messages_dma */
873 data->transfer_complete = true;
874 wake_up_interruptible(&data->wait);
877 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
879 struct pch_dma_slave *param = slave;
881 if ((chan->chan_id == param->chan_id) &&
882 (param->dma_dev == chan->device->dev)) {
883 chan->private = param;
890 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
893 struct dma_chan *chan;
894 struct pci_dev *dma_dev;
895 struct pch_dma_slave *param;
896 struct pch_spi_dma_ctrl *dma;
900 width = PCH_DMA_WIDTH_1_BYTE;
902 width = PCH_DMA_WIDTH_2_BYTES;
906 dma_cap_set(DMA_SLAVE, mask);
908 /* Get DMA's dev information */
909 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
912 param = &dma->param_tx;
913 param->dma_dev = &dma_dev->dev;
914 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
915 param->tx_reg = data->io_base_addr + PCH_SPDWR;
916 param->width = width;
917 chan = dma_request_channel(mask, pch_spi_filter, param);
919 dev_err(&data->master->dev,
920 "ERROR: dma_request_channel FAILS(Tx)\n");
927 param = &dma->param_rx;
928 param->dma_dev = &dma_dev->dev;
929 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
930 param->rx_reg = data->io_base_addr + PCH_SPDRR;
931 param->width = width;
932 chan = dma_request_channel(mask, pch_spi_filter, param);
934 dev_err(&data->master->dev,
935 "ERROR: dma_request_channel FAILS(Rx)\n");
936 dma_release_channel(dma->chan_tx);
944 static void pch_spi_release_dma(struct pch_spi_data *data)
946 struct pch_spi_dma_ctrl *dma;
950 dma_release_channel(dma->chan_tx);
954 dma_release_channel(dma->chan_rx);
960 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
966 struct scatterlist *sg;
967 struct dma_async_tx_descriptor *desc_tx;
968 struct dma_async_tx_descriptor *desc_rx;
974 struct pch_spi_dma_ctrl *dma;
978 /* set baud rate if needed */
979 if (data->cur_trans->speed_hz) {
980 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
981 spin_lock_irqsave(&data->lock, flags);
982 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
983 spin_unlock_irqrestore(&data->lock, flags);
986 /* set bits per word if needed */
987 if (data->cur_trans->bits_per_word &&
988 (data->current_msg->spi->bits_per_word !=
989 data->cur_trans->bits_per_word)) {
990 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
991 spin_lock_irqsave(&data->lock, flags);
992 pch_spi_set_bits_per_word(data->master,
993 data->cur_trans->bits_per_word);
994 spin_unlock_irqrestore(&data->lock, flags);
995 *bpw = data->cur_trans->bits_per_word;
997 *bpw = data->current_msg->spi->bits_per_word;
999 data->bpw_len = data->cur_trans->len / (*bpw / 8);
1002 if (data->cur_trans->tx_buf != NULL) {
1004 tx_buf = data->cur_trans->tx_buf;
1005 tx_dma_buf = dma->tx_buf_virt;
1006 for (i = 0; i < data->bpw_len; i++)
1007 *tx_dma_buf++ = *tx_buf++;
1009 tx_sbuf = data->cur_trans->tx_buf;
1010 tx_dma_sbuf = dma->tx_buf_virt;
1011 for (i = 0; i < data->bpw_len; i++)
1012 *tx_dma_sbuf++ = *tx_sbuf++;
1015 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1016 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1017 size = PCH_DMA_TRANS_SIZE;
1018 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1021 size = data->bpw_len;
1022 rem = data->bpw_len;
1024 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1025 __func__, num, size, rem);
1026 spin_lock_irqsave(&data->lock, flags);
1028 /* set receive fifo threshold and transmit fifo threshold */
1029 pch_spi_setclr_reg(data->master, PCH_SPCR,
1030 ((size - 1) << SPCR_RFIC_FIELD) |
1031 ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1033 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1035 spin_unlock_irqrestore(&data->lock, flags);
1038 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1039 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1040 /* offset, length setting */
1042 for (i = 0; i < num; i++, sg++) {
1045 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1047 sg_dma_len(sg) = rem;
1049 sg->offset = rem + size * (i - 1);
1050 sg->offset = sg->offset * (*bpw / 8);
1051 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1053 sg_dma_len(sg) = size;
1055 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1058 desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1059 num, DMA_FROM_DEVICE,
1060 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1062 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1066 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1067 desc_rx->callback = pch_dma_rx_complete;
1068 desc_rx->callback_param = data;
1070 dma->desc_rx = desc_rx;
1073 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1074 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1075 /* offset, length setting */
1077 for (i = 0; i < num; i++, sg++) {
1080 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1082 sg_dma_len(sg) = rem;
1084 sg->offset = rem + size * (i - 1);
1085 sg->offset = sg->offset * (*bpw / 8);
1086 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1088 sg_dma_len(sg) = size;
1090 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1093 desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1094 sg, num, DMA_TO_DEVICE,
1095 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1097 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1101 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1102 desc_tx->callback = NULL;
1103 desc_tx->callback_param = data;
1105 dma->desc_tx = desc_tx;
1107 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1108 "0x2 to SSNXCR\n", __func__);
1110 spin_lock_irqsave(&data->lock, flags);
1111 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1112 desc_rx->tx_submit(desc_rx);
1113 desc_tx->tx_submit(desc_tx);
1114 spin_unlock_irqrestore(&data->lock, flags);
1116 /* reset transfer complete flag */
1117 data->transfer_complete = false;
1120 static void pch_spi_process_messages(struct work_struct *pwork)
1122 struct spi_message *pmsg;
1123 struct pch_spi_data *data;
1126 data = container_of(pwork, struct pch_spi_data, work);
1127 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1129 spin_lock(&data->lock);
1130 /* check if suspend has been initiated;if yes flush queue */
1131 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1132 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1133 "flushing queue\n", __func__);
1134 list_for_each_entry(pmsg, data->queue.next, queue) {
1135 pmsg->status = -EIO;
1137 if (pmsg->complete != 0) {
1138 spin_unlock(&data->lock);
1139 pmsg->complete(pmsg->context);
1140 spin_lock(&data->lock);
1143 /* delete from queue */
1144 list_del_init(&pmsg->queue);
1147 spin_unlock(&data->lock);
1151 data->bcurrent_msg_processing = true;
1152 dev_dbg(&data->master->dev,
1153 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1155 /* Get the message from the queue and delete it from there. */
1156 data->current_msg = list_entry(data->queue.next, struct spi_message,
1159 list_del_init(&data->current_msg->queue);
1161 data->current_msg->status = 0;
1163 pch_spi_select_chip(data, data->current_msg->spi);
1165 spin_unlock(&data->lock);
1168 pch_spi_request_dma(data,
1169 data->current_msg->spi->bits_per_word);
1171 /* If we are already processing a message get the next
1172 transfer structure from the message otherwise retrieve
1173 the 1st transfer request from the message. */
1174 spin_lock(&data->lock);
1175 if (data->cur_trans == NULL) {
1177 list_entry(data->current_msg->transfers.next,
1178 struct spi_transfer, transfer_list);
1179 dev_dbg(&data->master->dev, "%s "
1180 ":Getting 1st transfer message\n", __func__);
1183 list_entry(data->cur_trans->transfer_list.next,
1184 struct spi_transfer, transfer_list);
1185 dev_dbg(&data->master->dev, "%s "
1186 ":Getting next transfer message\n", __func__);
1188 spin_unlock(&data->lock);
1190 if (data->use_dma) {
1191 pch_spi_handle_dma(data, &bpw);
1192 pch_spi_start_transfer(data);
1193 pch_spi_copy_rx_data_for_dma(data, bpw);
1195 pch_spi_set_tx(data, &bpw);
1196 pch_spi_set_ir(data);
1197 pch_spi_copy_rx_data(data, bpw);
1198 kfree(data->pkt_rx_buff);
1199 data->pkt_rx_buff = NULL;
1200 kfree(data->pkt_tx_buff);
1201 data->pkt_tx_buff = NULL;
1203 /* increment message count */
1204 data->current_msg->actual_length += data->cur_trans->len;
1206 dev_dbg(&data->master->dev,
1207 "%s:data->current_msg->actual_length=%d\n",
1208 __func__, data->current_msg->actual_length);
1210 /* check for delay */
1211 if (data->cur_trans->delay_usecs) {
1212 dev_dbg(&data->master->dev, "%s:"
1213 "delay in usec=%d\n", __func__,
1214 data->cur_trans->delay_usecs);
1215 udelay(data->cur_trans->delay_usecs);
1218 spin_lock(&data->lock);
1220 /* No more transfer in this message. */
1221 if ((data->cur_trans->transfer_list.next) ==
1222 &(data->current_msg->transfers)) {
1223 pch_spi_nomore_transfer(data);
1226 spin_unlock(&data->lock);
1228 } while (data->cur_trans != NULL);
1231 pch_spi_release_dma(data);
1234 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1235 struct pch_spi_data *data)
1237 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1239 /* free workqueue */
1240 if (data->wk != NULL) {
1241 destroy_workqueue(data->wk);
1243 dev_dbg(&board_dat->pdev->dev,
1244 "%s destroy_workqueue invoked successfully\n",
1249 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1250 struct pch_spi_data *data)
1254 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1256 /* create workqueue */
1257 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1259 dev_err(&board_dat->pdev->dev,
1260 "%s create_singlet hread_workqueue failed\n", __func__);
1265 /* reset PCH SPI h/w */
1266 pch_spi_reset(data->master);
1267 dev_dbg(&board_dat->pdev->dev,
1268 "%s pch_spi_reset invoked successfully\n", __func__);
1270 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1274 dev_err(&board_dat->pdev->dev,
1275 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1276 pch_spi_free_resources(board_dat, data);
1279 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1284 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1285 struct pch_spi_data *data)
1287 struct pch_spi_dma_ctrl *dma;
1290 if (dma->tx_buf_dma)
1291 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1292 dma->tx_buf_virt, dma->tx_buf_dma);
1293 if (dma->rx_buf_dma)
1294 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1295 dma->rx_buf_virt, dma->rx_buf_dma);
1299 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1300 struct pch_spi_data *data)
1302 struct pch_spi_dma_ctrl *dma;
1305 /* Get Consistent memory for Tx DMA */
1306 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1307 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1308 /* Get Consistent memory for Rx DMA */
1309 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1310 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1313 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1316 struct spi_master *master;
1317 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1318 struct pch_spi_data *data;
1320 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1322 master = spi_alloc_master(&board_dat->pdev->dev,
1323 sizeof(struct pch_spi_data));
1325 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1330 data = spi_master_get_devdata(master);
1331 data->master = master;
1333 platform_set_drvdata(plat_dev, data);
1335 /* baseaddress + address offset) */
1336 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1337 PCH_ADDRESS_SIZE * plat_dev->id;
1338 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1339 PCH_ADDRESS_SIZE * plat_dev->id;
1340 if (!data->io_remap_addr) {
1341 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1346 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1347 plat_dev->id, data->io_remap_addr);
1349 /* initialize members of SPI master */
1350 master->bus_num = -1;
1351 master->num_chipselect = PCH_MAX_CS;
1352 master->setup = pch_spi_setup;
1353 master->transfer = pch_spi_transfer;
1355 data->board_dat = board_dat;
1356 data->plat_dev = plat_dev;
1357 data->n_curnt_chip = 255;
1358 data->status = STATUS_RUNNING;
1359 data->ch = plat_dev->id;
1360 data->use_dma = use_dma;
1362 INIT_LIST_HEAD(&data->queue);
1363 spin_lock_init(&data->lock);
1364 INIT_WORK(&data->work, pch_spi_process_messages);
1365 init_waitqueue_head(&data->wait);
1367 ret = pch_spi_get_resources(board_dat, data);
1369 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1370 goto err_spi_get_resources;
1373 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1374 IRQF_SHARED, KBUILD_MODNAME, data);
1376 dev_err(&plat_dev->dev,
1377 "%s request_irq failed\n", __func__);
1378 goto err_request_irq;
1380 data->irq_reg_sts = true;
1382 pch_spi_set_master_mode(master);
1384 ret = spi_register_master(master);
1386 dev_err(&plat_dev->dev,
1387 "%s spi_register_master FAILED\n", __func__);
1388 goto err_spi_register_master;
1392 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1393 pch_alloc_dma_buf(board_dat, data);
1398 err_spi_register_master:
1399 free_irq(board_dat->pdev->irq, board_dat);
1401 pch_spi_free_resources(board_dat, data);
1402 err_spi_get_resources:
1403 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1405 spi_master_put(master);
1410 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1412 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1413 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1415 unsigned long flags;
1417 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1418 __func__, plat_dev->id, board_dat->pdev->irq);
1421 pch_free_dma_buf(board_dat, data);
1423 /* check for any pending messages; no action is taken if the queue
1424 * is still full; but at least we tried. Unload anyway */
1426 spin_lock_irqsave(&data->lock, flags);
1427 data->status = STATUS_EXITING;
1428 while ((list_empty(&data->queue) == 0) && --count) {
1429 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1431 spin_unlock_irqrestore(&data->lock, flags);
1432 msleep(PCH_SLEEP_TIME);
1433 spin_lock_irqsave(&data->lock, flags);
1435 spin_unlock_irqrestore(&data->lock, flags);
1437 pch_spi_free_resources(board_dat, data);
1438 /* disable interrupts & free IRQ */
1439 if (data->irq_reg_sts) {
1440 /* disable interrupts */
1441 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1442 data->irq_reg_sts = false;
1443 free_irq(board_dat->pdev->irq, data);
1446 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1447 spi_unregister_master(data->master);
1448 spi_master_put(data->master);
1449 platform_set_drvdata(plat_dev, NULL);
1454 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1458 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1459 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1461 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1464 dev_err(&pd_dev->dev,
1465 "%s pci_get_drvdata returned NULL\n", __func__);
1469 /* check if the current message is processed:
1470 Only after thats done the transfer will be suspended */
1472 while ((--count) > 0) {
1473 if (!(data->bcurrent_msg_processing))
1475 msleep(PCH_SLEEP_TIME);
1479 if (data->irq_reg_sts) {
1480 /* disable all interrupts */
1481 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1482 pch_spi_reset(data->master);
1483 free_irq(board_dat->pdev->irq, data);
1485 data->irq_reg_sts = false;
1486 dev_dbg(&pd_dev->dev,
1487 "%s free_irq invoked successfully.\n", __func__);
1493 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1495 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1496 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1500 dev_err(&pd_dev->dev,
1501 "%s pci_get_drvdata returned NULL\n", __func__);
1505 if (!data->irq_reg_sts) {
1507 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1508 IRQF_SHARED, KBUILD_MODNAME, data);
1510 dev_err(&pd_dev->dev,
1511 "%s request_irq failed\n", __func__);
1515 /* reset PCH SPI h/w */
1516 pch_spi_reset(data->master);
1517 pch_spi_set_master_mode(data->master);
1518 data->irq_reg_sts = true;
1523 #define pch_spi_pd_suspend NULL
1524 #define pch_spi_pd_resume NULL
1527 static struct platform_driver pch_spi_pd_driver = {
1530 .owner = THIS_MODULE,
1532 .probe = pch_spi_pd_probe,
1533 .remove = __devexit_p(pch_spi_pd_remove),
1534 .suspend = pch_spi_pd_suspend,
1535 .resume = pch_spi_pd_resume
1538 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1539 const struct pci_device_id *id)
1541 struct pch_spi_board_data *board_dat;
1542 struct platform_device *pd_dev = NULL;
1545 struct pch_pd_dev_save *pd_dev_save;
1547 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1549 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1553 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1555 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1560 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1562 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1563 goto pci_request_regions;
1566 board_dat->pdev = pdev;
1567 board_dat->num = id->driver_data;
1568 pd_dev_save->num = id->driver_data;
1569 pd_dev_save->board_dat = board_dat;
1571 retval = pci_enable_device(pdev);
1573 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1574 goto pci_enable_device;
1577 for (i = 0; i < board_dat->num; i++) {
1578 pd_dev = platform_device_alloc("pch-spi", i);
1580 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1581 goto err_platform_device;
1583 pd_dev_save->pd_save[i] = pd_dev;
1584 pd_dev->dev.parent = &pdev->dev;
1586 retval = platform_device_add_data(pd_dev, board_dat,
1587 sizeof(*board_dat));
1590 "platform_device_add_data failed\n");
1591 platform_device_put(pd_dev);
1592 goto err_platform_device;
1595 retval = platform_device_add(pd_dev);
1597 dev_err(&pdev->dev, "platform_device_add failed\n");
1598 platform_device_put(pd_dev);
1599 goto err_platform_device;
1603 pci_set_drvdata(pdev, pd_dev_save);
1607 err_platform_device:
1608 pci_disable_device(pdev);
1610 pci_release_regions(pdev);
1611 pci_request_regions:
1619 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1622 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1624 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1626 for (i = 0; i < pd_dev_save->num; i++)
1627 platform_device_unregister(pd_dev_save->pd_save[i]);
1629 pci_disable_device(pdev);
1630 pci_release_regions(pdev);
1631 kfree(pd_dev_save->board_dat);
1636 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1639 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1641 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1643 pd_dev_save->board_dat->suspend_sts = true;
1645 /* save config space */
1646 retval = pci_save_state(pdev);
1648 pci_enable_wake(pdev, PCI_D3hot, 0);
1649 pci_disable_device(pdev);
1650 pci_set_power_state(pdev, PCI_D3hot);
1652 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1658 static int pch_spi_resume(struct pci_dev *pdev)
1661 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1662 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1664 pci_set_power_state(pdev, PCI_D0);
1665 pci_restore_state(pdev);
1667 retval = pci_enable_device(pdev);
1670 "%s pci_enable_device failed\n", __func__);
1672 pci_enable_wake(pdev, PCI_D3hot, 0);
1674 /* set suspend status to false */
1675 pd_dev_save->board_dat->suspend_sts = false;
1681 #define pch_spi_suspend NULL
1682 #define pch_spi_resume NULL
1686 static struct pci_driver pch_spi_pcidev = {
1688 .id_table = pch_spi_pcidev_id,
1689 .probe = pch_spi_probe,
1690 .remove = pch_spi_remove,
1691 .suspend = pch_spi_suspend,
1692 .resume = pch_spi_resume,
1695 static int __init pch_spi_init(void)
1698 ret = platform_driver_register(&pch_spi_pd_driver);
1702 ret = pci_register_driver(&pch_spi_pcidev);
1708 module_init(pch_spi_init);
1710 static void __exit pch_spi_exit(void)
1712 pci_unregister_driver(&pch_spi_pcidev);
1713 platform_driver_unregister(&pch_spi_pd_driver);
1715 module_exit(pch_spi_exit);
1717 module_param(use_dma, int, 0644);
1718 MODULE_PARM_DESC(use_dma,
1719 "to use DMA for data transfers pass 1 else 0; default 1");
1721 MODULE_LICENSE("GPL");
1722 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");