2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
41 /* SPI Controller mode register definitions */
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45 #define SPMODE_DIV16 (1 << 27)
46 #define SPMODE_REV (1 << 26)
47 #define SPMODE_MS (1 << 25)
48 #define SPMODE_ENABLE (1 << 24)
49 #define SPMODE_LEN(x) ((x) << 20)
50 #define SPMODE_PM(x) ((x) << 16)
51 #define SPMODE_OP (1 << 14)
54 * Default for SPI Mode:
55 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
57 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
58 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
60 /* SPIE register values */
61 #define SPIE_NE 0x00000200 /* Not empty */
62 #define SPIE_NF 0x00000100 /* Not full */
64 /* SPIM register values */
65 #define SPIM_NE 0x00000200 /* Not empty */
66 #define SPIM_NF 0x00000100 /* Not full */
68 /* SPI Controller driver's private data. */
70 /* bitbang has to be first */
71 struct spi_bitbang bitbang;
72 struct completion done;
74 struct mpc83xx_spi_reg __iomem *base;
76 /* rx & tx bufs from the spi_transfer */
80 /* functions to deal with different sized buffers */
81 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
82 u32(*get_tx) (struct mpc83xx_spi *);
87 unsigned nsecs; /* (clock cycle time)/2 */
90 u32 rx_shift; /* RX data reg shift when in qe mode */
91 u32 tx_shift; /* TX data reg shift when in qe mode */
95 void (*activate_cs) (u8 cs, u8 polarity);
96 void (*deactivate_cs) (u8 cs, u8 polarity);
99 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
104 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
109 #define MPC83XX_SPI_RX_BUF(type) \
110 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
112 type * rx = mpc83xx_spi->rx; \
113 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
114 mpc83xx_spi->rx = rx; \
117 #define MPC83XX_SPI_TX_BUF(type) \
118 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
121 const type * tx = mpc83xx_spi->tx; \
124 data = *tx++ << mpc83xx_spi->tx_shift; \
125 mpc83xx_spi->tx = tx; \
129 MPC83XX_SPI_RX_BUF(u8)
130 MPC83XX_SPI_RX_BUF(u16)
131 MPC83XX_SPI_RX_BUF(u32)
132 MPC83XX_SPI_TX_BUF(u8)
133 MPC83XX_SPI_TX_BUF(u16)
134 MPC83XX_SPI_TX_BUF(u32)
136 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
138 struct mpc83xx_spi *mpc83xx_spi;
139 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
141 mpc83xx_spi = spi_master_get_devdata(spi->master);
143 if (value == BITBANG_CS_INACTIVE) {
144 if (mpc83xx_spi->deactivate_cs)
145 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
148 if (value == BITBANG_CS_ACTIVE) {
149 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
150 u32 len = spi->bits_per_word;
156 /* mask out bits we are going to set */
157 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
158 | SPMODE_LEN(0xF) | SPMODE_DIV16
159 | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);
161 if (spi->mode & SPI_CPHA)
162 regval |= SPMODE_CP_BEGIN_EDGECLK;
163 if (spi->mode & SPI_CPOL)
164 regval |= SPMODE_CI_INACTIVEHIGH;
165 if (!(spi->mode & SPI_LSB_FIRST))
166 regval |= SPMODE_REV;
167 if (spi->mode & SPI_LOOP)
168 regval |= SPMODE_LOOP;
170 regval |= SPMODE_LEN(len);
172 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
173 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
175 printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
176 "Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
177 spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
180 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
182 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
183 regval |= SPMODE_PM(pm);
186 /* Turn off SPI unit prior changing mode */
187 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
188 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
189 if (mpc83xx_spi->activate_cs)
190 mpc83xx_spi->activate_cs(spi->chip_select, pol);
195 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
197 struct mpc83xx_spi *mpc83xx_spi;
202 mpc83xx_spi = spi_master_get_devdata(spi->master);
205 bits_per_word = t->bits_per_word;
212 /* spi_transfer level calls that work per-word */
214 bits_per_word = spi->bits_per_word;
216 /* Make sure its a bit width we support [4..16, 32] */
217 if ((bits_per_word < 4)
218 || ((bits_per_word > 16) && (bits_per_word != 32)))
221 mpc83xx_spi->rx_shift = 0;
222 mpc83xx_spi->tx_shift = 0;
223 if (bits_per_word <= 8) {
224 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
225 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
226 if (mpc83xx_spi->qe_mode) {
227 mpc83xx_spi->rx_shift = 16;
228 mpc83xx_spi->tx_shift = 24;
230 } else if (bits_per_word <= 16) {
231 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
232 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
233 if (mpc83xx_spi->qe_mode) {
234 mpc83xx_spi->rx_shift = 16;
235 mpc83xx_spi->tx_shift = 16;
237 } else if (bits_per_word <= 32) {
238 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
239 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
243 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
244 mpc83xx_spi->tx_shift = 0;
245 if (bits_per_word <= 8)
246 mpc83xx_spi->rx_shift = 8;
248 mpc83xx_spi->rx_shift = 0;
251 /* nsecs = (clock period)/2 */
253 hz = spi->max_speed_hz;
254 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
255 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
258 if (bits_per_word == 32)
261 bits_per_word = bits_per_word - 1;
263 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
265 /* mask out bits we are going to set */
266 regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
267 regval |= SPMODE_LEN(bits_per_word);
268 if (!(spi->mode & SPI_LSB_FIRST))
269 regval |= SPMODE_REV;
271 /* Turn off SPI unit prior changing mode */
272 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
273 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
278 /* the spi->mode bits understood by this driver: */
279 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
280 | SPI_LSB_FIRST | SPI_LOOP)
282 static int mpc83xx_spi_setup(struct spi_device *spi)
284 struct spi_bitbang *bitbang;
285 struct mpc83xx_spi *mpc83xx_spi;
288 if (spi->mode & ~MODEBITS) {
289 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
290 spi->mode & ~MODEBITS);
294 if (!spi->max_speed_hz)
297 bitbang = spi_master_get_devdata(spi->master);
298 mpc83xx_spi = spi_master_get_devdata(spi->master);
300 if (!spi->bits_per_word)
301 spi->bits_per_word = 8;
303 retval = mpc83xx_spi_setup_transfer(spi, NULL);
307 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
308 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
309 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
311 /* NOTE we _need_ to call chipselect() early, ideally with adapter
312 * setup, unless the hardware defaults cooperate to avoid confusion
313 * between normal (active low) and inverted chipselects.
316 /* deselect chip (low or high) */
317 spin_lock(&bitbang->lock);
318 if (!bitbang->busy) {
319 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
320 ndelay(mpc83xx_spi->nsecs);
322 spin_unlock(&bitbang->lock);
327 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
329 struct mpc83xx_spi *mpc83xx_spi;
332 mpc83xx_spi = spi_master_get_devdata(spi->master);
334 mpc83xx_spi->tx = t->tx_buf;
335 mpc83xx_spi->rx = t->rx_buf;
336 mpc83xx_spi->count = t->len;
337 INIT_COMPLETION(mpc83xx_spi->done);
340 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
343 word = mpc83xx_spi->get_tx(mpc83xx_spi);
344 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
346 wait_for_completion(&mpc83xx_spi->done);
348 /* disable rx ints */
349 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
351 return t->len - mpc83xx_spi->count;
354 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
356 struct mpc83xx_spi *mpc83xx_spi = context_data;
358 irqreturn_t ret = IRQ_NONE;
360 /* Get interrupt events(tx/rx) */
361 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
363 /* We need handle RX first */
364 if (event & SPIE_NE) {
365 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
368 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
373 if ((event & SPIE_NF) == 0)
374 /* spin until TX is done */
376 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
380 mpc83xx_spi->count -= 1;
381 if (mpc83xx_spi->count) {
382 if (mpc83xx_spi->tx) {
383 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
384 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
388 complete(&mpc83xx_spi->done);
391 /* Clear the events */
392 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
397 static int __init mpc83xx_spi_probe(struct platform_device *dev)
399 struct spi_master *master;
400 struct mpc83xx_spi *mpc83xx_spi;
401 struct fsl_spi_platform_data *pdata;
406 /* Get resources(memory, IRQ) associated with the device */
407 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
409 if (master == NULL) {
414 platform_set_drvdata(dev, master);
415 pdata = dev->dev.platform_data;
422 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
427 mpc83xx_spi = spi_master_get_devdata(master);
428 mpc83xx_spi->bitbang.master = spi_master_get(master);
429 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
430 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
431 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
432 mpc83xx_spi->sysclk = pdata->sysclk;
433 mpc83xx_spi->activate_cs = pdata->activate_cs;
434 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
435 mpc83xx_spi->qe_mode = pdata->qe_mode;
436 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
437 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
439 mpc83xx_spi->rx_shift = 0;
440 mpc83xx_spi->tx_shift = 0;
441 if (mpc83xx_spi->qe_mode) {
442 mpc83xx_spi->rx_shift = 16;
443 mpc83xx_spi->tx_shift = 24;
446 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
447 init_completion(&mpc83xx_spi->done);
449 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
450 if (mpc83xx_spi->base == NULL) {
455 mpc83xx_spi->irq = platform_get_irq(dev, 0);
457 if (mpc83xx_spi->irq < 0) {
462 /* Register for SPI Interrupt */
463 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
464 0, "mpc83xx_spi", mpc83xx_spi);
469 master->bus_num = pdata->bus_num;
470 master->num_chipselect = pdata->max_chipselect;
472 /* SPI controller initializations */
473 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
474 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
475 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
476 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
478 /* Enable SPI interface */
479 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
483 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
485 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
491 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
492 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
497 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
499 iounmap(mpc83xx_spi->base);
501 spi_master_put(master);
508 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
510 struct mpc83xx_spi *mpc83xx_spi;
511 struct spi_master *master;
513 master = platform_get_drvdata(dev);
514 mpc83xx_spi = spi_master_get_devdata(master);
516 spi_bitbang_stop(&mpc83xx_spi->bitbang);
517 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
518 iounmap(mpc83xx_spi->base);
519 spi_master_put(mpc83xx_spi->bitbang.master);
524 static struct platform_driver mpc83xx_spi_driver = {
525 .probe = mpc83xx_spi_probe,
526 .remove = __devexit_p(mpc83xx_spi_remove),
528 .name = "mpc83xx_spi",
532 static int __init mpc83xx_spi_init(void)
534 return platform_driver_register(&mpc83xx_spi_driver);
537 static void __exit mpc83xx_spi_exit(void)
539 platform_driver_unregister(&mpc83xx_spi_driver);
542 module_init(mpc83xx_spi_init);
543 module_exit(mpc83xx_spi_exit);
545 MODULE_AUTHOR("Kumar Gala");
546 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
547 MODULE_LICENSE("GPL");