1 /* linux/drivers/spi/spi_s3c24xx.c
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
28 #include <plat/regs-spi.h>
32 * s3c24xx_spi_devstate - per device data
33 * @hz: Last frequency calculated for @sppre field.
34 * @mode: Last mode setting for the @spcon field.
35 * @spcon: Value to write to the SPCON register.
36 * @sppre: Value to write to the SPPRE register.
38 struct s3c24xx_spi_devstate {
46 /* bitbang has to be first */
47 struct spi_bitbang bitbang;
48 struct completion done;
55 void (*set_cs)(struct s3c2410_spi_info *spi,
59 const unsigned char *tx;
63 struct resource *ioarea;
64 struct spi_master *master;
65 struct spi_device *curdev;
67 struct s3c2410_spi_info *pdata;
70 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
71 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
73 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
75 return spi_master_get_devdata(sdev->master);
78 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
80 gpio_set_value(spi->pin_cs, pol);
83 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
86 struct s3c24xx_spi *hw = to_hw(spi);
87 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
89 /* change the chipselect state and the state of the spi engine clock */
92 case BITBANG_CS_INACTIVE:
93 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
94 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
97 case BITBANG_CS_ACTIVE:
98 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
99 hw->regs + S3C2410_SPCON);
100 hw->set_cs(hw->pdata, spi->chip_select, cspol);
105 static int s3c24xx_spi_update_state(struct spi_device *spi,
106 struct spi_transfer *t)
108 struct s3c24xx_spi *hw = to_hw(spi);
109 struct s3c24xx_spi_devstate *cs = spi->controller_state;
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
122 hz = spi->max_speed_hz;
125 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
129 if (spi->mode != cs->mode) {
130 u8 spcon = SPCON_DEFAULT;
132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
138 cs->mode = spi->mode;
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
159 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
166 ret = s3c24xx_spi_update_state(spi, t);
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
173 static int s3c24xx_spi_setup(struct spi_device *spi)
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
179 /* allocate settings on the first call */
181 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
183 dev_err(&spi->dev, "no memory for controller state\n");
187 cs->spcon = SPCON_DEFAULT;
189 spi->controller_state = cs;
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
197 spin_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
202 spin_unlock(&hw->bitbang.lock);
207 static void s3c24xx_spi_cleanup(struct spi_device *spi)
209 kfree(spi->controller_state);
212 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
214 return hw->tx ? hw->tx[count] : 0;
217 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
219 struct s3c24xx_spi *hw = to_hw(spi);
221 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
222 t->tx_buf, t->rx_buf, t->len);
229 init_completion(&hw->done);
231 /* send the first byte */
232 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
234 wait_for_completion(&hw->done);
239 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
241 struct s3c24xx_spi *hw = dev;
242 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
243 unsigned int count = hw->count;
245 if (spsta & S3C2410_SPSTA_DCOL) {
246 dev_dbg(hw->dev, "data-collision\n");
251 if (!(spsta & S3C2410_SPSTA_READY)) {
252 dev_dbg(hw->dev, "spi not ready for tx?\n");
260 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
265 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
273 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
275 /* for the moment, permanently enable the clock */
279 /* program defaults into the registers */
281 writeb(0xff, hw->regs + S3C2410_SPPRE);
282 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
283 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
286 if (hw->set_cs == s3c24xx_spi_gpiocs)
287 gpio_direction_output(hw->pdata->pin_cs, 1);
289 if (hw->pdata->gpio_setup)
290 hw->pdata->gpio_setup(hw->pdata, 1);
294 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
296 struct s3c2410_spi_info *pdata;
297 struct s3c24xx_spi *hw;
298 struct spi_master *master;
299 struct resource *res;
302 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
303 if (master == NULL) {
304 dev_err(&pdev->dev, "No memory for spi_master\n");
309 hw = spi_master_get_devdata(master);
310 memset(hw, 0, sizeof(struct s3c24xx_spi));
312 hw->master = spi_master_get(master);
313 hw->pdata = pdata = pdev->dev.platform_data;
314 hw->dev = &pdev->dev;
317 dev_err(&pdev->dev, "No platform data supplied\n");
322 platform_set_drvdata(pdev, hw);
323 init_completion(&hw->done);
325 /* setup the master state. */
327 /* the spi->mode bits understood by this driver: */
328 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
330 master->num_chipselect = hw->pdata->num_cs;
331 master->bus_num = pdata->bus_num;
333 /* setup the state for the bitbang driver */
335 hw->bitbang.master = hw->master;
336 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
337 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
338 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
340 hw->master->setup = s3c24xx_spi_setup;
341 hw->master->cleanup = s3c24xx_spi_cleanup;
343 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
345 /* find and map our resources */
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
354 hw->ioarea = request_mem_region(res->start, resource_size(res),
357 if (hw->ioarea == NULL) {
358 dev_err(&pdev->dev, "Cannot reserve region\n");
363 hw->regs = ioremap(res->start, resource_size(res));
364 if (hw->regs == NULL) {
365 dev_err(&pdev->dev, "Cannot map IO\n");
370 hw->irq = platform_get_irq(pdev, 0);
372 dev_err(&pdev->dev, "No IRQ specified\n");
377 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
379 dev_err(&pdev->dev, "Cannot claim IRQ\n");
383 hw->clk = clk_get(&pdev->dev, "spi");
384 if (IS_ERR(hw->clk)) {
385 dev_err(&pdev->dev, "No clock for device\n");
386 err = PTR_ERR(hw->clk);
390 /* setup any gpio we can */
392 if (!pdata->set_cs) {
393 if (pdata->pin_cs < 0) {
394 dev_err(&pdev->dev, "No chipselect pin\n");
398 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
400 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
404 hw->set_cs = s3c24xx_spi_gpiocs;
405 gpio_direction_output(pdata->pin_cs, 1);
407 hw->set_cs = pdata->set_cs;
409 s3c24xx_spi_initialsetup(hw);
411 /* register our spi controller */
413 err = spi_bitbang_start(&hw->bitbang);
415 dev_err(&pdev->dev, "Failed to register SPI master\n");
422 if (hw->set_cs == s3c24xx_spi_gpiocs)
423 gpio_free(pdata->pin_cs);
425 clk_disable(hw->clk);
429 free_irq(hw->irq, hw);
435 release_resource(hw->ioarea);
440 spi_master_put(hw->master);
446 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
448 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
450 platform_set_drvdata(dev, NULL);
452 spi_unregister_master(hw->master);
454 clk_disable(hw->clk);
457 free_irq(hw->irq, hw);
460 if (hw->set_cs == s3c24xx_spi_gpiocs)
461 gpio_free(hw->pdata->pin_cs);
463 release_resource(hw->ioarea);
466 spi_master_put(hw->master);
473 static int s3c24xx_spi_suspend(struct device *dev)
475 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
477 if (hw->pdata && hw->pdata->gpio_setup)
478 hw->pdata->gpio_setup(hw->pdata, 0);
480 clk_disable(hw->clk);
484 static int s3c24xx_spi_resume(struct device *dev)
486 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
488 s3c24xx_spi_initialsetup(hw);
492 static struct dev_pm_ops s3c24xx_spi_pmops = {
493 .suspend = s3c24xx_spi_suspend,
494 .resume = s3c24xx_spi_resume,
497 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
499 #define S3C24XX_SPI_PMOPS NULL
500 #endif /* CONFIG_PM */
502 MODULE_ALIAS("platform:s3c2410-spi");
503 static struct platform_driver s3c24xx_spi_driver = {
504 .remove = __exit_p(s3c24xx_spi_remove),
506 .name = "s3c2410-spi",
507 .owner = THIS_MODULE,
508 .pm = S3C24XX_SPI_PMOPS,
512 static int __init s3c24xx_spi_init(void)
514 return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
517 static void __exit s3c24xx_spi_exit(void)
519 platform_driver_unregister(&s3c24xx_spi_driver);
522 module_init(s3c24xx_spi_init);
523 module_exit(s3c24xx_spi_exit);
525 MODULE_DESCRIPTION("S3C24XX SPI Driver");
526 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
527 MODULE_LICENSE("GPL");