drivers/spi/ti_qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013, Texas Instruments, Incorporated
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <dm.h>
  15 #include <asm/gpio.h>
  16 #include <asm/omap_gpio.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/ti-common/ti-edma3.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* ti qpsi register bit masks */
  23 #define QSPI_TIMEOUT                    2000000
  24 #define QSPI_FCLK                       192000000
  25 #define QSPI_DRA7XX_FCLK                76800000
  26 #define QSPI_WLEN_MAX_BITS              128
  27 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  28 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  29 /* clock control */
  30 #define QSPI_CLK_EN                     BIT(31)
  31 #define QSPI_CLK_DIV_MAX                0xffff
  32 /* command */
  33 #define QSPI_EN_CS(n)                   (n << 28)
  34 #define QSPI_WLEN(n)                    ((n-1) << 19)
  35 #define QSPI_3_PIN                      BIT(18)
  36 #define QSPI_RD_SNGL                    BIT(16)
  37 #define QSPI_WR_SNGL                    (2 << 16)
  38 #define QSPI_INVAL                      (4 << 16)
  39 #define QSPI_RD_QUAD                    (7 << 16)
  40 /* device control */
  41 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  42 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  43 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  44 #define QSPI_CKPOL(n)                   (1 << (n*8))
  45 /* status */
  46 #define QSPI_WC                         BIT(1)
  47 #define QSPI_BUSY                       BIT(0)
  48 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  49 #define QSPI_XFER_DONE                  QSPI_WC
  50 #define MM_SWITCH                       0x01
  51 #define MEM_CS(cs)                      ((cs + 1) << 8)
  52 #define MEM_CS_UNSELECT                 0xfffff8ff
  53 #define MMAP_START_ADDR_DRA             0x5c000000
  54 #define MMAP_START_ADDR_AM43x           0x30000000
  55 #define CORE_CTRL_IO                    0x4a002558
  56
  57 #define QSPI_CMD_READ                   (0x3 << 0)
  58 #define QSPI_CMD_READ_DUAL              (0x6b << 0)
  59 #define QSPI_CMD_READ_QUAD              (0x6c << 0)
  60 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  61 #define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
  62 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  63 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  64 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  65 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  66 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  67 #define QSPI_CMD_WRITE                  (0x12 << 16)
  68 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  69
  70 /* ti qspi register set */
  71 struct ti_qspi_regs {
  72         u32 pid;
  73         u32 pad0[3];
  74         u32 sysconfig;
  75         u32 pad1[3];
  76         u32 int_stat_raw;
  77         u32 int_stat_en;
  78         u32 int_en_set;
  79         u32 int_en_ctlr;
  80         u32 intc_eoi;
  81         u32 pad2[3];
  82         u32 clk_ctrl;
  83         u32 dc;
  84         u32 cmd;
  85         u32 status;
  86         u32 data;
  87         u32 setup0;
  88         u32 setup1;
  89         u32 setup2;
  90         u32 setup3;
  91         u32 memswitch;
  92         u32 data1;
  93         u32 data2;
  94         u32 data3;
  95 };
  96
  97 /* ti qspi priv */
  98 struct ti_qspi_priv {
  99 #ifndef CONFIG_DM_SPI
 100         struct spi_slave slave;
 101 #else
 102         void *memory_map;
 103         uint max_hz;
 104         u32 num_cs;
 105 #endif
 106         struct ti_qspi_regs *base;
 107         void *ctrl_mod_mmap;
 108         ulong fclk;
 109         unsigned int mode;
 110         u32 cmd;
 111         u32 dc;
 112 };
 113
 114 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 115 {
 116         uint clk_div;
 117
 118         if (!hz)
 119                 clk_div = 0;
 120         else
 121                 clk_div = (priv->fclk / hz) - 1;
 122
 123         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 124
 125         /* disable SCLK */
 126         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 127                &priv->base->clk_ctrl);
 128
 129         /* assign clk_div values */
 130         if (clk_div < 0)
 131                 clk_div = 0;
 132         else if (clk_div > QSPI_CLK_DIV_MAX)
 133                 clk_div = QSPI_CLK_DIV_MAX;
 134
 135         /* enable SCLK */
 136         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 137 }
 138
 139 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 140 {
 141         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 142         /* dummy readl to ensure bus sync */
 143         readl(&priv->base->cmd);
 144 }
 145
 146 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
 147 {
 148         priv->dc = 0;
 149         if (mode & SPI_CPHA)
 150                 priv->dc |= QSPI_CKPHA(0);
 151         if (mode & SPI_CPOL)
 152                 priv->dc |= QSPI_CKPOL(0);
 153         if (mode & SPI_CS_HIGH)
 154                 priv->dc |= QSPI_CSPOL(0);
 155
 156         return 0;
 157 }
 158
 159 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
 160 {
 161         writel(priv->dc, &priv->base->dc);
 162         writel(0, &priv->base->cmd);
 163         writel(0, &priv->base->data);
 164
 165         priv->dc <<= cs * 8;
 166         writel(priv->dc, &priv->base->dc);
 167
 168         return 0;
 169 }
 170
 171 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
 172 {
 173         writel(0, &priv->base->dc);
 174         writel(0, &priv->base->cmd);
 175         writel(0, &priv->base->data);
 176 }
 177
 178 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 179 {
 180         u32 val;
 181
 182         val = readl(ctrl_mod_mmap);
 183         if (enable)
 184                 val |= MEM_CS(cs);
 185         else
 186                 val &= MEM_CS_UNSELECT;
 187         writel(val, ctrl_mod_mmap);
 188 }
 189
 190 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 191                         const void *dout, void *din, unsigned long flags,
 192                         u32 cs)
 193 {
 194         uint words = bitlen >> 3; /* fixed 8-bit word length */
 195         const uchar *txp = dout;
 196         uchar *rxp = din;
 197         uint status;
 198         int timeout;
 199
 200         /* Setup mmap flags */
 201         if (flags & SPI_XFER_MMAP) {
 202                 writel(MM_SWITCH, &priv->base->memswitch);
 203                 if (priv->ctrl_mod_mmap)
 204                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 205                 return 0;
 206         } else if (flags & SPI_XFER_MMAP_END) {
 207                 writel(~MM_SWITCH, &priv->base->memswitch);
 208                 if (priv->ctrl_mod_mmap)
 209                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 210                 return 0;
 211         }
 212
 213         if (bitlen == 0)
 214                 return -1;
 215
 216         if (bitlen % 8) {
 217                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 218                 return -1;
 219         }
 220
 221         /* Setup command reg */
 222         priv->cmd = 0;
 223         priv->cmd |= QSPI_WLEN(8);
 224         priv->cmd |= QSPI_EN_CS(cs);
 225         if (priv->mode & SPI_3WIRE)
 226                 priv->cmd |= QSPI_3_PIN;
 227         priv->cmd |= 0xfff;
 228
 229         while (words) {
 230                 u8 xfer_len = 0;
 231
 232                 if (txp) {
 233                         u32 cmd = priv->cmd;
 234
 235                         if (words >= QSPI_WLEN_MAX_BYTES) {
 236                                 u32 *txbuf = (u32 *)txp;
 237                                 u32 data;
 238
 239                                 data = cpu_to_be32(*txbuf++);
 240                                 writel(data, &priv->base->data3);
 241                                 data = cpu_to_be32(*txbuf++);
 242                                 writel(data, &priv->base->data2);
 243                                 data = cpu_to_be32(*txbuf++);
 244                                 writel(data, &priv->base->data1);
 245                                 data = cpu_to_be32(*txbuf++);
 246                                 writel(data, &priv->base->data);
 247                                 cmd &= ~QSPI_WLEN_MASK;
 248                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 249                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 250                         } else {
 251                                 writeb(*txp, &priv->base->data);
 252                                 xfer_len = 1;
 253                         }
 254                         debug("tx cmd %08x dc %08x\n",
 255                               cmd | QSPI_WR_SNGL, priv->dc);
 256                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 257                         status = readl(&priv->base->status);
 258                         timeout = QSPI_TIMEOUT;
 259                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 260                                 if (--timeout < 0) {
 261                                         printf("spi_xfer: TX timeout!\n");
 262                                         return -1;
 263                                 }
 264                                 status = readl(&priv->base->status);
 265                         }
 266                         txp += xfer_len;
 267                         debug("tx done, status %08x\n", status);
 268                 }
 269                 if (rxp) {
 270                         debug("rx cmd %08x dc %08x\n",
 271                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 272                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 273                         status = readl(&priv->base->status);
 274                         timeout = QSPI_TIMEOUT;
 275                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 276                                 if (--timeout < 0) {
 277                                         printf("spi_xfer: RX timeout!\n");
 278                                         return -1;
 279                                 }
 280                                 status = readl(&priv->base->status);
 281                         }
 282                         *rxp++ = readl(&priv->base->data);
 283                         xfer_len = 1;
 284                         debug("rx done, status %08x, read %02x\n",
 285                               status, *(rxp-1));
 286                 }
 287                 words -= xfer_len;
 288         }
 289
 290         /* Terminate frame */
 291         if (flags & SPI_XFER_END)
 292                 ti_qspi_cs_deactivate(priv);
 293
 294         return 0;
 295 }
 296
 297 /* TODO: control from sf layer to here through dm-spi */
 298 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 299 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 300 {
 301         unsigned int                    addr = (unsigned int) (data);
 302         unsigned int                    edma_slot_num = 1;
 303
 304         /* Invalidate the area, so no writeback into the RAM races with DMA */
 305         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 306
 307         /* enable edma3 clocks */
 308         enable_edma3_clocks();
 309
 310         /* Call edma3 api to do actual DMA transfer     */
 311         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 312
 313         /* disable edma3 clocks */
 314         disable_edma3_clocks();
 315
 316         *((unsigned int *)offset) += len;
 317 }
 318 #endif
 319
 320 #ifndef CONFIG_DM_SPI
 321
 322 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 323 {
 324         return container_of(slave, struct ti_qspi_priv, slave);
 325 }
 326
 327 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 328 {
 329         return 1;
 330 }
 331
 332 void spi_cs_activate(struct spi_slave *slave)
 333 {
 334         /* CS handled in xfer */
 335         return;
 336 }
 337
 338 void spi_cs_deactivate(struct spi_slave *slave)
 339 {
 340         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 341         ti_qspi_cs_deactivate(priv);
 342 }
 343
 344 void spi_init(void)
 345 {
 346         /* nothing to do */
 347 }
 348
 349 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
 350 {
 351         u32 memval = 0;
 352
 353 #ifdef CONFIG_QSPI_QUAD_SUPPORT
 354         struct spi_slave *slave = &priv->slave;
 355         memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
 356                         QSPI_SETUP0_NUM_D_BYTES_8_BITS |
 357                         QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
 358                         QSPI_NUM_DUMMY_BITS);
 359         slave->mode |= SPI_RX_QUAD;
 360 #else
 361         memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 362                         QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 363                         QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 364                         QSPI_NUM_DUMMY_BITS;
 365 #endif
 366
 367         writel(memval, &priv->base->setup0);
 368 }
 369
 370 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 371                                   unsigned int max_hz, unsigned int mode)
 372 {
 373         struct ti_qspi_priv *priv;
 374
 375 #ifdef CONFIG_AM43XX
 376         gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 377         gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 378 #endif
 379
 380         priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
 381         if (!priv) {
 382                 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
 383                 return NULL;
 384         }
 385
 386         priv->base = (struct ti_qspi_regs *)QSPI_BASE;
 387         priv->mode = mode;
 388 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 389         priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 390         priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
 391         priv->fclk = QSPI_DRA7XX_FCLK;
 392 #else
 393         priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
 394         priv->fclk = QSPI_FCLK;
 395 #endif
 396
 397         ti_spi_set_speed(priv, max_hz);
 398
 399 #ifdef CONFIG_TI_SPI_MMAP
 400         ti_spi_setup_spi_register(priv);
 401 #endif
 402
 403         return &priv->slave;
 404 }
 405
 406 void spi_free_slave(struct spi_slave *slave)
 407 {
 408         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 409         free(priv);
 410 }
 411
 412 int spi_claim_bus(struct spi_slave *slave)
 413 {
 414         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 415
 416         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 417         __ti_qspi_set_mode(priv, priv->mode);
 418         return __ti_qspi_claim_bus(priv, priv->slave.cs);
 419 }
 420 void spi_release_bus(struct spi_slave *slave)
 421 {
 422         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 423
 424         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 425         __ti_qspi_release_bus(priv);
 426 }
 427
 428 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 429              void *din, unsigned long flags)
 430 {
 431         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 432
 433         debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
 434               priv->slave.bus, priv->slave.cs, bitlen, flags);
 435         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
 436 }
 437
 438 #else /* CONFIG_DM_SPI */
 439
 440 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
 441                                       struct spi_slave *slave,
 442                                       bool enable)
 443 {
 444         u32 memval;
 445         u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
 446
 447         if (!enable) {
 448                 writel(0, &priv->base->setup0);
 449                 return;
 450         }
 451
 452         memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
 453
 454         switch (mode) {
 455         case SPI_RX_QUAD:
 456                 memval |= QSPI_CMD_READ_QUAD;
 457                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 458                 memval |= QSPI_SETUP0_READ_QUAD;
 459                 slave->mode |= SPI_RX_QUAD;
 460                 break;
 461         case SPI_RX_DUAL:
 462                 memval |= QSPI_CMD_READ_DUAL;
 463                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 464                 memval |= QSPI_SETUP0_READ_DUAL;
 465                 break;
 466         default:
 467                 memval |= QSPI_CMD_READ;
 468                 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
 469                 memval |= QSPI_SETUP0_READ_NORMAL;
 470                 break;
 471         }
 472
 473         writel(memval, &priv->base->setup0);
 474 }
 475
 476
 477 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
 478 {
 479         struct ti_qspi_priv *priv = dev_get_priv(bus);
 480
 481         ti_spi_set_speed(priv, max_hz);
 482
 483         return 0;
 484 }
 485
 486 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 487 {
 488         struct ti_qspi_priv *priv = dev_get_priv(bus);
 489         return __ti_qspi_set_mode(priv, mode);
 490 }
 491
 492 static int ti_qspi_claim_bus(struct udevice *dev)
 493 {
 494         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 495         struct spi_slave *slave = dev_get_parent_priv(dev);
 496         struct ti_qspi_priv *priv;
 497         struct udevice *bus;
 498
 499         bus = dev->parent;
 500         priv = dev_get_priv(bus);
 501
 502         if (slave_plat->cs > priv->num_cs) {
 503                 debug("invalid qspi chip select\n");
 504                 return -EINVAL;
 505         }
 506
 507         __ti_qspi_setup_memorymap(priv, slave, true);
 508
 509         return __ti_qspi_claim_bus(priv, slave_plat->cs);
 510 }
 511
 512 static int ti_qspi_release_bus(struct udevice *dev)
 513 {
 514         struct spi_slave *slave = dev_get_parent_priv(dev);
 515         struct ti_qspi_priv *priv;
 516         struct udevice *bus;
 517
 518         bus = dev->parent;
 519         priv = dev_get_priv(bus);
 520
 521         __ti_qspi_setup_memorymap(priv, slave, false);
 522         __ti_qspi_release_bus(priv);
 523
 524         return 0;
 525 }
 526
 527 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 528                         const void *dout, void *din, unsigned long flags)
 529 {
 530         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 531         struct ti_qspi_priv *priv;
 532         struct udevice *bus;
 533
 534         bus = dev->parent;
 535         priv = dev_get_priv(bus);
 536
 537         if (slave->cs > priv->num_cs) {
 538                 debug("invalid qspi chip select\n");
 539                 return -EINVAL;
 540         }
 541
 542         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
 543 }
 544
 545 static int ti_qspi_probe(struct udevice *bus)
 546 {
 547         struct ti_qspi_priv *priv = dev_get_priv(bus);
 548
 549         priv->fclk = dev_get_driver_data(bus);
 550
 551         return 0;
 552 }
 553
 554 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 555 {
 556         struct ti_qspi_priv *priv = dev_get_priv(bus);
 557         const void *blob = gd->fdt_blob;
 558         int node = bus->of_offset;
 559         fdt_addr_t addr;
 560         void *mmap;
 561
 562         priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
 563                                  MAP_NOCACHE);
 564         priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
 565                                        MAP_NOCACHE);
 566         addr = dev_get_addr_index(bus, 2);
 567         mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
 568         priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 569
 570         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 571         if (priv->max_hz < 0) {
 572                 debug("Error: Max frequency missing\n");
 573                 return -ENODEV;
 574         }
 575         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 576
 577         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 578               (int)priv->base, priv->max_hz);
 579
 580         return 0;
 581 }
 582
 583 static int ti_qspi_child_pre_probe(struct udevice *dev)
 584 {
 585         struct spi_slave *slave = dev_get_parent_priv(dev);
 586         struct udevice *bus = dev_get_parent(dev);
 587         struct ti_qspi_priv *priv = dev_get_priv(bus);
 588
 589         slave->memory_map = priv->memory_map;
 590         return 0;
 591 }
 592
 593 static const struct dm_spi_ops ti_qspi_ops = {
 594         .claim_bus      = ti_qspi_claim_bus,
 595         .release_bus    = ti_qspi_release_bus,
 596         .xfer           = ti_qspi_xfer,
 597         .set_speed      = ti_qspi_set_speed,
 598         .set_mode       = ti_qspi_set_mode,
 599 };
 600
 601 static const struct udevice_id ti_qspi_ids[] = {
 602         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 603         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 604         { }
 605 };
 606
 607 U_BOOT_DRIVER(ti_qspi) = {
 608         .name   = "ti_qspi",
 609         .id     = UCLASS_SPI,
 610         .of_match = ti_qspi_ids,
 611         .ops    = &ti_qspi_ops,
 612         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 613         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 614         .probe  = ti_qspi_probe,
 615         .child_pre_probe = ti_qspi_child_pre_probe,
 616 };
 617 #endif /* CONFIG_DM_SPI */