2 * Qualcomm SPMI bus driver
4 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 * Loosely based on Little Kernel driver
8 * SPDX-License-Identifier: BSD-3-Clause
16 #include <spmi/spmi.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
21 #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
23 #define PMIC_ARB_VERSION 0x0000
24 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
26 #define SPMI_REG_CMD0 0x0
27 #define SPMI_REG_CONFIG 0x4
28 #define SPMI_REG_STATUS 0x8
29 #define SPMI_REG_WDATA 0x10
30 #define SPMI_REG_RDATA 0x18
32 #define SPMI_CMD_OPCODE_SHIFT 27
33 #define SPMI_CMD_SLAVE_ID_SHIFT 20
34 #define SPMI_CMD_ADDR_SHIFT 12
35 #define SPMI_CMD_ADDR_OFFSET_SHIFT 4
36 #define SPMI_CMD_BYTE_CNT_SHIFT 0
38 #define SPMI_V2_CMD_OPCODE_SHIFT 27
39 #define SPMI_V2_CMD_ADDR_OFFSET_SHIFT 4
40 #define SPMI_V2_CMD_BYTE_CNT_SHIFT 0
42 #define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
43 #define SPMI_CMD_EXT_REG_READ_LONG 0x01
45 #define SPMI_STATUS_DONE 0x1
47 #define SPMI_MAX_CHANNELS 128
48 #define SPMI_MAX_SLAVES 16
49 #define SPMI_MAX_PERIPH 256
51 #define SPMI_READ_TIMEOUT 100
52 #define SPMI_WRITE_TIMEOUT 100
54 static int pmic_arb_ver;
56 static inline int pmic_arb_is_v1(void)
58 return pmic_arb_ver < PMIC_ARB_VERSION_V2_MIN;
61 struct msm_spmi_priv {
62 phys_addr_t arb_chnl; /* ARB channel mapping base */
63 phys_addr_t spmi_core; /* SPMI core */
64 phys_addr_t spmi_chnls; /* SPMI chnls */
65 phys_addr_t spmi_obs; /* SPMI observer */
66 /* SPMI channel map */
67 uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
70 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
73 struct msm_spmi_priv *priv = dev_get_priv(dev);
76 int timeout = SPMI_WRITE_TIMEOUT;
78 if (usid >= SPMI_MAX_SLAVES)
80 if (pid >= SPMI_MAX_PERIPH)
83 channel = priv->channel_map[usid][pid];
85 /* Disable IRQ mode for the current channel */
86 writel(0x0, priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
89 /* Write single byte */
90 writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
92 /* Prepare write command */
93 if (pmic_arb_is_v1()) {
94 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
95 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
96 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
97 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
98 reg |= 1; /* byte count */
100 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
101 reg |= ((off & 0xff) << SPMI_CMD_ADDR_OFFSET_SHIFT);
102 reg |= 0; /* byte count - 1 */
104 /* Send write command */
105 writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
107 /* Wait till CMD DONE status */
109 reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
114 } while (timeout-- > 0);
115 if (!(reg & SPMI_STATUS_DONE)) {
116 printf("SPMI write timed out\n");
120 if (reg ^ SPMI_STATUS_DONE) {
121 printf("SPMI write failure.\n");
128 static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
130 struct msm_spmi_priv *priv = dev_get_priv(dev);
134 if (usid >= SPMI_MAX_SLAVES)
136 if (pid >= SPMI_MAX_PERIPH)
139 channel = priv->channel_map[usid][pid];
141 /* Disable IRQ mode for the current channel*/
142 writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
144 /* Prepare read command */
145 if (pmic_arb_is_v1()) {
146 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
147 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
148 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
149 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
150 reg |= 1; /* byte count */
152 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
153 reg |= ((off & 0xff) << SPMI_CMD_ADDR_OFFSET_SHIFT);
154 reg |= 0; /* byte count - 1 */
158 writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
160 /* Wait till CMD DONE status */
163 reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
167 if (reg ^ SPMI_STATUS_DONE) {
168 printf("SPMI read failure.\n");
173 return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
174 SPMI_REG_RDATA) & 0xFF;
177 static struct dm_spmi_ops msm_spmi_ops = {
178 .read = msm_spmi_read,
179 .write = msm_spmi_write,
182 static int msm_spmi_probe(struct udevice *dev)
184 struct udevice *parent = dev->parent;
185 struct msm_spmi_priv *priv = dev_get_priv(dev);
188 priv->spmi_core = dev_get_addr(dev);
189 priv->spmi_chnls = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
194 priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
196 dev->of_offset, "reg",
198 if (priv->spmi_core == FDT_ADDR_T_NONE ||
199 priv->spmi_chnls == FDT_ADDR_T_NONE ||
200 priv->spmi_obs == FDT_ADDR_T_NONE)
203 priv->arb_chnl = priv->spmi_core + 0x800;
205 /* Scan peripherals connected to each SPMI channel */
206 for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
207 uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
208 uint8_t slave_id = (periph & 0xf0000) >> 16;
209 uint8_t pid = (periph & 0xff00) >> 8;
211 priv->channel_map[slave_id][pid] = i;
213 pmic_arb_ver = readl(priv->spmi_core + PMIC_ARB_VERSION);
214 printf("PMIC: PM8916 ARB version %d\n", pmic_arb_is_v1() ? 1 : 2);
218 static const struct udevice_id msm_spmi_ids[] = {
219 { .compatible = "qcom,spmi-pmic-arb" },
223 U_BOOT_DRIVER(msm_spmi) = {
226 .of_match = msm_spmi_ids,
227 .ops = &msm_spmi_ops,
228 .probe = msm_spmi_probe,
229 .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),