2 * Sonics Silicon Backplane
3 * Broadcom MIPS core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/serial.h>
15 #include <linux/serial_core.h>
16 #include <linux/serial_reg.h>
17 #include <linux/time.h>
19 #include "ssb_private.h"
21 static const char *part_probes[] = { "bcm47xxpart", NULL };
23 static struct physmap_flash_data ssb_pflash_data = {
24 .part_probe_types = part_probes,
27 static struct resource ssb_pflash_resource = {
29 .flags = IORESOURCE_MEM,
32 struct platform_device ssb_pflash_dev = {
33 .name = "physmap-flash",
35 .platform_data = &ssb_pflash_data,
37 .resource = &ssb_pflash_resource,
41 static inline u32 mips_read32(struct ssb_mipscore *mcore,
44 return ssb_read32(mcore->dev, offset);
47 static inline void mips_write32(struct ssb_mipscore *mcore,
51 ssb_write32(mcore->dev, offset, value);
54 static const u32 ipsflag_irq_mask[] = {
62 static const u32 ipsflag_irq_shift[] = {
64 SSB_IPSFLAG_IRQ1_SHIFT,
65 SSB_IPSFLAG_IRQ2_SHIFT,
66 SSB_IPSFLAG_IRQ3_SHIFT,
67 SSB_IPSFLAG_IRQ4_SHIFT,
70 static inline u32 ssb_irqflag(struct ssb_device *dev)
72 u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
74 return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
76 /* not irq supported */
80 static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
82 struct ssb_bus *bus = rdev->bus;
84 for (i = 0; i < bus->nr_devices; i++) {
85 struct ssb_device *dev;
86 dev = &(bus->devices[i]);
87 if (ssb_irqflag(dev) == irqflag)
93 /* Get the MIPS IRQ assignment for a specified device.
94 * If unassigned, 0 is returned.
95 * If disabled, 5 is returned.
96 * If not supported, 6 is returned.
98 unsigned int ssb_mips_irq(struct ssb_device *dev)
100 struct ssb_bus *bus = dev->bus;
101 struct ssb_device *mdev = bus->mipscore.dev;
107 irqflag = ssb_irqflag(dev);
110 ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
111 for (irq = 1; irq <= 4; irq++) {
112 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
117 if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
124 static void clear_irq(struct ssb_bus *bus, unsigned int irq)
126 struct ssb_device *dev = bus->mipscore.dev;
128 /* Clear the IRQ in the MIPScore backplane registers */
130 ssb_write32(dev, SSB_INTVEC, 0);
132 ssb_write32(dev, SSB_IPSFLAG,
133 ssb_read32(dev, SSB_IPSFLAG) |
134 ipsflag_irq_mask[irq]);
138 static void set_irq(struct ssb_device *dev, unsigned int irq)
140 unsigned int oldirq = ssb_mips_irq(dev);
141 struct ssb_bus *bus = dev->bus;
142 struct ssb_device *mdev = bus->mipscore.dev;
143 u32 irqflag = ssb_irqflag(dev);
149 /* clear the old irq */
151 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
152 else if (oldirq != 5)
153 clear_irq(bus, oldirq);
155 /* assign the new one */
157 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
159 u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
160 if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
161 u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
162 struct ssb_device *olddev = find_device(dev, oldipsflag);
166 irqflag <<= ipsflag_irq_shift[irq];
167 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
168 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
170 ssb_dprintk(KERN_INFO PFX
171 "set_irq: core 0x%04x, irq %d => %d\n",
172 dev->id.coreid, oldirq+2, irq+2);
175 static void print_irq(struct ssb_device *dev, unsigned int irq)
178 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
179 ssb_dprintk(KERN_INFO PFX
180 "core 0x%04x, irq :", dev->id.coreid);
181 for (i = 0; i <= 6; i++) {
182 ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
187 static void dump_irq(struct ssb_bus *bus)
190 for (i = 0; i < bus->nr_devices; i++) {
191 struct ssb_device *dev;
192 dev = &(bus->devices[i]);
193 print_irq(dev, ssb_mips_irq(dev));
197 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
199 struct ssb_bus *bus = mcore->dev->bus;
201 if (ssb_extif_available(&bus->extif))
202 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
203 else if (ssb_chipco_available(&bus->chipco))
204 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
206 mcore->nr_serial_ports = 0;
209 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
211 struct ssb_bus *bus = mcore->dev->bus;
212 struct ssb_pflash *pflash = &mcore->pflash;
214 /* When there is no chipcommon on the bus there is 4MB flash */
215 if (!ssb_chipco_available(&bus->chipco)) {
216 pflash->present = true;
217 pflash->buswidth = 2;
218 pflash->window = SSB_FLASH1;
219 pflash->window_size = SSB_FLASH1_SZ;
223 /* There is ChipCommon, so use it to read info about flash */
224 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
225 case SSB_CHIPCO_FLASHT_STSER:
226 case SSB_CHIPCO_FLASHT_ATSER:
227 pr_debug("Found serial flash\n");
228 ssb_sflash_init(&bus->chipco);
230 case SSB_CHIPCO_FLASHT_PARA:
231 pr_debug("Found parallel flash\n");
232 pflash->present = true;
233 pflash->window = SSB_FLASH2;
234 pflash->window_size = SSB_FLASH2_SZ;
235 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
236 & SSB_CHIPCO_CFG_DS16) == 0)
237 pflash->buswidth = 1;
239 pflash->buswidth = 2;
244 if (pflash->present) {
245 ssb_pflash_data.width = pflash->buswidth;
246 ssb_pflash_resource.start = pflash->window;
247 ssb_pflash_resource.end = pflash->window + pflash->window_size;
251 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
253 struct ssb_bus *bus = mcore->dev->bus;
254 u32 pll_type, n, m, rate = 0;
256 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
257 return ssb_pmu_get_cpu_clock(&bus->chipco);
259 if (ssb_extif_available(&bus->extif)) {
260 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
261 } else if (ssb_chipco_available(&bus->chipco)) {
262 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
266 if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
269 rate = ssb_calc_clock_rate(pll_type, n, m);
272 if (pll_type == SSB_PLLTYPE_6) {
279 void ssb_mipscore_init(struct ssb_mipscore *mcore)
282 struct ssb_device *dev;
283 unsigned long hz, ns;
287 return; /* We don't have a MIPS core */
289 ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
291 bus = mcore->dev->bus;
292 hz = ssb_clockspeed(bus);
295 ns = 1000000000 / hz;
297 if (ssb_extif_available(&bus->extif))
298 ssb_extif_timing_init(&bus->extif, ns);
299 else if (ssb_chipco_available(&bus->chipco))
300 ssb_chipco_timing_init(&bus->chipco, ns);
302 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
303 for (irq = 2, i = 0; i < bus->nr_devices; i++) {
305 dev = &(bus->devices[i]);
306 mips_irq = ssb_mips_irq(dev);
310 dev->irq = mips_irq + 2;
313 switch (dev->id.coreid) {
314 case SSB_DEV_USB11_HOST:
315 /* shouldn't need a separate irq line for non-4710, most of them have a proper
316 * external usb controller on the pci */
317 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
322 case SSB_DEV_ETHERNET:
323 case SSB_DEV_ETHERNET_GBIT:
325 case SSB_DEV_USB20_HOST:
326 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
337 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
340 ssb_mips_serial_init(mcore);
341 ssb_mips_flash_detect(mcore);