2 * Sonics Silicon Backplane
3 * Broadcom MIPS core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/serial.h>
15 #include <linux/serial_core.h>
16 #include <linux/serial_reg.h>
17 #include <linux/time.h>
19 #include "ssb_private.h"
21 static const char * const part_probes[] = { "bcm47xxpart", NULL };
23 static struct physmap_flash_data ssb_pflash_data = {
24 .part_probe_types = part_probes,
27 static struct resource ssb_pflash_resource = {
29 .flags = IORESOURCE_MEM,
32 struct platform_device ssb_pflash_dev = {
33 .name = "physmap-flash",
35 .platform_data = &ssb_pflash_data,
37 .resource = &ssb_pflash_resource,
41 static inline u32 mips_read32(struct ssb_mipscore *mcore,
44 return ssb_read32(mcore->dev, offset);
47 static inline void mips_write32(struct ssb_mipscore *mcore,
51 ssb_write32(mcore->dev, offset, value);
54 static const u32 ipsflag_irq_mask[] = {
62 static const u32 ipsflag_irq_shift[] = {
64 SSB_IPSFLAG_IRQ1_SHIFT,
65 SSB_IPSFLAG_IRQ2_SHIFT,
66 SSB_IPSFLAG_IRQ3_SHIFT,
67 SSB_IPSFLAG_IRQ4_SHIFT,
70 static inline u32 ssb_irqflag(struct ssb_device *dev)
72 u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
74 return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
76 /* not irq supported */
80 static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
82 struct ssb_bus *bus = rdev->bus;
84 for (i = 0; i < bus->nr_devices; i++) {
85 struct ssb_device *dev;
86 dev = &(bus->devices[i]);
87 if (ssb_irqflag(dev) == irqflag)
93 /* Get the MIPS IRQ assignment for a specified device.
94 * If unassigned, 0 is returned.
95 * If disabled, 5 is returned.
96 * If not supported, 6 is returned.
98 unsigned int ssb_mips_irq(struct ssb_device *dev)
100 struct ssb_bus *bus = dev->bus;
101 struct ssb_device *mdev = bus->mipscore.dev;
107 irqflag = ssb_irqflag(dev);
110 ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
111 for (irq = 1; irq <= 4; irq++) {
112 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
117 if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
124 static void clear_irq(struct ssb_bus *bus, unsigned int irq)
126 struct ssb_device *dev = bus->mipscore.dev;
128 /* Clear the IRQ in the MIPScore backplane registers */
130 ssb_write32(dev, SSB_INTVEC, 0);
132 ssb_write32(dev, SSB_IPSFLAG,
133 ssb_read32(dev, SSB_IPSFLAG) |
134 ipsflag_irq_mask[irq]);
138 static void set_irq(struct ssb_device *dev, unsigned int irq)
140 unsigned int oldirq = ssb_mips_irq(dev);
141 struct ssb_bus *bus = dev->bus;
142 struct ssb_device *mdev = bus->mipscore.dev;
143 u32 irqflag = ssb_irqflag(dev);
149 /* clear the old irq */
151 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
152 else if (oldirq != 5)
153 clear_irq(bus, oldirq);
155 /* assign the new one */
157 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
159 u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
160 if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
161 u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
162 struct ssb_device *olddev = find_device(dev, oldipsflag);
166 irqflag <<= ipsflag_irq_shift[irq];
167 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
168 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
170 ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
171 dev->id.coreid, oldirq+2, irq+2);
174 static void print_irq(struct ssb_device *dev, unsigned int irq)
176 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
177 ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
179 irq_name[0], irq == 0 ? "*" : " ",
180 irq_name[1], irq == 1 ? "*" : " ",
181 irq_name[2], irq == 2 ? "*" : " ",
182 irq_name[3], irq == 3 ? "*" : " ",
183 irq_name[4], irq == 4 ? "*" : " ",
184 irq_name[5], irq == 5 ? "*" : " ",
185 irq_name[6], irq == 6 ? "*" : " ");
188 static void dump_irq(struct ssb_bus *bus)
191 for (i = 0; i < bus->nr_devices; i++) {
192 struct ssb_device *dev;
193 dev = &(bus->devices[i]);
194 print_irq(dev, ssb_mips_irq(dev));
198 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
200 struct ssb_bus *bus = mcore->dev->bus;
202 if (ssb_extif_available(&bus->extif))
203 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
204 else if (ssb_chipco_available(&bus->chipco))
205 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
207 mcore->nr_serial_ports = 0;
210 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
212 struct ssb_bus *bus = mcore->dev->bus;
213 struct ssb_pflash *pflash = &mcore->pflash;
215 /* When there is no chipcommon on the bus there is 4MB flash */
216 if (!ssb_chipco_available(&bus->chipco)) {
217 pflash->present = true;
218 pflash->buswidth = 2;
219 pflash->window = SSB_FLASH1;
220 pflash->window_size = SSB_FLASH1_SZ;
224 /* There is ChipCommon, so use it to read info about flash */
225 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
226 case SSB_CHIPCO_FLASHT_STSER:
227 case SSB_CHIPCO_FLASHT_ATSER:
228 pr_debug("Found serial flash\n");
229 ssb_sflash_init(&bus->chipco);
231 case SSB_CHIPCO_FLASHT_PARA:
232 pr_debug("Found parallel flash\n");
233 pflash->present = true;
234 pflash->window = SSB_FLASH2;
235 pflash->window_size = SSB_FLASH2_SZ;
236 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
237 & SSB_CHIPCO_CFG_DS16) == 0)
238 pflash->buswidth = 1;
240 pflash->buswidth = 2;
245 if (pflash->present) {
246 ssb_pflash_data.width = pflash->buswidth;
247 ssb_pflash_resource.start = pflash->window;
248 ssb_pflash_resource.end = pflash->window + pflash->window_size;
252 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
254 struct ssb_bus *bus = mcore->dev->bus;
255 u32 pll_type, n, m, rate = 0;
257 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
258 return ssb_pmu_get_cpu_clock(&bus->chipco);
260 if (ssb_extif_available(&bus->extif)) {
261 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
262 } else if (ssb_chipco_available(&bus->chipco)) {
263 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
267 if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
270 rate = ssb_calc_clock_rate(pll_type, n, m);
273 if (pll_type == SSB_PLLTYPE_6) {
280 void ssb_mipscore_init(struct ssb_mipscore *mcore)
283 struct ssb_device *dev;
284 unsigned long hz, ns;
288 return; /* We don't have a MIPS core */
290 ssb_dbg("Initializing MIPS core...\n");
292 bus = mcore->dev->bus;
293 hz = ssb_clockspeed(bus);
296 ns = 1000000000 / hz;
298 if (ssb_extif_available(&bus->extif))
299 ssb_extif_timing_init(&bus->extif, ns);
300 else if (ssb_chipco_available(&bus->chipco))
301 ssb_chipco_timing_init(&bus->chipco, ns);
303 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
304 for (irq = 2, i = 0; i < bus->nr_devices; i++) {
306 dev = &(bus->devices[i]);
307 mips_irq = ssb_mips_irq(dev);
311 dev->irq = mips_irq + 2;
314 switch (dev->id.coreid) {
315 case SSB_DEV_USB11_HOST:
316 /* shouldn't need a separate irq line for non-4710, most of them have a proper
317 * external usb controller on the pci */
318 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
323 case SSB_DEV_ETHERNET:
324 case SSB_DEV_ETHERNET_GBIT:
326 case SSB_DEV_USB20_HOST:
327 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
338 ssb_dbg("after irq reconfiguration\n");
341 ssb_mips_serial_init(mcore);
342 ssb_mips_flash_detect(mcore);