2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
14 #include <linux/ssb/ssb_embedded.h>
16 #include "ssb_private.h"
18 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
19 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
20 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
21 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
22 u8 address, u16 data);
25 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
27 return ssb_read32(pc->dev, offset);
31 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
33 ssb_write32(pc->dev, offset, value);
37 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
39 return ssb_read16(pc->dev, offset);
43 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
45 ssb_write16(pc->dev, offset, value);
48 /**************************************************
49 * Code for hostmode operation.
50 **************************************************/
52 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
54 #include <asm/paccess.h>
55 /* Probe a 32bit value on the bus and catch bus exceptions.
56 * Returns nonzero on a bus exception.
57 * This is MIPS specific */
58 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
60 /* Assume one-hot slot wiring */
61 #define SSB_PCI_SLOT_MAX 16
63 /* Global lock is OK, as we won't have more than one extpci anyway. */
64 static DEFINE_SPINLOCK(cfgspace_lock);
65 /* Core to access the external PCI config space. Can only have one. */
66 static struct ssb_pcicore *extpci_core;
69 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
70 unsigned int bus, unsigned int dev,
71 unsigned int func, unsigned int off)
76 /* We do only have one cardbus device behind the bridge. */
77 if (pc->cardbusmode && (dev >= 1))
81 /* Type 0 transaction */
82 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
84 /* Slide the window */
85 tmp = SSB_PCICORE_SBTOPCI_CFG0;
86 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
87 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
88 /* Calculate the address */
90 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
94 /* Type 1 transaction */
95 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
96 SSB_PCICORE_SBTOPCI_CFG1);
97 /* Calculate the address */
108 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
109 unsigned int bus, unsigned int dev,
110 unsigned int func, unsigned int off,
117 SSB_WARN_ON(!pc->hostmode);
118 if (unlikely(len != 1 && len != 2 && len != 4))
120 addr = get_cfgspace_addr(pc, bus, dev, func, off);
124 mmio = ioremap_nocache(addr, len);
128 if (mips_busprobe32(val, mmio)) {
134 val >>= (8 * (off & 3));
138 *((u8 *)buf) = (u8)val;
141 *((u16 *)buf) = (u16)val;
144 *((u32 *)buf) = (u32)val;
154 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
155 unsigned int bus, unsigned int dev,
156 unsigned int func, unsigned int off,
157 const void *buf, int len)
163 SSB_WARN_ON(!pc->hostmode);
164 if (unlikely(len != 1 && len != 2 && len != 4))
166 addr = get_cfgspace_addr(pc, bus, dev, func, off);
170 mmio = ioremap_nocache(addr, len);
174 if (mips_busprobe32(val, mmio)) {
182 val &= ~(0xFF << (8 * (off & 3)));
183 val |= *((const u8 *)buf) << (8 * (off & 3));
187 val &= ~(0xFFFF << (8 * (off & 3)));
188 val |= *((const u16 *)buf) << (8 * (off & 3));
191 val = *((const u32 *)buf);
203 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
204 int reg, int size, u32 *val)
209 spin_lock_irqsave(&cfgspace_lock, flags);
210 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
211 PCI_FUNC(devfn), reg, val, size);
212 spin_unlock_irqrestore(&cfgspace_lock, flags);
214 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
217 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
218 int reg, int size, u32 val)
223 spin_lock_irqsave(&cfgspace_lock, flags);
224 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
225 PCI_FUNC(devfn), reg, &val, size);
226 spin_unlock_irqrestore(&cfgspace_lock, flags);
228 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
231 static struct pci_ops ssb_pcicore_pciops = {
232 .read = ssb_pcicore_read_config,
233 .write = ssb_pcicore_write_config,
236 static struct resource ssb_pcicore_mem_resource = {
237 .name = "SSB PCIcore external memory",
238 .start = SSB_PCI_DMA,
239 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
240 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
243 static struct resource ssb_pcicore_io_resource = {
244 .name = "SSB PCIcore external I/O",
247 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
250 static struct pci_controller ssb_pcicore_controller = {
251 .pci_ops = &ssb_pcicore_pciops,
252 .io_resource = &ssb_pcicore_io_resource,
253 .mem_resource = &ssb_pcicore_mem_resource,
256 /* This function is called when doing a pci_enable_device().
257 * We must first check if the device is a device on the PCI-core bridge. */
258 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
260 if (d->bus->ops != &ssb_pcicore_pciops) {
261 /* This is not a device on the PCI-core bridge. */
265 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
268 /* Fix up interrupt lines */
269 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
270 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
275 /* Early PCI fixup for a device on the PCI-core bridge. */
276 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
280 if (dev->bus->ops != &ssb_pcicore_pciops) {
281 /* This is not a device on the PCI-core bridge. */
284 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
287 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
289 /* Enable PCI bridge bus mastering and memory space */
291 if (pcibios_enable_device(dev, ~0) < 0) {
292 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
296 /* Enable PCI bridge BAR1 prefetch and burst */
297 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
299 /* Make sure our latency is high enough to handle the devices behind us */
301 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
303 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
305 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
307 /* PCI device IRQ mapping. */
308 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
310 if (dev->bus->ops != &ssb_pcicore_pciops) {
311 /* This is not a device on the PCI-core bridge. */
314 return ssb_mips_irq(extpci_core->dev) + 2;
317 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
321 if (WARN_ON(extpci_core))
325 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
326 /* Reset devices on the external PCI bus */
327 val = SSB_PCICORE_CTL_RST_OE;
328 val |= SSB_PCICORE_CTL_CLK_OE;
329 pcicore_write32(pc, SSB_PCICORE_CTL, val);
330 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
331 pcicore_write32(pc, SSB_PCICORE_CTL, val);
332 udelay(150); /* Assertion time demanded by the PCI standard */
333 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
334 pcicore_write32(pc, SSB_PCICORE_CTL, val);
335 val = SSB_PCICORE_ARBCTL_INTERN;
336 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
337 udelay(1); /* Assertion time demanded by the PCI standard */
339 if (pc->dev->bus->has_cardbus_slot) {
340 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
342 /* GPIO 1 resets the bridge */
343 ssb_gpio_out(pc->dev->bus, 1, 1);
344 ssb_gpio_outen(pc->dev->bus, 1, 1);
345 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
346 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
350 /* 64MB I/O window */
351 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
352 SSB_PCICORE_SBTOPCI_IO);
353 /* 64MB config space */
354 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
355 SSB_PCICORE_SBTOPCI_CFG0);
356 /* 1GB memory window */
357 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
358 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
360 /* Enable PCI bridge BAR0 prefetch and burst */
361 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
362 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
363 /* Clear error conditions */
365 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
367 /* Enable PCI interrupts */
368 pcicore_write32(pc, SSB_PCICORE_IMASK,
369 SSB_PCICORE_IMASK_INTA);
371 /* Ok, ready to run, register it to the system.
372 * The following needs change, if we want to port hostmode
373 * to non-MIPS platform. */
374 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
375 set_io_port_base(ssb_pcicore_controller.io_map_base);
376 /* Give some time to the PCI controller to configure itself with the new
377 * values. Not waiting at this point causes crashes of the machine. */
379 register_pci_controller(&ssb_pcicore_controller);
382 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
384 struct ssb_bus *bus = pc->dev->bus;
388 chipid_top = (bus->chip_id & 0xFF00);
389 if (chipid_top != 0x4700 &&
390 chipid_top != 0x5300)
393 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
396 /* The 200-pin BCM4712 package does not bond out PCI. Even when
397 * PCI is bonded out, some boards may leave the pins floating. */
398 if (bus->chip_id == 0x4712) {
399 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
401 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
404 if (bus->chip_id == 0x5350)
407 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
409 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
411 /**************************************************
413 **************************************************/
415 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
417 return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
420 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
422 const u8 serdes_pll_device = 0x1D;
423 const u8 serdes_rx_device = 0x1F;
426 ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
427 ssb_pcicore_polarity_workaround(pc));
428 tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
430 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
433 /**************************************************
434 * Generic and Clientmode operation code.
435 **************************************************/
437 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
439 /* Disable PCI interrupts. */
440 ssb_write32(pc->dev, SSB_INTVEC, 0);
443 void ssb_pcicore_init(struct ssb_pcicore *pc)
445 struct ssb_device *dev = pc->dev;
449 if (!ssb_device_is_enabled(dev))
450 ssb_device_enable(dev, 0);
452 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
453 pc->hostmode = pcicore_is_in_hostmode(pc);
455 ssb_pcicore_init_hostmode(pc);
456 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
458 ssb_pcicore_init_clientmode(pc);
460 ssb_pcicore_serdes_workaround(pc);
463 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
465 pcicore_write32(pc, 0x130, address);
466 return pcicore_read32(pc, 0x134);
469 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
471 pcicore_write32(pc, 0x130, address);
472 pcicore_write32(pc, 0x134, data);
475 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
477 const u16 mdio_control = 0x128;
478 const u16 mdio_data = 0x12C;
482 v = (1 << 30); /* Start of Transaction */
483 v |= (1 << 28); /* Write Transaction */
484 v |= (1 << 17); /* Turnaround */
487 pcicore_write32(pc, mdio_data, v);
490 for (i = 0; i < 200; i++) {
491 v = pcicore_read32(pc, mdio_control);
492 if (v & 0x100 /* Trans complete */)
498 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
500 const u16 mdio_control = 0x128;
501 const u16 mdio_data = 0x12C;
502 int max_retries = 10;
507 v = 0x80; /* Enable Preamble Sequence */
508 v |= 0x2; /* MDIO Clock Divisor */
509 pcicore_write32(pc, mdio_control, v);
511 if (pc->dev->id.revision >= 10) {
513 ssb_pcie_mdio_set_phy(pc, device);
516 v = (1 << 30); /* Start of Transaction */
517 v |= (1 << 29); /* Read Transaction */
518 v |= (1 << 17); /* Turnaround */
519 if (pc->dev->id.revision < 10)
520 v |= (u32)device << 22;
521 v |= (u32)address << 18;
522 pcicore_write32(pc, mdio_data, v);
523 /* Wait for the device to complete the transaction */
525 for (i = 0; i < 200; i++) {
526 v = pcicore_read32(pc, mdio_control);
527 if (v & 0x100 /* Trans complete */) {
529 ret = pcicore_read32(pc, mdio_data);
534 pcicore_write32(pc, mdio_control, 0);
538 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
539 u8 address, u16 data)
541 const u16 mdio_control = 0x128;
542 const u16 mdio_data = 0x12C;
543 int max_retries = 10;
547 v = 0x80; /* Enable Preamble Sequence */
548 v |= 0x2; /* MDIO Clock Divisor */
549 pcicore_write32(pc, mdio_control, v);
551 if (pc->dev->id.revision >= 10) {
553 ssb_pcie_mdio_set_phy(pc, device);
556 v = (1 << 30); /* Start of Transaction */
557 v |= (1 << 28); /* Write Transaction */
558 v |= (1 << 17); /* Turnaround */
559 if (pc->dev->id.revision < 10)
560 v |= (u32)device << 22;
561 v |= (u32)address << 18;
563 pcicore_write32(pc, mdio_data, v);
564 /* Wait for the device to complete the transaction */
566 for (i = 0; i < max_retries; i++) {
567 v = pcicore_read32(pc, mdio_control);
568 if (v & 0x100 /* Trans complete */)
572 pcicore_write32(pc, mdio_control, 0);
575 static void ssb_broadcast_value(struct ssb_device *dev,
576 u32 address, u32 data)
578 /* This is used for both, PCI and ChipCommon core, so be careful. */
579 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
580 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
582 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
583 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
584 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
585 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
588 static void ssb_commit_settings(struct ssb_bus *bus)
590 struct ssb_device *dev;
592 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
595 /* This forces an update of the cached registers. */
596 ssb_broadcast_value(dev, 0xFD8, 0);
599 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
600 struct ssb_device *dev)
602 struct ssb_device *pdev = pc->dev;
607 if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
608 /* This SSB device is not on a PCI host-bus. So the IRQs are
609 * not routed through the PCI core.
610 * So we must not enable routing through the PCI core. */
618 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
620 /* Enable interrupts for this device. */
621 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
624 /* Calculate the "coremask" for the device. */
625 coremask = (1 << dev->core_index);
627 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
628 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
631 tmp |= coremask << 8;
632 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
638 intvec = ssb_read32(pdev, SSB_INTVEC);
639 tmp = ssb_read32(dev, SSB_TPSFLAG);
640 tmp &= SSB_TPSFLAG_BPFLAG;
641 intvec |= (1 << tmp);
642 ssb_write32(pdev, SSB_INTVEC, intvec);
645 /* Setup PCIcore operation. */
648 if (pdev->id.coreid == SSB_DEV_PCI) {
649 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
650 tmp |= SSB_PCICORE_SBTOPCI_PREF;
651 tmp |= SSB_PCICORE_SBTOPCI_BURST;
652 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
654 if (pdev->id.revision < 5) {
655 tmp = ssb_read32(pdev, SSB_IMCFGLO);
656 tmp &= ~SSB_IMCFGLO_SERTO;
658 tmp &= ~SSB_IMCFGLO_REQTO;
659 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
660 ssb_write32(pdev, SSB_IMCFGLO, tmp);
661 ssb_commit_settings(bus);
662 } else if (pdev->id.revision >= 11) {
663 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
664 tmp |= SSB_PCICORE_SBTOPCI_MRM;
665 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
668 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
669 //TODO: Better make defines for all these magic PCIE values.
670 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
671 /* TLP Workaround register. */
672 tmp = ssb_pcie_read(pc, 0x4);
674 ssb_pcie_write(pc, 0x4, tmp);
676 if (pdev->id.revision == 0) {
677 const u8 serdes_rx_device = 0x1F;
679 ssb_pcie_mdio_write(pc, serdes_rx_device,
680 2 /* Timer */, 0x8128);
681 ssb_pcie_mdio_write(pc, serdes_rx_device,
682 6 /* CDR */, 0x0100);
683 ssb_pcie_mdio_write(pc, serdes_rx_device,
684 7 /* CDR BW */, 0x1466);
685 } else if (pdev->id.revision == 1) {
686 /* DLLP Link Control register. */
687 tmp = ssb_pcie_read(pc, 0x100);
689 ssb_pcie_write(pc, 0x100, tmp);
696 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);