2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/types.h>
19 #include <bcmendian.h>
22 #include <sdio.h> /* SDIO Device and Protocol Specs */
23 #include <sdioh.h> /* SDIO Host Controller Specification */
24 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
25 #include <sdiovar.h> /* ioctl/iovars */
27 #include <linux/mmc/core.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/sdio_ids.h>
31 #include <dngl_stats.h>
34 #if defined(CONFIG_PM_SLEEP)
35 #include <linux/suspend.h>
36 extern volatile bool dhd_mmc_suspend;
38 #include "bcmsdh_sdmmc.h"
40 extern int sdio_function_init(void);
41 extern void sdio_function_cleanup(void);
43 #if !defined(OOB_INTR_ONLY)
44 static void IRQHandler(struct sdio_func *func);
45 static void IRQHandlerF2(struct sdio_func *func);
46 #endif /* !defined(OOB_INTR_ONLY) */
47 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr);
48 extern int sdio_reset_comm(struct mmc_card *card);
50 extern PBCMSDH_SDMMC_INSTANCE gInstance;
52 uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
53 uint sd_f2_blocksize = 512; /* Default blocksize */
55 uint sd_divisor = 2; /* Default 48MHz/2 = 24MHz */
57 uint sd_power = 1; /* Default to SD Slot powered ON */
58 uint sd_clock = 1; /* Default to SD Clock turned ON */
59 uint sd_hiok = false; /* Don't use hi-speed mode by default */
60 uint sd_msglevel = 0x01;
61 uint sd_use_dma = true;
62 DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
63 DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
64 DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
65 DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
67 #define DMA_ALIGN_MASK 0x03
69 int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
70 int regsize, u32 *data);
72 static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
78 sd_trace(("%s\n", __func__));
80 /* Get the Card's common CIS address */
81 sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
82 sd->func_cis_ptr[0] = sd->com_cis_ptr;
83 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
86 /* Get the Card's function CIS (for each function) */
87 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
88 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
89 sd->func_cis_ptr[func] =
90 sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
91 sd_info(("%s: Function %d CIS Ptr = 0x%x\n", __func__, func,
92 sd->func_cis_ptr[func]));
95 sd->func_cis_ptr[0] = sd->com_cis_ptr;
96 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
99 /* Enable Function 1 */
100 sdio_claim_host(gInstance->func[1]);
101 err_ret = sdio_enable_func(gInstance->func[1]);
102 sdio_release_host(gInstance->func[1]);
104 sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x",
112 * Public entry points & extern's
114 extern sdioh_info_t *sdioh_attach(osl_t *osh, void *bar0, uint irq)
119 sd_trace(("%s\n", __func__));
121 if (gInstance == NULL) {
122 sd_err(("%s: SDIO Device not present\n", __func__));
126 sd = kzalloc(sizeof(sdioh_info_t), GFP_ATOMIC);
128 sd_err(("sdioh_attach: out of memory\n"));
132 if (sdioh_sdmmc_osinit(sd) != 0) {
133 sd_err(("%s:sdioh_sdmmc_osinit() failed\n", __func__));
139 sd->sd_blockmode = true;
140 sd->use_client_ints = true;
141 sd->client_block_size[0] = 64;
145 /* Claim host controller */
146 sdio_claim_host(gInstance->func[1]);
148 sd->client_block_size[1] = 64;
149 err_ret = sdio_set_block_size(gInstance->func[1], 64);
151 sd_err(("bcmsdh_sdmmc: Failed to set F1 blocksize\n"));
153 /* Release host controller F1 */
154 sdio_release_host(gInstance->func[1]);
156 if (gInstance->func[2]) {
157 /* Claim host controller F2 */
158 sdio_claim_host(gInstance->func[2]);
160 sd->client_block_size[2] = sd_f2_blocksize;
162 sdio_set_block_size(gInstance->func[2], sd_f2_blocksize);
164 sd_err(("bcmsdh_sdmmc: Failed to set F2 blocksize "
165 "to %d\n", sd_f2_blocksize));
167 /* Release host controller F2 */
168 sdio_release_host(gInstance->func[2]);
171 sdioh_sdmmc_card_enablefuncs(sd);
173 sd_trace(("%s: Done\n", __func__));
177 extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd)
179 sd_trace(("%s\n", __func__));
183 /* Disable Function 2 */
184 sdio_claim_host(gInstance->func[2]);
185 sdio_disable_func(gInstance->func[2]);
186 sdio_release_host(gInstance->func[2]);
188 /* Disable Function 1 */
189 sdio_claim_host(gInstance->func[1]);
190 sdio_disable_func(gInstance->func[1]);
191 sdio_release_host(gInstance->func[1]);
194 sdioh_sdmmc_osfree(sd);
198 return SDIOH_API_RC_SUCCESS;
201 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
203 extern SDIOH_API_RC sdioh_enable_func_intr(void)
208 if (gInstance->func[0]) {
209 sdio_claim_host(gInstance->func[0]);
211 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
213 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
215 sdio_release_host(gInstance->func[0]);
216 return SDIOH_API_RC_FAIL;
219 /* Enable F1 and F2 interrupts, set master enable */
221 (INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN |
224 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
225 sdio_release_host(gInstance->func[0]);
228 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
230 return SDIOH_API_RC_FAIL;
234 return SDIOH_API_RC_SUCCESS;
237 extern SDIOH_API_RC sdioh_disable_func_intr(void)
242 if (gInstance->func[0]) {
243 sdio_claim_host(gInstance->func[0]);
244 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
246 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
248 sdio_release_host(gInstance->func[0]);
249 return SDIOH_API_RC_FAIL;
252 reg &= ~(INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
253 /* Disable master interrupt with the last function interrupt */
256 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
258 sdio_release_host(gInstance->func[0]);
260 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
262 return SDIOH_API_RC_FAIL;
265 return SDIOH_API_RC_SUCCESS;
267 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
269 /* Configure callback to client when we recieve client interrupt */
271 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
273 sd_trace(("%s: Entering\n", __func__));
275 sd_err(("%s: interrupt handler is NULL, not registering\n",
277 return SDIOH_API_RC_FAIL;
279 #if !defined(OOB_INTR_ONLY)
280 sd->intr_handler = fn;
281 sd->intr_handler_arg = argh;
282 sd->intr_handler_valid = true;
284 /* register and unmask irq */
285 if (gInstance->func[2]) {
286 sdio_claim_host(gInstance->func[2]);
287 sdio_claim_irq(gInstance->func[2], IRQHandlerF2);
288 sdio_release_host(gInstance->func[2]);
291 if (gInstance->func[1]) {
292 sdio_claim_host(gInstance->func[1]);
293 sdio_claim_irq(gInstance->func[1], IRQHandler);
294 sdio_release_host(gInstance->func[1]);
296 #elif defined(HW_OOB)
297 sdioh_enable_func_intr();
298 #endif /* defined(OOB_INTR_ONLY) */
299 return SDIOH_API_RC_SUCCESS;
302 extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *sd)
304 sd_trace(("%s: Entering\n", __func__));
306 #if !defined(OOB_INTR_ONLY)
307 if (gInstance->func[1]) {
308 /* register and unmask irq */
309 sdio_claim_host(gInstance->func[1]);
310 sdio_release_irq(gInstance->func[1]);
311 sdio_release_host(gInstance->func[1]);
314 if (gInstance->func[2]) {
315 /* Claim host controller F2 */
316 sdio_claim_host(gInstance->func[2]);
317 sdio_release_irq(gInstance->func[2]);
318 /* Release host controller F2 */
319 sdio_release_host(gInstance->func[2]);
322 sd->intr_handler_valid = false;
323 sd->intr_handler = NULL;
324 sd->intr_handler_arg = NULL;
325 #elif defined(HW_OOB)
326 sdioh_disable_func_intr();
327 #endif /* !defined(OOB_INTR_ONLY) */
328 return SDIOH_API_RC_SUCCESS;
331 extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
333 sd_trace(("%s: Entering\n", __func__));
334 *onoff = sd->client_intr_enabled;
335 return SDIOH_API_RC_SUCCESS;
338 #if defined(DHD_DEBUG)
339 extern bool sdioh_interrupt_pending(sdioh_info_t *sd)
345 uint sdioh_query_iofnum(sdioh_info_t *sd)
347 return sd->num_funcs;
370 const bcm_iovar_t sdioh_iovars[] = {
371 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0},
372 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0},
373 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0},/* ((fn << 16) |
375 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0},
376 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0},
377 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0},
378 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0},
379 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
381 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
383 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0}
385 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0}
387 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0}
389 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100}
391 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0}
393 {"sd_rxchain", IOV_RXCHAIN, 0, IOVT_BOOL, 0}
399 sdioh_iovar_op(sdioh_info_t *si, const char *name,
400 void *params, int plen, void *arg, int len, bool set)
402 const bcm_iovar_t *vi = NULL;
412 /* Get must have return space; Set does not take qualifiers */
413 ASSERT(set || (arg && len));
414 ASSERT(!set || (!params && !plen));
416 sd_trace(("%s: Enter (%s %s)\n", __func__, (set ? "set" : "get"),
419 vi = bcm_iovar_lookup(sdioh_iovars, name);
421 bcmerror = BCME_UNSUPPORTED;
425 bcmerror = bcm_iovar_lencheck(vi, arg, len, set);
429 /* Set up params so get and set can share the convenience variables */
430 if (params == NULL) {
435 if (vi->type == IOVT_VOID)
437 else if (vi->type == IOVT_BUFFER)
440 val_size = sizeof(int);
442 if (plen >= (int)sizeof(int_val))
443 bcopy(params, &int_val, sizeof(int_val));
445 bool_val = (int_val != 0) ? true : false;
447 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
449 case IOV_GVAL(IOV_MSGLEVEL):
450 int_val = (s32) sd_msglevel;
451 bcopy(&int_val, arg, val_size);
454 case IOV_SVAL(IOV_MSGLEVEL):
455 sd_msglevel = int_val;
458 case IOV_GVAL(IOV_BLOCKMODE):
459 int_val = (s32) si->sd_blockmode;
460 bcopy(&int_val, arg, val_size);
463 case IOV_SVAL(IOV_BLOCKMODE):
464 si->sd_blockmode = (bool) int_val;
465 /* Haven't figured out how to make non-block mode with DMA */
468 case IOV_GVAL(IOV_BLOCKSIZE):
469 if ((u32) int_val > si->num_funcs) {
470 bcmerror = BCME_BADARG;
473 int_val = (s32) si->client_block_size[int_val];
474 bcopy(&int_val, arg, val_size);
477 case IOV_SVAL(IOV_BLOCKSIZE):
479 uint func = ((u32) int_val >> 16);
480 uint blksize = (u16) int_val;
483 if (func > si->num_funcs) {
484 bcmerror = BCME_BADARG;
493 maxsize = BLOCK_SIZE_4318;
496 maxsize = BLOCK_SIZE_4328;
501 if (blksize > maxsize) {
502 bcmerror = BCME_BADARG;
509 si->client_block_size[func] = blksize;
514 case IOV_GVAL(IOV_RXCHAIN):
516 bcopy(&int_val, arg, val_size);
519 case IOV_GVAL(IOV_DMA):
520 int_val = (s32) si->sd_use_dma;
521 bcopy(&int_val, arg, val_size);
524 case IOV_SVAL(IOV_DMA):
525 si->sd_use_dma = (bool) int_val;
528 case IOV_GVAL(IOV_USEINTS):
529 int_val = (s32) si->use_client_ints;
530 bcopy(&int_val, arg, val_size);
533 case IOV_SVAL(IOV_USEINTS):
534 si->use_client_ints = (bool) int_val;
535 if (si->use_client_ints)
536 si->intmask |= CLIENT_INTR;
538 si->intmask &= ~CLIENT_INTR;
542 case IOV_GVAL(IOV_DIVISOR):
543 int_val = (u32) sd_divisor;
544 bcopy(&int_val, arg, val_size);
547 case IOV_SVAL(IOV_DIVISOR):
548 sd_divisor = int_val;
551 case IOV_GVAL(IOV_POWER):
552 int_val = (u32) sd_power;
553 bcopy(&int_val, arg, val_size);
556 case IOV_SVAL(IOV_POWER):
560 case IOV_GVAL(IOV_CLOCK):
561 int_val = (u32) sd_clock;
562 bcopy(&int_val, arg, val_size);
565 case IOV_SVAL(IOV_CLOCK):
569 case IOV_GVAL(IOV_SDMODE):
570 int_val = (u32) sd_sdmode;
571 bcopy(&int_val, arg, val_size);
574 case IOV_SVAL(IOV_SDMODE):
578 case IOV_GVAL(IOV_HISPEED):
579 int_val = (u32) sd_hiok;
580 bcopy(&int_val, arg, val_size);
583 case IOV_SVAL(IOV_HISPEED):
587 case IOV_GVAL(IOV_NUMINTS):
588 int_val = (s32) si->intrcount;
589 bcopy(&int_val, arg, val_size);
592 case IOV_GVAL(IOV_NUMLOCALINTS):
594 bcopy(&int_val, arg, val_size);
597 case IOV_GVAL(IOV_HOSTREG):
599 sdreg_t *sd_ptr = (sdreg_t *) params;
601 if (sd_ptr->offset < SD_SysAddr
602 || sd_ptr->offset > SD_MaxCurCap) {
603 sd_err(("%s: bad offset 0x%x\n", __func__,
605 bcmerror = BCME_BADARG;
609 sd_trace(("%s: rreg%d at offset %d\n", __func__,
610 (sd_ptr->offset & 1) ? 8
611 : ((sd_ptr->offset & 2) ? 16 : 32),
613 if (sd_ptr->offset & 1)
614 int_val = 8; /* sdioh_sdmmc_rreg8(si,
616 else if (sd_ptr->offset & 2)
617 int_val = 16; /* sdioh_sdmmc_rreg16(si,
620 int_val = 32; /* sdioh_sdmmc_rreg(si,
623 bcopy(&int_val, arg, sizeof(int_val));
627 case IOV_SVAL(IOV_HOSTREG):
629 sdreg_t *sd_ptr = (sdreg_t *) params;
631 if (sd_ptr->offset < SD_SysAddr
632 || sd_ptr->offset > SD_MaxCurCap) {
633 sd_err(("%s: bad offset 0x%x\n", __func__,
635 bcmerror = BCME_BADARG;
639 sd_trace(("%s: wreg%d value 0x%08x at offset %d\n",
640 __func__, sd_ptr->value,
641 (sd_ptr->offset & 1) ? 8
642 : ((sd_ptr->offset & 2) ? 16 : 32),
647 case IOV_GVAL(IOV_DEVREG):
649 sdreg_t *sd_ptr = (sdreg_t *) params;
653 (si, sd_ptr->func, sd_ptr->offset, &data)) {
654 bcmerror = BCME_SDIO_ERROR;
659 bcopy(&int_val, arg, sizeof(int_val));
663 case IOV_SVAL(IOV_DEVREG):
665 sdreg_t *sd_ptr = (sdreg_t *) params;
666 u8 data = (u8) sd_ptr->value;
669 (si, sd_ptr->func, sd_ptr->offset, &data)) {
670 bcmerror = BCME_SDIO_ERROR;
677 bcmerror = BCME_UNSUPPORTED;
685 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
687 SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
693 data = 3; /* enable hw oob interrupt */
695 data = 4; /* disable hw oob interrupt */
696 data |= 4; /* Active HIGH */
698 status = sdioh_request_byte(sd, SDIOH_WRITE, 0, 0xf2, &data);
701 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
704 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
707 /* No lock needed since sdioh_request_byte does locking */
708 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
713 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
715 /* No lock needed since sdioh_request_byte does locking */
717 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
721 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr)
723 /* read 24 bits and return valid 17 bit addr */
725 u32 scratch, regdata;
726 u8 *ptr = (u8 *)&scratch;
727 for (i = 0; i < 3; i++) {
728 if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, ®data)) !=
730 sd_err(("%s: Can't read!\n", __func__));
732 *ptr++ = (u8) regdata;
736 /* Only the lower 17-bits are valid */
737 scratch = ltoh32(scratch);
738 scratch &= 0x0001FFFF;
743 sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, u32 length)
750 sd_trace(("%s: Func = %d\n", __func__, func));
752 if (!sd->func_cis_ptr[func]) {
754 sd_err(("%s: no func_cis_ptr[%d]\n", __func__, func));
755 return SDIOH_API_RC_FAIL;
758 sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __func__, func,
759 sd->func_cis_ptr[func]));
761 for (count = 0; count < length; count++) {
762 offset = sd->func_cis_ptr[func] + count;
763 if (sdioh_sdmmc_card_regread(sd, 0, offset, 1, &foo) < 0) {
764 sd_err(("%s: regread failed: Can't read CIS\n",
766 return SDIOH_API_RC_FAIL;
769 *cis = (u8) (foo & 0xff);
773 return SDIOH_API_RC_SUCCESS;
777 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
782 sd_info(("%s: rw=%d, func=%d, addr=0x%05x\n", __func__, rw, func,
785 DHD_PM_RESUME_WAIT(sdioh_request_byte_wait);
786 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
787 if (rw) { /* CMD52 Write */
789 /* Can only directly write to some F0 registers.
793 if (regaddr == SDIOD_CCCR_IOEN) {
794 if (gInstance->func[2]) {
795 sdio_claim_host(gInstance->func[2]);
796 if (*byte & SDIO_FUNC_ENABLE_2) {
797 /* Enable Function 2 */
800 (gInstance->func[2]);
802 sd_err(("bcmsdh_sdmmc: enable F2 failed:%d",
805 /* Disable Function 2 */
808 (gInstance->func[2]);
810 sd_err(("bcmsdh_sdmmc: Disab F2 failed:%d",
813 sdio_release_host(gInstance->func[2]);
816 #if defined(MMC_SDIO_ABORT)
817 /* to allow abort command through F1 */
818 else if (regaddr == SDIOD_CCCR_IOABORT) {
819 sdio_claim_host(gInstance->func[func]);
821 * this sdio_f0_writeb() can be replaced
823 * depending upon MMC driver change.
824 * As of this time, this is temporaray one
826 sdio_writeb(gInstance->func[func], *byte,
828 sdio_release_host(gInstance->func[func]);
830 #endif /* MMC_SDIO_ABORT */
831 else if (regaddr < 0xF0) {
832 sd_err(("bcmsdh_sdmmc: F0 Wr:0x%02x: write "
833 "disallowed\n", regaddr));
835 /* Claim host controller, perform F0 write,
837 sdio_claim_host(gInstance->func[func]);
838 sdio_f0_writeb(gInstance->func[func], *byte,
840 sdio_release_host(gInstance->func[func]);
843 /* Claim host controller, perform Fn write,
845 sdio_claim_host(gInstance->func[func]);
846 sdio_writeb(gInstance->func[func], *byte, regaddr,
848 sdio_release_host(gInstance->func[func]);
850 } else { /* CMD52 Read */
851 /* Claim host controller, perform Fn read, and release */
852 sdio_claim_host(gInstance->func[func]);
856 sdio_f0_readb(gInstance->func[func], regaddr,
860 sdio_readb(gInstance->func[func], regaddr,
864 sdio_release_host(gInstance->func[func]);
868 sd_err(("bcmsdh_sdmmc: Failed to %s byte F%d:@0x%05x=%02x, "
869 "Err: %d\n", rw ? "Write" : "Read", func, regaddr,
872 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
876 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func,
877 uint addr, u32 *word, uint nbytes)
879 int err_ret = SDIOH_API_RC_FAIL;
882 sd_err(("%s: Only CMD52 allowed to F0.\n", __func__));
883 return SDIOH_API_RC_FAIL;
886 sd_info(("%s: cmd_type=%d, rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
887 __func__, cmd_type, rw, func, addr, nbytes));
889 DHD_PM_RESUME_WAIT(sdioh_request_word_wait);
890 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
891 /* Claim host controller */
892 sdio_claim_host(gInstance->func[func]);
894 if (rw) { /* CMD52 Write */
896 sdio_writel(gInstance->func[func], *word, addr,
898 } else if (nbytes == 2) {
899 sdio_writew(gInstance->func[func], (*word & 0xFFFF),
902 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
904 } else { /* CMD52 Read */
907 sdio_readl(gInstance->func[func], addr, &err_ret);
908 } else if (nbytes == 2) {
910 sdio_readw(gInstance->func[func], addr,
913 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
917 /* Release host controller */
918 sdio_release_host(gInstance->func[func]);
921 sd_err(("bcmsdh_sdmmc: Failed to %s word, Err: 0x%08x",
922 rw ? "Write" : "Read", err_ret));
925 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
929 sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
930 uint addr, void *pkt)
932 bool fifo = (fix_inc == SDIOH_DATA_FIX);
938 sd_trace(("%s: Enter\n", __func__));
941 DHD_PM_RESUME_WAIT(sdioh_request_packet_wait);
942 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
944 /* Claim host controller */
945 sdio_claim_host(gInstance->func[func]);
946 for (pnext = pkt; pnext; pnext = PKTNEXT(pnext)) {
947 uint pkt_len = PKTLEN(pnext);
949 pkt_len &= 0xFFFFFFFC;
951 #ifdef CONFIG_MMC_MSM7X00A
952 if ((pkt_len % 64) == 32) {
953 sd_trace(("%s: Rounding up TX packet +=32\n",
957 #endif /* CONFIG_MMC_MSM7X00A */
958 /* Make sure the packet is aligned properly.
959 * If it isn't, then this
960 * is the fault of sdioh_request_buffer() which
961 * is supposed to give
962 * us something we can work with.
964 ASSERT(((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0);
966 if ((write) && (!fifo)) {
967 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
968 ((u8 *) PKTDATA(pnext)),
971 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
972 ((u8 *) PKTDATA(pnext)),
975 err_ret = sdio_readsb(gInstance->func[func],
976 ((u8 *) PKTDATA(pnext)),
979 err_ret = sdio_memcpy_fromio(gInstance->func[func],
980 ((u8 *) PKTDATA(pnext)),
985 sd_err(("%s: %s FAILED %p[%d], addr=0x%05x, pkt_len=%d,"
986 "ERR=0x%08x\n", __func__,
987 (write) ? "TX" : "RX",
988 pnext, SGCount, addr, pkt_len, err_ret));
990 sd_trace(("%s: %s xfr'd %p[%d], addr=0x%05x, len=%d\n",
992 (write) ? "TX" : "RX",
993 pnext, SGCount, addr, pkt_len));
1002 /* Release host controller */
1003 sdio_release_host(gInstance->func[func]);
1005 sd_trace(("%s: Exit\n", __func__));
1006 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
1010 * This function takes a buffer or packet, and fixes everything up
1012 * end, a DMA-able packet is created.
1014 * A buffer does not have an associated packet pointer,
1015 * and may or may not be aligned.
1016 * A packet may consist of a single packet, or a packet chain.
1017 * If it is a packet chain,
1018 * then all the packets in the chain must be properly aligned.
1019 * If the packet data is not
1020 * aligned, then there may only be one packet, and in this case,
1021 * it is copied to a new
1026 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
1027 uint func, uint addr, uint reg_width, uint buflen_u,
1028 u8 *buffer, void *pkt)
1030 SDIOH_API_RC Status;
1033 sd_trace(("%s: Enter\n", __func__));
1035 DHD_PM_RESUME_WAIT(sdioh_request_buffer_wait);
1036 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
1037 /* Case 1: we don't have a packet. */
1039 sd_data(("%s: Creating new %s Packet, len=%d\n",
1040 __func__, write ? "TX" : "RX", buflen_u));
1041 mypkt = PKTGET(sd->osh, buflen_u, write ? true : false);
1043 sd_err(("%s: PKTGET failed: len %d\n",
1044 __func__, buflen_u));
1045 return SDIOH_API_RC_FAIL;
1048 /* For a write, copy the buffer data into the packet. */
1050 bcopy(buffer, PKTDATA(mypkt), buflen_u);
1053 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1055 /* For a read, copy the packet data back to the buffer. */
1057 bcopy(PKTDATA(mypkt), buffer, buflen_u);
1059 PKTFREE(sd->osh, mypkt, write ? true : false);
1060 } else if (((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) {
1061 /* Case 2: We have a packet, but it is unaligned. */
1063 /* In this case, we cannot have a chain. */
1064 ASSERT(PKTNEXT(pkt) == NULL);
1066 sd_data(("%s: Creating aligned %s Packet, len=%d\n",
1067 __func__, write ? "TX" : "RX", PKTLEN(pkt)));
1068 mypkt = PKTGET(sd->osh, PKTLEN(pkt), write ? true : false);
1070 sd_err(("%s: PKTGET failed: len %d\n",
1071 __func__, PKTLEN(pkt)));
1072 return SDIOH_API_RC_FAIL;
1075 /* For a write, copy the buffer data into the packet. */
1077 bcopy(PKTDATA(pkt), PKTDATA(mypkt), PKTLEN(pkt));
1080 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1082 /* For a read, copy the packet data back to the buffer. */
1084 bcopy(PKTDATA(mypkt), PKTDATA(pkt), PKTLEN(mypkt));
1086 PKTFREE(sd->osh, mypkt, write ? true : false);
1087 } else { /* case 3: We have a packet and
1089 sd_data(("%s: Aligned %s Packet, direct DMA\n",
1090 __func__, write ? "Tx" : "Rx"));
1092 sdioh_request_packet(sd, fix_inc, write, func, addr, pkt);
1098 /* this function performs "abort" for both of host & device */
1099 extern int sdioh_abort(sdioh_info_t *sd, uint func)
1101 #if defined(MMC_SDIO_ABORT)
1102 char t_func = (char)func;
1103 #endif /* defined(MMC_SDIO_ABORT) */
1104 sd_trace(("%s: Enter\n", __func__));
1106 #if defined(MMC_SDIO_ABORT)
1107 /* issue abort cmd52 command through F1 */
1108 sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT,
1110 #endif /* defined(MMC_SDIO_ABORT) */
1112 sd_trace(("%s: Exit\n", __func__));
1113 return SDIOH_API_RC_SUCCESS;
1116 /* Reset and re-initialize the device */
1117 int sdioh_sdio_reset(sdioh_info_t *si)
1119 sd_trace(("%s: Enter\n", __func__));
1120 sd_trace(("%s: Exit\n", __func__));
1121 return SDIOH_API_RC_SUCCESS;
1124 /* Disable device interrupt */
1125 void sdioh_sdmmc_devintr_off(sdioh_info_t *sd)
1127 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1128 sd->intmask &= ~CLIENT_INTR;
1131 /* Enable device interrupt */
1132 void sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
1134 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1135 sd->intmask |= CLIENT_INTR;
1138 /* Read client card reg */
1140 sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
1141 int regsize, u32 *data)
1144 if ((func == 0) || (regsize == 1)) {
1147 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1150 sd_data(("%s: byte read data=0x%02x\n", __func__, *data));
1152 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, data,
1157 sd_data(("%s: word read data=0x%08x\n", __func__, *data));
1163 #if !defined(OOB_INTR_ONLY)
1164 /* bcmsdh_sdmmc interrupt handler */
1165 static void IRQHandler(struct sdio_func *func)
1169 sd_trace(("bcmsdh_sdmmc: ***IRQHandler\n"));
1173 sdio_release_host(gInstance->func[0]);
1175 if (sd->use_client_ints) {
1177 ASSERT(sd->intr_handler);
1178 ASSERT(sd->intr_handler_arg);
1179 (sd->intr_handler) (sd->intr_handler_arg);
1181 sd_err(("bcmsdh_sdmmc: ***IRQHandler\n"));
1183 sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
1184 __func__, sd->client_intr_enabled, sd->intr_handler));
1187 sdio_claim_host(gInstance->func[0]);
1190 /* bcmsdh_sdmmc interrupt handler for F2 (dummy handler) */
1191 static void IRQHandlerF2(struct sdio_func *func)
1195 sd_trace(("bcmsdh_sdmmc: ***IRQHandlerF2\n"));
1201 #endif /* !defined(OOB_INTR_ONLY) */
1204 /* Write client card reg */
1206 sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, u32 regaddr,
1207 int regsize, u32 data)
1210 if ((func == 0) || (regsize == 1)) {
1214 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1215 sd_data(("%s: byte write data=0x%02x\n", __func__, data));
1220 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, &data,
1223 sd_data(("%s: word write data=0x%08x\n", __func__, data));
1228 #endif /* NOTUSED */
1230 int sdioh_start(sdioh_info_t *si, int stage)
1235 int sdioh_stop(sdioh_info_t *si)