2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
26 #include <sdio_host.h>
29 #include <brcmu_wifi.h>
30 #include <brcmu_utils.h>
31 #include <brcm_hw_ids.h>
35 /* register access macros */
39 bcmsdh_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
43 __typeof(*(r)) __osl_v; \
44 __asm__ __volatile__("sync"); \
45 __osl_v = bcmsdh_reg_read(NULL, (unsigned long)(r),\
47 __asm__ __volatile__("sync"); \
52 #define W_REG(r, v) do { \
53 bcmsdh_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), (v)); \
55 #else /* __BIG_ENDIAN */
57 bcmsdh_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
58 #define W_REG(r, v) do { \
59 bcmsdh_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), (v)); \
61 #endif /* __BIG_ENDIAN */
63 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
64 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
66 #define SET_REG(r, mask, val) \
67 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
71 /* ARM trap handling */
73 /* Trap types defined by ARM (see arminc.h) */
75 /* Trap locations in lo memory */
77 #define FIRST_TRAP TR_RST
78 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
80 #if defined(__ARM_ARCH_4T__)
81 #define MAX_TRAP_TYPE (TR_FIQ + 1)
82 #elif defined(__ARM_ARCH_7M__)
83 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
84 #endif /* __ARM_ARCH_7M__ */
86 /* The trap structure is defined here as offsets for assembly */
92 #define TR_REG(n) (TR_REGS + (n) * 4)
93 #define TR_SP TR_REG(13)
94 #define TR_LR TR_REG(14)
95 #define TR_PC TR_REG(15)
97 #define TRAP_T_SIZE 80
99 typedef struct _trap_struct {
122 #define CBUF_LEN (128)
124 #define LOG_BUF_LEN 1024
127 u32 buf; /* Can't be pointer on (64-bit) hosts */
130 char *_buf_compat; /* Redundant pointer for backward compat. */
135 * When there is no UART (e.g. Quickturn),
136 * the host should write a complete
137 * input line directly into cbuf and then write
138 * the length into vcons_in.
139 * This may also be used when there is a real UART
140 * (at risk of conflicting with
141 * the real UART). vcons_out is currently unused.
143 volatile uint vcons_in;
144 volatile uint vcons_out;
146 /* Output (logging) buffer
147 * Console output is written to a ring buffer log_buf at index log_idx.
148 * The host may read the output when it sees log_idx advance.
149 * Output will be lost if the output wraps around faster than the host
154 /* Console input line buffer
155 * Characters are read one at a time into cbuf
156 * until <CR> is received, then
157 * the buffer is processed as a command line.
158 * Also used for virtual UART.
164 #endif /* DHD_DEBUG */
165 #include <chipcommon.h>
169 #include <dngl_stats.h>
172 #include <dhd_proto.h>
177 #ifndef DHDSDIO_MEM_DUMP_FNAME
178 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
181 #define TXQLEN 2048 /* bulk tx queue length */
182 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
183 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
186 #define TXRETRIES 2 /* # of retries for tx frames */
188 #if defined(CONFIG_MACH_SANDGATE2G)
189 #define DHD_RXBOUND 250 /* Default for max rx frames in
192 #define DHD_RXBOUND 50 /* Default for max rx frames in
194 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
196 #define DHD_TXBOUND 20 /* Default for max tx frames in
199 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
201 #define MEMBLOCK 2048 /* Block size used for downloading
203 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
204 biggest possible glom */
206 /* Packet alignment for most efficient SDIO (can change based on platform) */
208 #define DHD_SDALIGN 32
210 #if !ISPOWEROF2(DHD_SDALIGN)
211 #error DHD_SDALIGN is not a power of 2!
214 #ifndef DHD_FIRSTREAD
215 #define DHD_FIRSTREAD 32
217 #if !ISPOWEROF2(DHD_FIRSTREAD)
218 #error DHD_FIRSTREAD is not a power of 2!
221 /* Total length of frame header for dongle protocol */
222 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
224 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
226 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
230 * Software allocation of To SB Mailbox resources
233 /* tosbmailbox bits corresponding to intstatus bits */
234 #define SMB_NAK (1 << 0) /* Frame NAK */
235 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
236 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
237 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
239 /* tosbmailboxdata */
240 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
243 * Software allocation of To Host Mailbox resources
247 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
248 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
249 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
250 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
252 /* tohostmailboxdata */
253 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
254 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
255 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
256 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
258 #define HMB_DATA_FCDATA_MASK 0xff000000
259 #define HMB_DATA_FCDATA_SHIFT 24
261 #define HMB_DATA_VERSION_MASK 0x00ff0000
262 #define HMB_DATA_VERSION_SHIFT 16
265 * Software-defined protocol header
268 /* Current protocol version */
269 #define SDPCM_PROT_VERSION 4
271 /* SW frame header */
272 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
274 #define SDPCM_CHANNEL_MASK 0x00000f00
275 #define SDPCM_CHANNEL_SHIFT 8
276 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
278 #define SDPCM_NEXTLEN_OFFSET 2
280 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
281 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
282 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
283 #define SDPCM_DOFFSET_MASK 0xff000000
284 #define SDPCM_DOFFSET_SHIFT 24
285 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
286 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
287 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
288 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
290 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
292 /* logical channel numbers */
293 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
294 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
295 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
296 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
297 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
299 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
301 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
303 /* For TEST_CHANNEL packets, define another 4-byte header */
304 #define SDPCM_TEST_HDRLEN 4 /*
305 * Generally: Cmd(1), Ext(1), Len(2);
306 * Semantics of Ext byte depend on
307 * command. Len is current or requested
308 * frame length, not including test
309 * header; sent little-endian.
311 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
312 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
313 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
314 #define SDPCM_TEST_BURST 0x04 /*
315 * Receiver to send a burst.
316 * Ext is a frame count
318 #define SDPCM_TEST_SEND 0x05 /*
319 * Receiver sets send mode.
320 * Ext is boolean on/off
323 /* Handy macro for filling in datagen packets with a pattern */
324 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
327 * Shared structure between dongle and the host.
328 * The structure contains pointers to trap or assert information.
330 #define SDPCM_SHARED_VERSION 0x0002
331 #define SDPCM_SHARED_VERSION_MASK 0x00FF
332 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
333 #define SDPCM_SHARED_ASSERT 0x0200
334 #define SDPCM_SHARED_TRAP 0x0400
337 /* Space for header read, limit for data packets */
339 #define MAX_HDR_READ 32
341 #if !ISPOWEROF2(MAX_HDR_READ)
342 #error MAX_HDR_READ is not a power of 2!
345 #define MAX_RX_DATASZ 2048
347 /* Maximum milliseconds to wait for F2 to come up */
348 #define DHD_WAIT_F2RDY 3000
350 /* Bump up limit on waiting for HT to account for first startup;
351 * if the image is doing a CRC calculation before programming the PMU
352 * for HT availability, it could take a couple hundred ms more, so
353 * max out at a 1 second (1000000us).
355 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
356 #undef PMU_MAX_TRANSITION_DLY
357 #define PMU_MAX_TRANSITION_DLY 1000000
360 /* Value for ChipClockCSR during initial setup */
361 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
362 SBSDIO_ALP_AVAIL_REQ)
363 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
365 /* Flags for SDH calls */
366 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
369 #define SBIM_IBE 0x20000 /* inbanderror */
370 #define SBIM_TO 0x40000 /* timeout */
371 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
372 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
375 #define SBTML_RESET 0x0001 /* reset */
376 #define SBTML_REJ_MASK 0x0006 /* reject field */
377 #define SBTML_REJ 0x0002 /* reject */
378 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
380 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
383 #define SBTMH_SERR 0x0001 /* serror */
384 #define SBTMH_INT 0x0002 /* interrupt */
385 #define SBTMH_BUSY 0x0004 /* busy */
386 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
388 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
391 #define SBIDL_INIT 0x80 /* initiator */
394 #define SBIDH_RC_MASK 0x000f /* revision code */
395 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
396 #define SBIDH_RCE_SHIFT 8
397 #define SBCOREREV(sbidh) \
398 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
399 #define SBIDH_CC_MASK 0x8ff0 /* core code */
400 #define SBIDH_CC_SHIFT 4
401 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
402 #define SBIDH_VC_SHIFT 16
405 * Conversion of 802.1D priority to precedence level
407 #define PRIO2PREC(prio) \
408 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
411 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
412 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
415 /* Core reg address translation */
416 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
417 #define CORE_BUS_REG(base, field) \
418 (base + offsetof(struct sdpcmd_regs, field))
419 #define CORE_SB(base, field) \
420 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
423 /* Device console log buffer state */
424 typedef struct dhd_console {
425 uint count; /* Poll interval msec counter */
426 uint log_addr; /* Log struct address (fixed) */
427 rte_log_t log; /* Log struct (host copy) */
428 uint bufsize; /* Size of log buffer */
429 u8 *buf; /* Log buffer (host copy) */
430 uint last; /* Last buffer read index */
432 #endif /* DHD_DEBUG */
434 struct sdpcm_shared {
438 u32 assert_file_addr;
440 u32 console_addr; /* Address of rte_cons_t */
446 /* misc chip info needed by some of the routines */
462 /* Private data for SDIO bus interaction */
463 typedef struct dhd_bus {
466 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
467 struct chip_info *ci; /* Chip info struct */
468 char *vars; /* Variables (from CIS and/or other) */
469 uint varsz; /* Size of variables buffer */
470 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
472 struct sdpcmd_regs *regs; /* SDIO core */
473 uint sdpcmrev; /* SDIO core revision */
474 uint armrev; /* CPU core revision */
475 uint ramrev; /* SOCRAM core revision */
476 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
477 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
479 u32 bus; /* gSPI or SDIO bus */
480 u32 hostintmask; /* Copy of Host Interrupt Mask */
481 u32 intstatus; /* Intstatus bits (events) pending */
482 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
483 bool fcstate; /* State of dongle flow-control */
485 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
486 char *fw_path; /* module_param: path to firmware image */
487 char *nv_path; /* module_param: path to nvram vars file */
488 const char *nvram_params; /* user specified nvram params. */
490 uint blocksize; /* Block size of SDIO transfers */
491 uint roundup; /* Max roundup limit */
493 struct pktq txq; /* Queue length used for flow-control */
494 u8 flowcontrol; /* per prio flow control bitmask */
495 u8 tx_seq; /* Transmit sequence number (next) */
496 u8 tx_max; /* Maximum transmit sequence allowed */
498 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
499 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
500 u16 nextlen; /* Next Read Len from last header */
501 u8 rx_seq; /* Receive sequence number (expected) */
502 bool rxskip; /* Skip receive (awaiting NAK ACK) */
504 struct sk_buff *glomd; /* Packet containing glomming descriptor */
505 struct sk_buff *glom; /* Packet chain for glommed superframe */
506 uint glomerr; /* Glom packet read errors */
508 u8 *rxbuf; /* Buffer for receiving control packets */
509 uint rxblen; /* Allocated length of rxbuf */
510 u8 *rxctl; /* Aligned pointer into rxbuf */
511 u8 *databuf; /* Buffer for receiving big glom packet */
512 u8 *dataptr; /* Aligned pointer into databuf */
513 uint rxlen; /* Length of valid data in buffer */
515 u8 sdpcm_ver; /* Bus protocol reported by dongle */
517 bool intr; /* Use interrupts */
518 bool poll; /* Use polling */
519 bool ipend; /* Device interrupt is pending */
520 bool intdis; /* Interrupts disabled by isr */
521 uint intrcount; /* Count of device interrupt callbacks */
522 uint lastintrs; /* Count as of last watchdog timer */
523 uint spurious; /* Count of spurious interrupts */
524 uint pollrate; /* Ticks between device polls */
525 uint polltick; /* Tick counter */
526 uint pollcnt; /* Count of active polls */
529 dhd_console_t console; /* Console output polling support */
530 uint console_addr; /* Console address from shared struct */
531 #endif /* DHD_DEBUG */
533 uint regfails; /* Count of R_REG/W_REG failures */
535 uint clkstate; /* State of sd and backplane clock(s) */
536 bool activity; /* Activity flag for clock down */
537 s32 idletime; /* Control for activity timeout */
538 s32 idlecount; /* Activity timeout counter */
539 s32 idleclock; /* How to set bus driver when idle */
540 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
541 bool use_rxchain; /* If dhd should use PKT chains */
542 bool sleeping; /* Is SDIO bus sleeping? */
543 bool rxflow_mode; /* Rx flow control mode */
544 bool rxflow; /* Is rx flow control on */
545 uint prev_rxlim_hit; /* Is prev rx limit exceeded
546 (per dpc schedule) */
547 bool alp_only; /* Don't use HT clock (ALP only) */
548 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
552 /* external loopback */
556 /* pktgen configuration */
557 uint pktgen_freq; /* Ticks between bursts */
558 uint pktgen_count; /* Packets to send each burst */
559 uint pktgen_print; /* Bursts between count displays */
560 uint pktgen_total; /* Stop after this many */
561 uint pktgen_minlen; /* Minimum packet data len */
562 uint pktgen_maxlen; /* Maximum packet data len */
563 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
564 uint pktgen_stop; /* Number of tx failures causing stop */
566 /* active pktgen fields */
567 uint pktgen_tick; /* Tick counter for bursts */
568 uint pktgen_ptick; /* Burst counter for printing */
569 uint pktgen_sent; /* Number of test packets generated */
570 uint pktgen_rcvd; /* Number of test packets received */
571 uint pktgen_fail; /* Number of failed send attempts */
572 u16 pktgen_len; /* Length of next packet to send */
575 /* Some additional counters */
576 uint tx_sderrs; /* Count of tx attempts with sd errors */
577 uint fcqueued; /* Tx packets that got queued */
578 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
579 uint rx_toolong; /* Receive frames too long to receive */
580 uint rxc_errors; /* SDIO errors when reading control frames */
581 uint rx_hdrfail; /* SDIO errors on header reads */
582 uint rx_badhdr; /* Bad received headers (roosync?) */
583 uint rx_badseq; /* Mismatched rx sequence number */
584 uint fc_rcvd; /* Number of flow-control events received */
585 uint fc_xoff; /* Number which turned on flow-control */
586 uint fc_xon; /* Number which turned off flow-control */
587 uint rxglomfail; /* Failed deglom attempts */
588 uint rxglomframes; /* Number of glom frames (superframes) */
589 uint rxglompkts; /* Number of packets from glom frames */
590 uint f2rxhdrs; /* Number of header reads */
591 uint f2rxdata; /* Number of frame data reads */
592 uint f2txdata; /* Number of f2 frame writes */
593 uint f1regdata; /* Number of f1 register accesses */
597 bool ctrl_frame_stat;
600 typedef volatile struct _sbconfig {
602 u32 sbipsflag; /* initiator port ocp slave flag */
604 u32 sbtpsflag; /* target port ocp slave flag */
606 u32 sbtmerrloga; /* (sonics >= 2.3) */
608 u32 sbtmerrlog; /* (sonics >= 2.3) */
610 u32 sbadmatch3; /* address match3 */
612 u32 sbadmatch2; /* address match2 */
614 u32 sbadmatch1; /* address match1 */
616 u32 sbimstate; /* initiator agent state */
617 u32 sbintvec; /* interrupt mask */
618 u32 sbtmstatelow; /* target state */
619 u32 sbtmstatehigh; /* target state */
620 u32 sbbwa0; /* bandwidth allocation table0 */
622 u32 sbimconfiglow; /* initiator configuration */
623 u32 sbimconfighigh; /* initiator configuration */
624 u32 sbadmatch0; /* address match0 */
626 u32 sbtmconfiglow; /* target configuration */
627 u32 sbtmconfighigh; /* target configuration */
628 u32 sbbconfig; /* broadcast configuration */
630 u32 sbbstate; /* broadcast state */
632 u32 sbactcnfg; /* activate configuration */
634 u32 sbflagst; /* current sbflags */
636 u32 sbidlow; /* identification */
637 u32 sbidhigh; /* identification */
643 #define CLK_PENDING 2 /* Not used yet */
646 #define DHD_NOPMU(dhd) (false)
649 static int qcount[NUMPRIO];
650 static int tx_packets[NUMPRIO];
651 #endif /* DHD_DEBUG */
653 /* Deferred transmit */
654 const uint dhd_deferred_tx = 1;
656 extern uint dhd_watchdog_ms;
657 extern void dhd_os_wd_timer(void *bus, uint wdtick);
664 /* override the RAM size if possible */
665 #define DONGLE_MIN_MEMSIZE (128 * 1024)
666 int dhd_dongle_memsize;
668 static bool dhd_alignctl;
672 static bool retrydata;
673 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
675 static const uint watermark = 8;
676 static const uint firstread = DHD_FIRSTREAD;
678 #define HDATLEN (firstread - (SDPCM_HDRLEN))
680 /* Retry count for register access failures */
681 static const uint retry_limit = 2;
683 /* Force even SD lengths (some host controllers mess up on odd bytes) */
684 static bool forcealign;
688 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
689 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
692 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
693 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
694 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
695 #define PKTALIGN(_p, _len, _align) \
698 datalign = (unsigned long)((_p)->data); \
699 datalign = roundup(datalign, (_align)) - datalign; \
700 ASSERT(datalign < (_align)); \
701 ASSERT((_p)->len >= ((_len) + datalign)); \
703 skb_pull((_p), datalign); \
704 __skb_trim((_p), (_len)); \
707 /* Limit on rounding up frames */
708 static const uint max_roundup = 512;
710 /* Try doing readahead */
711 static bool dhd_readahead;
713 /* To check if there's window offered */
714 #define DATAOK(bus) \
715 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
716 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
718 /* Macros to get register read/write status */
719 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
720 #define R_SDREG(regvar, regaddr, retryvar) \
724 regvar = R_REG(regaddr); \
725 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
727 bus->regfails += (retryvar-1); \
728 if (retryvar > retry_limit) { \
729 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
730 __func__, __LINE__)); \
736 #define W_SDREG(regval, regaddr, retryvar) \
740 W_REG(regaddr, regval); \
741 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
743 bus->regfails += (retryvar-1); \
744 if (retryvar > retry_limit) \
745 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
746 __func__, __LINE__)); \
750 #define DHD_BUS SDIO_BUS
752 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
754 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
757 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
758 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
762 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
763 static int dhdsdio_mem_dump(dhd_bus_t *bus);
764 #endif /* DHD_DEBUG */
765 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
767 static void dhdsdio_release(dhd_bus_t *bus);
768 static void dhdsdio_release_malloc(dhd_bus_t *bus);
769 static void dhdsdio_disconnect(void *ptr);
770 static bool dhdsdio_chipmatch(u16 chipid);
771 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
772 void *regsva, u16 devid);
773 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
774 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
775 static void dhdsdio_release_dongle(dhd_bus_t *bus);
777 static uint process_nvram_vars(char *varbuf, uint len);
779 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
780 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
781 uint flags, u8 *buf, uint nbytes,
782 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
785 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
786 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
788 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
789 static int dhdsdio_download_nvram(struct dhd_bus *bus);
790 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
791 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
792 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
793 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
795 static void dhdsdio_chip_detach(struct dhd_bus *bus);
797 /* Packet free applicable unconditionally for sdio and sdspi.
798 * Conditional if bufpool was present for gspi bus.
800 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
802 dhd_os_sdlock_rxq(bus->dhd);
803 if ((bus->bus != SPI_BUS) || bus->usebufpool)
804 brcmu_pkt_buf_free_skb(pkt);
805 dhd_os_sdunlock_rxq(bus->dhd);
808 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
810 s32 min_size = DONGLE_MIN_MEMSIZE;
811 /* Restrict the memsize to user specified limit */
812 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
813 dhd_dongle_memsize, min_size));
814 if ((dhd_dongle_memsize > min_size) &&
815 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
816 bus->ramsize = dhd_dongle_memsize;
819 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
822 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
823 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
825 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
826 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
828 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
829 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
834 /* Turn backplane clock on or off */
835 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
838 u8 clkctl, clkreq, devctl;
841 DHD_TRACE(("%s: Enter\n", __func__));
843 #if defined(OOB_INTR_ONLY)
850 /* Request HT Avail */
852 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
854 if ((bus->ci->chip == BCM4329_CHIP_ID)
855 && (bus->ci->chiprev == 0))
856 clkreq |= SBSDIO_FORCE_ALP;
858 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
861 DHD_ERROR(("%s: HT Avail request error: %d\n",
866 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
867 && (bus->ci->buscorerev == 9))) {
869 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
872 /* Check current status */
874 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
877 DHD_ERROR(("%s: HT Avail read error: %d\n",
882 /* Go to pending and await interrupt if appropriate */
883 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
884 /* Allow only clock-available interrupt */
886 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
889 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
894 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
895 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
897 DHD_INFO(("CLKCTL: set PENDING\n"));
898 bus->clkstate = CLK_PENDING;
901 } else if (bus->clkstate == CLK_PENDING) {
902 /* Cancel CA-only interrupt filter */
904 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
906 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
907 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
911 /* Otherwise, wait here (polling) for HT Avail */
912 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
913 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
915 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
916 SBSDIO_FUNC1_CHIPCLKCSR,
918 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
919 PMU_MAX_TRANSITION_DLY);
922 DHD_ERROR(("%s: HT Avail request error: %d\n",
926 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
927 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
928 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
932 /* Mark clock available */
933 bus->clkstate = CLK_AVAIL;
934 DHD_INFO(("CLKCTL: turned ON\n"));
936 #if defined(DHD_DEBUG)
937 if (bus->alp_only == true) {
938 #if !defined(BCMLXSDMMC)
939 if (!SBSDIO_ALPONLY(clkctl)) {
940 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
943 #endif /* !defined(BCMLXSDMMC) */
945 if (SBSDIO_ALPONLY(clkctl)) {
946 DHD_ERROR(("%s: HT Clock should be on.\n",
950 #endif /* defined (DHD_DEBUG) */
952 bus->activity = true;
956 if (bus->clkstate == CLK_PENDING) {
957 /* Cancel CA-only interrupt filter */
959 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
961 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
962 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
966 bus->clkstate = CLK_SDONLY;
967 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
969 DHD_INFO(("CLKCTL: turned OFF\n"));
971 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
979 /* Change idle/active SD state */
980 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
982 DHD_TRACE(("%s: Enter\n", __func__));
985 bus->clkstate = CLK_SDONLY;
987 bus->clkstate = CLK_NONE;
992 /* Transition SD and backplane clock readiness */
993 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
996 uint oldstate = bus->clkstate;
997 #endif /* DHD_DEBUG */
999 DHD_TRACE(("%s: Enter\n", __func__));
1001 /* Early exit if we're already there */
1002 if (bus->clkstate == target) {
1003 if (target == CLK_AVAIL) {
1004 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1005 bus->activity = true;
1012 /* Make sure SD clock is available */
1013 if (bus->clkstate == CLK_NONE)
1014 dhdsdio_sdclk(bus, true);
1015 /* Now request HT Avail on the backplane */
1016 dhdsdio_htclk(bus, true, pendok);
1017 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1018 bus->activity = true;
1022 /* Remove HT request, or bring up SD clock */
1023 if (bus->clkstate == CLK_NONE)
1024 dhdsdio_sdclk(bus, true);
1025 else if (bus->clkstate == CLK_AVAIL)
1026 dhdsdio_htclk(bus, false, false);
1028 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
1029 bus->clkstate, target));
1030 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1034 /* Make sure to remove HT request */
1035 if (bus->clkstate == CLK_AVAIL)
1036 dhdsdio_htclk(bus, false, false);
1037 /* Now remove the SD clock */
1038 dhdsdio_sdclk(bus, false);
1039 dhd_os_wd_timer(bus->dhd, 0);
1043 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1044 #endif /* DHD_DEBUG */
1049 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1051 bcmsdh_info_t *sdh = bus->sdh;
1052 struct sdpcmd_regs *regs = bus->regs;
1055 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1056 (sleep ? "SLEEP" : "WAKE"),
1057 (bus->sleeping ? "SLEEP" : "WAKE")));
1059 /* Done if we're already in the requested state */
1060 if (sleep == bus->sleeping)
1063 /* Going to sleep: set the alarm and turn off the lights... */
1065 /* Don't sleep if something is pending */
1066 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1069 /* Disable SDIO interrupts (no longer interested) */
1070 bcmsdh_intr_disable(bus->sdh);
1072 /* Make sure the controller has the bus up */
1073 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1075 /* Tell device to start using OOB wakeup */
1076 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1077 if (retries > retry_limit)
1078 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1080 /* Turn off our contribution to the HT clock request */
1081 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1083 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1084 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1086 /* Isolate the bus */
1087 if (bus->ci->chip != BCM4329_CHIP_ID
1088 && bus->ci->chip != BCM4319_CHIP_ID) {
1089 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1090 SBSDIO_DEVCTL_PADS_ISO, NULL);
1094 bus->sleeping = true;
1097 /* Waking up: bus power up is ok, set local state */
1099 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1102 /* Force pad isolation off if possible
1103 (in case power never toggled) */
1104 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1105 && (bus->ci->buscorerev >= 10))
1106 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
1109 /* Make sure the controller has the bus up */
1110 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1112 /* Send misc interrupt to indicate OOB not needed */
1113 W_SDREG(0, ®s->tosbmailboxdata, retries);
1114 if (retries <= retry_limit)
1115 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1117 if (retries > retry_limit)
1118 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1120 /* Make sure we have SD bus access */
1121 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1124 bus->sleeping = false;
1126 /* Enable interrupts again */
1127 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1128 bus->intdis = false;
1129 bcmsdh_intr_enable(bus->sdh);
1136 #if defined(OOB_INTR_ONLY)
1137 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1140 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1142 sdpcmd_regs_t *regs = bus->regs;
1145 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1146 if (enable == true) {
1148 /* Tell device to start using OOB wakeup */
1149 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1150 if (retries > retry_limit)
1151 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1154 /* Send misc interrupt to indicate OOB not needed */
1155 W_SDREG(0, ®s->tosbmailboxdata, retries);
1156 if (retries <= retry_limit)
1157 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1160 /* Turn off our contribution to the HT clock request */
1161 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1162 #endif /* !defined(HW_OOB) */
1164 #endif /* defined(OOB_INTR_ONLY) */
1166 #define BUS_WAKE(bus) \
1168 if ((bus)->sleeping) \
1169 dhdsdio_bussleep((bus), false); \
1172 /* Writes a HW/SW header into the packet and sends it. */
1173 /* Assumes: (a) header space already there, (b) caller holds lock */
1174 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1183 struct sk_buff *new;
1186 DHD_TRACE(("%s: Enter\n", __func__));
1190 if (bus->dhd->dongle_reset) {
1195 frame = (u8 *) (pkt->data);
1197 /* Add alignment padding, allocate new packet if needed */
1198 pad = ((unsigned long)frame % DHD_SDALIGN);
1200 if (skb_headroom(pkt) < pad) {
1201 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1202 __func__, skb_headroom(pkt), pad));
1203 bus->dhd->tx_realloc++;
1204 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1206 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1208 __func__, pkt->len + DHD_SDALIGN));
1213 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1214 memcpy(new->data, pkt->data, pkt->len);
1216 brcmu_pkt_buf_free_skb(pkt);
1217 /* free the pkt if canned one is not used */
1220 frame = (u8 *) (pkt->data);
1221 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1225 frame = (u8 *) (pkt->data);
1227 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1228 memset(frame, 0, pad + SDPCM_HDRLEN);
1231 ASSERT(pad < DHD_SDALIGN);
1233 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1234 len = (u16) (pkt->len);
1235 *(u16 *) frame = cpu_to_le16(len);
1236 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1238 /* Software tag: channel, sequence number, data offset */
1240 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1242 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1244 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1245 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1248 tx_packets[pkt->priority]++;
1249 if (DHD_BYTES_ON() &&
1250 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1251 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1252 printk(KERN_DEBUG "Tx Frame:\n");
1253 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1254 } else if (DHD_HDRS_ON()) {
1255 printk(KERN_DEBUG "TxHdr:\n");
1256 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1257 frame, min_t(u16, len, 16));
1261 /* Raise len to next SDIO block to eliminate tail command */
1262 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1263 u16 pad = bus->blocksize - (len % bus->blocksize);
1264 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1266 if (pad <= skb_tailroom(pkt))
1267 #endif /* NOTUSED */
1269 } else if (len % DHD_SDALIGN) {
1270 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1273 /* Some controllers have trouble with odd bytes -- round to even */
1274 if (forcealign && (len & (ALIGNMENT - 1))) {
1276 if (skb_tailroom(pkt))
1278 len = roundup(len, ALIGNMENT);
1281 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1288 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1289 F2SYNC, frame, len, pkt, NULL, NULL);
1291 ASSERT(ret != -BCME_PENDING);
1294 /* On failure, abort the command
1295 and terminate the frame */
1296 DHD_INFO(("%s: sdio error %d, abort command and "
1297 "terminate frame.\n", __func__, ret));
1300 bcmsdh_abort(sdh, SDIO_FUNC_2);
1301 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1302 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1306 for (i = 0; i < 3; i++) {
1308 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1309 SBSDIO_FUNC1_WFRAMEBCHI,
1311 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1312 SBSDIO_FUNC1_WFRAMEBCLO,
1314 bus->f1regdata += 2;
1315 if ((hi == 0) && (lo == 0))
1321 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1323 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1326 /* restore pkt buffer pointer before calling tx complete routine */
1327 skb_pull(pkt, SDPCM_HDRLEN + pad);
1328 dhd_os_sdunlock(bus->dhd);
1329 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1330 dhd_os_sdlock(bus->dhd);
1333 brcmu_pkt_buf_free_skb(pkt);
1338 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1343 DHD_TRACE(("%s: Enter\n", __func__));
1348 /* Push the test header if doing loopback */
1349 if (bus->ext_loop) {
1351 skb_push(pkt, SDPCM_TEST_HDRLEN);
1353 *data++ = SDPCM_TEST_ECHOREQ;
1354 *data++ = (u8) bus->loopid++;
1355 *data++ = (datalen >> 0);
1356 *data++ = (datalen >> 8);
1357 datalen += SDPCM_TEST_HDRLEN;
1361 /* Add space for the header */
1362 skb_push(pkt, SDPCM_HDRLEN);
1363 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1365 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1367 /* Check for existing queue, current flow-control,
1368 pending event, or pending clock */
1369 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1370 || bus->dpc_sched || (!DATAOK(bus))
1371 || (bus->flowcontrol & NBITVAL(prec))
1372 || (bus->clkstate != CLK_AVAIL)) {
1373 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1374 pktq_len(&bus->txq)));
1377 /* Priority based enq */
1378 dhd_os_sdlock_txq(bus->dhd);
1379 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1380 skb_pull(pkt, SDPCM_HDRLEN);
1381 dhd_txcomplete(bus->dhd, pkt, false);
1382 brcmu_pkt_buf_free_skb(pkt);
1383 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1388 dhd_os_sdunlock_txq(bus->dhd);
1390 if (pktq_len(&bus->txq) >= TXHI)
1391 dhd_txflowcontrol(bus->dhd, 0, ON);
1394 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1395 qcount[prec] = pktq_plen(&bus->txq, prec);
1397 /* Schedule DPC if needed to send queued packet(s) */
1398 if (dhd_deferred_tx && !bus->dpc_sched) {
1399 bus->dpc_sched = true;
1400 dhd_sched_dpc(bus->dhd);
1403 /* Lock: we're about to use shared data/code (and SDIO) */
1404 dhd_os_sdlock(bus->dhd);
1406 /* Otherwise, send it now */
1408 /* Make sure back plane ht clk is on, no pending allowed */
1409 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1412 DHD_TRACE(("%s: calling txpkt\n", __func__));
1413 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1415 ret = dhdsdio_txpkt(bus, pkt,
1416 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1417 SDPCM_DATA_CHANNEL), true);
1420 bus->dhd->tx_errors++;
1422 bus->dhd->dstats.tx_bytes += datalen;
1424 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1425 bus->activity = false;
1426 dhdsdio_clkctl(bus, CLK_NONE, true);
1429 dhd_os_sdunlock(bus->dhd);
1435 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1437 struct sk_buff *pkt;
1440 int ret = 0, prec_out;
1445 dhd_pub_t *dhd = bus->dhd;
1446 struct sdpcmd_regs *regs = bus->regs;
1448 DHD_TRACE(("%s: Enter\n", __func__));
1450 tx_prec_map = ~bus->flowcontrol;
1452 /* Send frames until the limit or some other event */
1453 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1454 dhd_os_sdlock_txq(bus->dhd);
1455 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1457 dhd_os_sdunlock_txq(bus->dhd);
1460 dhd_os_sdunlock_txq(bus->dhd);
1461 datalen = pkt->len - SDPCM_HDRLEN;
1464 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1466 ret = dhdsdio_txpkt(bus, pkt,
1467 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1468 SDPCM_DATA_CHANNEL), true);
1471 bus->dhd->tx_errors++;
1473 bus->dhd->dstats.tx_bytes += datalen;
1475 /* In poll mode, need to check for other events */
1476 if (!bus->intr && cnt) {
1477 /* Check device status, signal pending interrupt */
1478 R_SDREG(intstatus, ®s->intstatus, retries);
1480 if (bcmsdh_regfail(bus->sdh))
1482 if (intstatus & bus->hostintmask)
1487 /* Deflow-control stack if needed */
1488 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1489 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1490 dhd_txflowcontrol(dhd, 0, OFF);
1495 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1501 bcmsdh_info_t *sdh = bus->sdh;
1506 DHD_TRACE(("%s: Enter\n", __func__));
1508 if (bus->dhd->dongle_reset)
1511 /* Back the pointer to make a room for bus header */
1512 frame = msg - SDPCM_HDRLEN;
1513 len = (msglen += SDPCM_HDRLEN);
1515 /* Add alignment padding (optional for ctl frames) */
1517 doff = ((unsigned long)frame % DHD_SDALIGN);
1522 memset(frame, 0, doff + SDPCM_HDRLEN);
1524 ASSERT(doff < DHD_SDALIGN);
1526 doff += SDPCM_HDRLEN;
1528 /* Round send length to next SDIO block */
1529 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1530 u16 pad = bus->blocksize - (len % bus->blocksize);
1531 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1533 } else if (len % DHD_SDALIGN) {
1534 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1537 /* Satisfy length-alignment requirements */
1538 if (forcealign && (len & (ALIGNMENT - 1)))
1539 len = roundup(len, ALIGNMENT);
1541 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1543 /* Need to lock here to protect txseq and SDIO tx calls */
1544 dhd_os_sdlock(bus->dhd);
1548 /* Make sure backplane clock is on */
1549 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1551 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1552 *(u16 *) frame = cpu_to_le16((u16) msglen);
1553 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1555 /* Software tag: channel, sequence number, data offset */
1557 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1559 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1560 SDPCM_DOFFSET_MASK);
1561 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1562 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1565 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1566 __func__, bus->tx_max, bus->tx_seq));
1567 bus->ctrl_frame_stat = true;
1569 bus->ctrl_frame_buf = frame;
1570 bus->ctrl_frame_len = len;
1572 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1574 if (bus->ctrl_frame_stat == false) {
1575 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1578 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1585 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1586 printk(KERN_DEBUG "Tx Frame:\n");
1587 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1589 } else if (DHD_HDRS_ON()) {
1590 printk(KERN_DEBUG "TxHdr:\n");
1591 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1592 frame, min_t(u16, len, 16));
1597 bus->ctrl_frame_stat = false;
1599 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1600 SDIO_FUNC_2, F2SYNC, frame, len,
1603 ASSERT(ret != -BCME_PENDING);
1606 /* On failure, abort the command and
1607 terminate the frame */
1608 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1612 bcmsdh_abort(sdh, SDIO_FUNC_2);
1614 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1615 SBSDIO_FUNC1_FRAMECTRL,
1619 for (i = 0; i < 3; i++) {
1621 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1622 SBSDIO_FUNC1_WFRAMEBCHI,
1624 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1625 SBSDIO_FUNC1_WFRAMEBCLO,
1627 bus->f1regdata += 2;
1628 if ((hi == 0) && (lo == 0))
1635 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1637 } while ((ret < 0) && retries++ < TXRETRIES);
1640 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1641 bus->activity = false;
1642 dhdsdio_clkctl(bus, CLK_NONE, true);
1645 dhd_os_sdunlock(bus->dhd);
1648 bus->dhd->tx_ctlerrs++;
1650 bus->dhd->tx_ctlpkts++;
1652 return ret ? -EIO : 0;
1655 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1661 DHD_TRACE(("%s: Enter\n", __func__));
1663 if (bus->dhd->dongle_reset)
1666 /* Wait until control frame is available */
1667 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1669 dhd_os_sdlock(bus->dhd);
1671 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1673 dhd_os_sdunlock(bus->dhd);
1676 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1677 __func__, rxlen, msglen));
1678 } else if (timeleft == 0) {
1679 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1681 dhd_os_sdlock(bus->dhd);
1682 dhdsdio_checkdied(bus, NULL, 0);
1683 dhd_os_sdunlock(bus->dhd);
1684 #endif /* DHD_DEBUG */
1685 } else if (pending == true) {
1686 DHD_CTL(("%s: cancelled\n", __func__));
1687 return -ERESTARTSYS;
1689 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1691 dhd_os_sdlock(bus->dhd);
1692 dhdsdio_checkdied(bus, NULL, 0);
1693 dhd_os_sdunlock(bus->dhd);
1694 #endif /* DHD_DEBUG */
1698 bus->dhd->rx_ctlpkts++;
1700 bus->dhd->rx_ctlerrs++;
1702 return rxlen ? (int)rxlen : -ETIMEDOUT;
1741 const struct brcmu_iovar dhdsdio_iovars[] = {
1742 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1743 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1744 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1745 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1746 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1747 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1748 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1749 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1750 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1751 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1752 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1753 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1754 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1755 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1756 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1757 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1759 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1761 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1763 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1765 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1767 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1769 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1771 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1773 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1776 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1778 #endif /* DHD_DEBUG */
1779 #endif /* DHD_DEBUG */
1781 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1783 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1791 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1796 brcmu_bprintf(strbuf, "%s N/A", desc);
1799 q2 = (100 * (num - (q1 * div))) / div;
1800 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1804 void dhd_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1806 dhd_bus_t *bus = dhdp->bus;
1808 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1809 brcmu_bprintf(strbuf,
1810 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1811 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1812 brcmu_bprintf(strbuf,
1813 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1814 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1815 bus->rxskip, bus->rxlen, bus->rx_seq);
1816 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1817 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1818 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1819 bus->pollrate, bus->pollcnt, bus->regfails);
1821 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1822 brcmu_bprintf(strbuf,
1823 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1824 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1826 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1827 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1828 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1829 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1830 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1831 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1832 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1834 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1835 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1837 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1838 (bus->f2rxhdrs + bus->f2rxdata));
1839 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1841 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1842 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1843 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1845 brcmu_bprintf(strbuf, "\n");
1847 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1848 bus->dhd->rx_packets);
1849 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1851 brcmu_bprintf(strbuf, "\n");
1853 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1855 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1857 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1858 (bus->f2txdata + bus->f1regdata));
1859 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1861 brcmu_bprintf(strbuf, "\n");
1863 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1864 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1865 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1866 dhd_dump_pct(strbuf, ", pkts/f1sd",
1867 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1869 dhd_dump_pct(strbuf, ", pkts/sd",
1870 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1871 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1873 dhd_dump_pct(strbuf, ", pkts/int",
1874 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1876 brcmu_bprintf(strbuf, "\n\n");
1880 if (bus->pktgen_count) {
1881 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1882 brcmu_bprintf(strbuf,
1883 "freq %d count %d print %d total %d min %d len %d\n",
1884 bus->pktgen_freq, bus->pktgen_count,
1885 bus->pktgen_print, bus->pktgen_total,
1886 bus->pktgen_minlen, bus->pktgen_maxlen);
1887 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1888 bus->pktgen_sent, bus->pktgen_rcvd,
1893 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1895 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1896 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1898 #endif /* DHD_DEBUG */
1899 brcmu_bprintf(strbuf,
1900 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1901 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1905 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1907 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1909 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1910 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1911 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1912 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1913 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1914 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1918 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1920 dhd_pktgen_t pktgen;
1922 pktgen.version = DHD_PKTGEN_VERSION;
1923 pktgen.freq = bus->pktgen_freq;
1924 pktgen.count = bus->pktgen_count;
1925 pktgen.print = bus->pktgen_print;
1926 pktgen.total = bus->pktgen_total;
1927 pktgen.minlen = bus->pktgen_minlen;
1928 pktgen.maxlen = bus->pktgen_maxlen;
1929 pktgen.numsent = bus->pktgen_sent;
1930 pktgen.numrcvd = bus->pktgen_rcvd;
1931 pktgen.numfail = bus->pktgen_fail;
1932 pktgen.mode = bus->pktgen_mode;
1933 pktgen.stop = bus->pktgen_stop;
1935 memcpy(arg, &pktgen, sizeof(pktgen));
1940 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1942 dhd_pktgen_t pktgen;
1943 uint oldcnt, oldmode;
1945 memcpy(&pktgen, arg, sizeof(pktgen));
1946 if (pktgen.version != DHD_PKTGEN_VERSION)
1949 oldcnt = bus->pktgen_count;
1950 oldmode = bus->pktgen_mode;
1952 bus->pktgen_freq = pktgen.freq;
1953 bus->pktgen_count = pktgen.count;
1954 bus->pktgen_print = pktgen.print;
1955 bus->pktgen_total = pktgen.total;
1956 bus->pktgen_minlen = pktgen.minlen;
1957 bus->pktgen_maxlen = pktgen.maxlen;
1958 bus->pktgen_mode = pktgen.mode;
1959 bus->pktgen_stop = pktgen.stop;
1961 bus->pktgen_tick = bus->pktgen_ptick = 0;
1962 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1963 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1965 /* Clear counts for a new pktgen (mode change, or was stopped) */
1966 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1967 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1974 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1981 /* Determine initial transfer parameters */
1982 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1983 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1984 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1988 /* Set the backplane window to include the start address */
1989 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1991 DHD_ERROR(("%s: window change failed\n", __func__));
1995 /* Do the transfer(s) */
1997 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1998 __func__, (write ? "write" : "read"), dsize,
1999 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
2001 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
2003 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2007 /* Adjust for next transfer (if any) */
2012 bcmerror = dhdsdio_set_siaddr_window(bus, address);
2014 DHD_ERROR(("%s: window change failed\n",
2019 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2024 /* Return the window to backplane enumeration space for core access */
2025 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
2026 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2027 __func__, bcmsdh_cur_sbwad(bus->sdh)));
2034 static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2039 /* Read last word in memory to determine address of
2040 sdpcm_shared structure */
2041 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
2045 addr = le32_to_cpu(addr);
2047 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2050 * Check if addr is valid.
2051 * NVRAM length at the end of memory should have been overwritten.
2053 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2054 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2059 /* Read rte_shared structure */
2060 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
2061 sizeof(struct sdpcm_shared));
2066 sh->flags = le32_to_cpu(sh->flags);
2067 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2068 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2069 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2070 sh->assert_line = le32_to_cpu(sh->assert_line);
2071 sh->console_addr = le32_to_cpu(sh->console_addr);
2072 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2074 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2075 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2076 "is different than sdpcm_shared version %d in dongle\n",
2077 __func__, SDPCM_SHARED_VERSION,
2078 sh->flags & SDPCM_SHARED_VERSION_MASK));
2085 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2089 char *mbuffer = NULL;
2090 uint maxstrlen = 256;
2093 struct sdpcm_shared sdpcm_shared;
2094 struct brcmu_strbuf strbuf;
2096 DHD_TRACE(("%s: Enter\n", __func__));
2100 * Called after a rx ctrl timeout. "data" is NULL.
2101 * allocate memory to trace the trap or assert.
2104 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2105 if (mbuffer == NULL) {
2106 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2113 str = kmalloc(maxstrlen, GFP_ATOMIC);
2115 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2120 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
2124 brcmu_binit(&strbuf, data, size);
2126 brcmu_bprintf(&strbuf,
2127 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2128 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2130 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2131 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2132 * (Avoids conflict with real asserts for programmatic
2133 * parsing of output.)
2135 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2138 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2140 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2141 * (Avoids conflict with real asserts for programmatic
2142 * parsing of output.)
2144 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2145 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2148 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2149 /* Download assert */
2150 brcmu_bprintf(&strbuf, "Dongle assert");
2151 if (sdpcm_shared.assert_exp_addr != 0) {
2153 bcmerror = dhdsdio_membytes(bus, false,
2154 sdpcm_shared.assert_exp_addr,
2155 (u8 *) str, maxstrlen);
2159 str[maxstrlen - 1] = '\0';
2160 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2163 if (sdpcm_shared.assert_file_addr != 0) {
2165 bcmerror = dhdsdio_membytes(bus, false,
2166 sdpcm_shared.assert_file_addr,
2167 (u8 *) str, maxstrlen);
2171 str[maxstrlen - 1] = '\0';
2172 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2175 brcmu_bprintf(&strbuf, " line %d ",
2176 sdpcm_shared.assert_line);
2179 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2180 bcmerror = dhdsdio_membytes(bus, false,
2181 sdpcm_shared.trap_addr, (u8 *)&tr,
2186 brcmu_bprintf(&strbuf,
2187 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2188 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2189 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2190 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2191 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2192 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2197 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2198 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2201 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2202 /* Mem dump to a file on device */
2203 dhdsdio_mem_dump(bus);
2205 #endif /* DHD_DEBUG */
2214 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2217 int size; /* Full mem size */
2218 int start = 0; /* Start address */
2219 int read_size = 0; /* Read size of each iteration */
2220 u8 *buf = NULL, *databuf = NULL;
2222 /* Get full mem size */
2223 size = bus->ramsize;
2224 buf = kmalloc(size, GFP_ATOMIC);
2226 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2230 /* Read mem content */
2231 printk(KERN_DEBUG "Dump dongle memory");
2234 read_size = min(MEMBLOCK, size);
2235 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2237 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2243 /* Decrement size and increment start address */
2246 databuf += read_size;
2248 printk(KERN_DEBUG "Done\n");
2250 /* free buf before return !!! */
2251 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2252 DHD_ERROR(("%s: Error writing to files\n", __func__));
2256 /* buf free handled in write_to_file, not here */
2260 #define CONSOLE_LINE_MAX 192
2262 static int dhdsdio_readconsole(dhd_bus_t *bus)
2264 dhd_console_t *c = &bus->console;
2265 u8 line[CONSOLE_LINE_MAX], ch;
2269 /* Don't do anything until FWREADY updates console address */
2270 if (bus->console_addr == 0)
2273 /* Read console log struct */
2274 addr = bus->console_addr + offsetof(rte_cons_t, log);
2275 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2280 /* Allocate console buffer (one time only) */
2281 if (c->buf == NULL) {
2282 c->bufsize = le32_to_cpu(c->log.buf_size);
2283 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2288 idx = le32_to_cpu(c->log.idx);
2290 /* Protect against corrupt value */
2291 if (idx > c->bufsize)
2294 /* Skip reading the console buffer if the index pointer
2299 /* Read the console buffer */
2300 addr = le32_to_cpu(c->log.buf);
2301 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2305 while (c->last != idx) {
2306 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2307 if (c->last == idx) {
2308 /* This would output a partial line.
2310 * the buffer pointer and output this
2311 * line next time around.
2316 c->last = c->bufsize - n;
2319 ch = c->buf[c->last];
2320 c->last = (c->last + 1) % c->bufsize;
2327 if (line[n - 1] == '\r')
2330 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2337 #endif /* DHD_DEBUG */
2339 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2343 DHD_TRACE(("%s: Enter\n", __func__));
2345 /* Basic sanity checks */
2347 bcmerror = -EISCONN;
2351 bcmerror = -EOVERFLOW;
2355 /* Free the old ones and replace with passed variables */
2358 bus->vars = kmalloc(len, GFP_ATOMIC);
2359 bus->varsz = bus->vars ? len : 0;
2360 if (bus->vars == NULL) {
2365 /* Copy the passed variables, which should include the
2366 terminating double-null */
2367 memcpy(bus->vars, arg, bus->varsz);
2373 dhdsdio_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2374 const char *name, void *params, int plen, void *arg, int len,
2381 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2382 "len %d val_size %d\n",
2383 __func__, actionid, name, params, plen, arg, len, val_size));
2385 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2389 if (plen >= (int)sizeof(int_val))
2390 memcpy(&int_val, params, sizeof(int_val));
2392 bool_val = (int_val != 0) ? true : false;
2394 /* Some ioctls use the bus */
2395 dhd_os_sdlock(bus->dhd);
2397 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2398 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2399 actionid == IOV_GVAL(IOV_DEVRESET))) {
2404 /* Handle sleep stuff before any clock mucking */
2405 if (vi->varid == IOV_SLEEP) {
2406 if (IOV_ISSET(actionid)) {
2407 bcmerror = dhdsdio_bussleep(bus, bool_val);
2409 int_val = (s32) bus->sleeping;
2410 memcpy(arg, &int_val, val_size);
2415 /* Request clock to allow SDIO accesses */
2416 if (!bus->dhd->dongle_reset) {
2418 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2422 case IOV_GVAL(IOV_INTR):
2423 int_val = (s32) bus->intr;
2424 memcpy(arg, &int_val, val_size);
2427 case IOV_SVAL(IOV_INTR):
2428 bus->intr = bool_val;
2429 bus->intdis = false;
2432 DHD_INTR(("%s: enable SDIO device interrupts\n",
2434 bcmsdh_intr_enable(bus->sdh);
2436 DHD_INTR(("%s: disable SDIO interrupts\n",
2438 bcmsdh_intr_disable(bus->sdh);
2443 case IOV_GVAL(IOV_POLLRATE):
2444 int_val = (s32) bus->pollrate;
2445 memcpy(arg, &int_val, val_size);
2448 case IOV_SVAL(IOV_POLLRATE):
2449 bus->pollrate = (uint) int_val;
2450 bus->poll = (bus->pollrate != 0);
2453 case IOV_GVAL(IOV_IDLETIME):
2454 int_val = bus->idletime;
2455 memcpy(arg, &int_val, val_size);
2458 case IOV_SVAL(IOV_IDLETIME):
2459 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2462 bus->idletime = int_val;
2465 case IOV_GVAL(IOV_IDLECLOCK):
2466 int_val = (s32) bus->idleclock;
2467 memcpy(arg, &int_val, val_size);
2470 case IOV_SVAL(IOV_IDLECLOCK):
2471 bus->idleclock = int_val;
2474 case IOV_GVAL(IOV_SD1IDLE):
2475 int_val = (s32) sd1idle;
2476 memcpy(arg, &int_val, val_size);
2479 case IOV_SVAL(IOV_SD1IDLE):
2483 case IOV_SVAL(IOV_MEMBYTES):
2484 case IOV_GVAL(IOV_MEMBYTES):
2490 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2492 ASSERT(plen >= 2 * sizeof(int));
2494 address = (u32) int_val;
2495 memcpy(&int_val, (char *)params + sizeof(int_val),
2497 size = (uint) int_val;
2499 /* Do some validation */
2500 dsize = set ? plen - (2 * sizeof(int)) : len;
2502 DHD_ERROR(("%s: error on %s membytes, addr "
2503 "0x%08x size %d dsize %d\n",
2504 __func__, (set ? "set" : "get"),
2505 address, size, dsize));
2510 DHD_INFO(("%s: Request to %s %d bytes at address "
2512 __func__, (set ? "write" : "read"), size, address));
2514 /* If we know about SOCRAM, check for a fit */
2515 if ((bus->orig_ramsize) &&
2516 ((address > bus->orig_ramsize)
2517 || (address + size > bus->orig_ramsize))) {
2518 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2519 "bytes at 0x%08x\n",
2520 __func__, bus->orig_ramsize, size, address));
2525 /* Generate the actual data pointer */
2527 set ? (u8 *) params +
2528 2 * sizeof(int) : (u8 *) arg;
2530 /* Call to do the transfer */
2532 dhdsdio_membytes(bus, set, address, data, size);
2537 case IOV_GVAL(IOV_MEMSIZE):
2538 int_val = (s32) bus->ramsize;
2539 memcpy(arg, &int_val, val_size);
2542 case IOV_GVAL(IOV_SDIOD_DRIVE):
2543 int_val = (s32) dhd_sdiod_drive_strength;
2544 memcpy(arg, &int_val, val_size);
2547 case IOV_SVAL(IOV_SDIOD_DRIVE):
2548 dhd_sdiod_drive_strength = int_val;
2549 dhdsdio_sdiod_drive_strength_init(bus,
2550 dhd_sdiod_drive_strength);
2553 case IOV_SVAL(IOV_DOWNLOAD):
2554 bcmerror = dhdsdio_download_state(bus, bool_val);
2557 case IOV_SVAL(IOV_VARS):
2558 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2561 case IOV_GVAL(IOV_READAHEAD):
2562 int_val = (s32) dhd_readahead;
2563 memcpy(arg, &int_val, val_size);
2566 case IOV_SVAL(IOV_READAHEAD):
2567 if (bool_val && !dhd_readahead)
2569 dhd_readahead = bool_val;
2572 case IOV_GVAL(IOV_SDRXCHAIN):
2573 int_val = (s32) bus->use_rxchain;
2574 memcpy(arg, &int_val, val_size);
2577 case IOV_SVAL(IOV_SDRXCHAIN):
2578 if (bool_val && !bus->sd_rxchain)
2579 bcmerror = -ENOTSUPP;
2581 bus->use_rxchain = bool_val;
2583 case IOV_GVAL(IOV_ALIGNCTL):
2584 int_val = (s32) dhd_alignctl;
2585 memcpy(arg, &int_val, val_size);
2588 case IOV_SVAL(IOV_ALIGNCTL):
2589 dhd_alignctl = bool_val;
2592 case IOV_GVAL(IOV_SDALIGN):
2593 int_val = DHD_SDALIGN;
2594 memcpy(arg, &int_val, val_size);
2598 case IOV_GVAL(IOV_VARS):
2599 if (bus->varsz < (uint) len)
2600 memcpy(arg, bus->vars, bus->varsz);
2602 bcmerror = -EOVERFLOW;
2604 #endif /* DHD_DEBUG */
2607 case IOV_GVAL(IOV_SDREG):
2612 sd_ptr = (sdreg_t *) params;
2614 addr = (unsigned long)bus->regs + sd_ptr->offset;
2615 size = sd_ptr->func;
2616 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2617 if (bcmsdh_regfail(bus->sdh))
2619 memcpy(arg, &int_val, sizeof(s32));
2623 case IOV_SVAL(IOV_SDREG):
2628 sd_ptr = (sdreg_t *) params;
2630 addr = (unsigned long)bus->regs + sd_ptr->offset;
2631 size = sd_ptr->func;
2632 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2633 if (bcmsdh_regfail(bus->sdh))
2638 /* Same as above, but offset is not backplane
2640 case IOV_GVAL(IOV_SBREG):
2645 memcpy(&sdreg, params, sizeof(sdreg));
2647 addr = SI_ENUM_BASE + sdreg.offset;
2649 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2650 if (bcmsdh_regfail(bus->sdh))
2652 memcpy(arg, &int_val, sizeof(s32));
2656 case IOV_SVAL(IOV_SBREG):
2661 memcpy(&sdreg, params, sizeof(sdreg));
2663 addr = SI_ENUM_BASE + sdreg.offset;
2665 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2666 if (bcmsdh_regfail(bus->sdh))
2671 case IOV_GVAL(IOV_SDCIS):
2675 strcat(arg, "\nFunc 0\n");
2676 bcmsdh_cis_read(bus->sdh, 0x10,
2677 (u8 *) arg + strlen(arg),
2678 SBSDIO_CIS_SIZE_LIMIT);
2679 strcat(arg, "\nFunc 1\n");
2680 bcmsdh_cis_read(bus->sdh, 0x11,
2681 (u8 *) arg + strlen(arg),
2682 SBSDIO_CIS_SIZE_LIMIT);
2683 strcat(arg, "\nFunc 2\n");
2684 bcmsdh_cis_read(bus->sdh, 0x12,
2685 (u8 *) arg + strlen(arg),
2686 SBSDIO_CIS_SIZE_LIMIT);
2690 case IOV_GVAL(IOV_FORCEEVEN):
2691 int_val = (s32) forcealign;
2692 memcpy(arg, &int_val, val_size);
2695 case IOV_SVAL(IOV_FORCEEVEN):
2696 forcealign = bool_val;
2699 case IOV_GVAL(IOV_TXBOUND):
2700 int_val = (s32) dhd_txbound;
2701 memcpy(arg, &int_val, val_size);
2704 case IOV_SVAL(IOV_TXBOUND):
2705 dhd_txbound = (uint) int_val;
2708 case IOV_GVAL(IOV_RXBOUND):
2709 int_val = (s32) dhd_rxbound;
2710 memcpy(arg, &int_val, val_size);
2713 case IOV_SVAL(IOV_RXBOUND):
2714 dhd_rxbound = (uint) int_val;
2717 case IOV_GVAL(IOV_TXMINMAX):
2718 int_val = (s32) dhd_txminmax;
2719 memcpy(arg, &int_val, val_size);
2722 case IOV_SVAL(IOV_TXMINMAX):
2723 dhd_txminmax = (uint) int_val;
2725 #endif /* DHD_DEBUG */
2728 case IOV_GVAL(IOV_EXTLOOP):
2729 int_val = (s32) bus->ext_loop;
2730 memcpy(arg, &int_val, val_size);
2733 case IOV_SVAL(IOV_EXTLOOP):
2734 bus->ext_loop = bool_val;
2737 case IOV_GVAL(IOV_PKTGEN):
2738 bcmerror = dhdsdio_pktgen_get(bus, arg);
2741 case IOV_SVAL(IOV_PKTGEN):
2742 bcmerror = dhdsdio_pktgen_set(bus, arg);
2746 case IOV_SVAL(IOV_DEVRESET):
2747 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2749 __func__, bool_val, bus->dhd->dongle_reset,
2750 bus->dhd->busstate));
2752 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2756 case IOV_GVAL(IOV_DEVRESET):
2757 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2759 /* Get its status */
2760 int_val = (bool) bus->dhd->dongle_reset;
2761 memcpy(arg, &int_val, val_size);
2766 bcmerror = -ENOTSUPP;
2771 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2772 bus->activity = false;
2773 dhdsdio_clkctl(bus, CLK_NONE, true);
2776 dhd_os_sdunlock(bus->dhd);
2778 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2779 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2784 static int dhdsdio_write_vars(dhd_bus_t *bus)
2792 char *nvram_ularray;
2793 #endif /* DHD_DEBUG */
2795 /* Even if there are no vars are to be written, we still
2796 need to set the ramsize. */
2797 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2798 varaddr = (bus->ramsize - 4) - varsize;
2801 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2805 memcpy(vbuffer, bus->vars, bus->varsz);
2807 /* Write the vars list */
2809 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2811 /* Verify NVRAM bytes */
2812 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2813 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2817 /* Upload image to verify downloaded contents. */
2818 memset(nvram_ularray, 0xaa, varsize);
2820 /* Read the vars list to temp buffer for comparison */
2822 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2825 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2826 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2828 /* Compare the org NVRAM with the one read from RAM */
2829 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2830 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2833 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2836 kfree(nvram_ularray);
2837 #endif /* DHD_DEBUG */
2842 /* adjust to the user specified RAM */
2843 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2844 bus->orig_ramsize, bus->ramsize));
2845 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2846 varsize = ((bus->orig_ramsize - 4) - varaddr);
2849 * Determine the length token:
2850 * Varsize, converted to words, in lower 16-bits, checksum
2856 varsizew = varsize / 4;
2857 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2858 varsizew = cpu_to_le32(varsizew);
2861 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2864 /* Write the length token to the last word */
2865 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2866 (u8 *)&varsizew, 4);
2871 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2877 /* To enter download state, disable ARM and reset SOCRAM.
2878 * To exit download state, simply reset ARM (default is RAM boot).
2881 bus->alp_only = true;
2883 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2885 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2887 /* Clear the top bit of memory */
2890 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2894 regdata = bcmsdh_reg_read(bus->sdh,
2895 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2896 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2897 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2898 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2899 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2905 bcmerror = dhdsdio_write_vars(bus);
2907 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2911 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2913 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2915 /* Allow HT Clock now that the ARM is running. */
2916 bus->alp_only = false;
2918 bus->dhd->busstate = DHD_BUS_LOAD;
2925 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2926 void *params, int plen, void *arg, int len, bool set)
2928 dhd_bus_t *bus = dhdp->bus;
2929 const struct brcmu_iovar *vi = NULL;
2934 DHD_TRACE(("%s: Enter\n", __func__));
2939 /* Get MUST have return space */
2940 ASSERT(set || (arg && len));
2942 /* Set does NOT take qualifiers */
2943 ASSERT(!set || (!params && !plen));
2945 /* Look up var locally; if not found pass to host driver */
2946 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2948 dhd_os_sdlock(bus->dhd);
2952 /* Turn on clock in case SD command needs backplane */
2953 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2956 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2959 /* Similar check for blocksize change */
2960 if (set && strcmp(name, "sd_blocksize") == 0) {
2963 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2964 &bus->blocksize, sizeof(s32),
2967 DHD_ERROR(("%s: fail on %s get\n", __func__,
2970 DHD_INFO(("%s: noted %s update, value now %d\n",
2971 __func__, "sd_blocksize",
2975 bus->roundup = min(max_roundup, bus->blocksize);
2977 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2978 bus->activity = false;
2979 dhdsdio_clkctl(bus, CLK_NONE, true);
2982 dhd_os_sdunlock(bus->dhd);
2986 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2987 name, (set ? "set" : "get"), len, plen));
2989 /* set up 'params' pointer in case this is a set command so that
2990 * the convenience int and bool code can be common to set and get
2992 if (params == NULL) {
2997 if (vi->type == IOVT_VOID)
2999 else if (vi->type == IOVT_BUFFER)
3002 /* all other types are integer sized */
3003 val_size = sizeof(int);
3005 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3007 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
3014 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
3016 u32 local_hostintmask;
3021 DHD_TRACE(("%s: Enter\n", __func__));
3024 dhd_os_sdlock(bus->dhd);
3028 /* Enable clock for device interrupts */
3029 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3031 /* Disable and clear interrupts at the chip level also */
3032 W_SDREG(0, &bus->regs->hostintmask, retries);
3033 local_hostintmask = bus->hostintmask;
3034 bus->hostintmask = 0;
3036 /* Change our idea of bus state */
3037 bus->dhd->busstate = DHD_BUS_DOWN;
3039 /* Force clocks on backplane to be sure F2 interrupt propagates */
3041 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3044 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3045 (saveclk | SBSDIO_FORCE_HT), &err);
3048 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3052 /* Turn off the bus (F2), free any pending packets */
3053 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3054 bcmsdh_intr_disable(bus->sdh);
3055 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3056 SDIO_FUNC_ENABLE_1, NULL);
3058 /* Clear any pending interrupts now that F2 is disabled */
3059 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3061 /* Turn off the backplane clock (only) */
3062 dhdsdio_clkctl(bus, CLK_SDONLY, false);
3064 /* Clear the data packet queues */
3065 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3067 /* Clear any held glomming stuff */
3069 brcmu_pkt_buf_free_skb(bus->glomd);
3072 brcmu_pkt_buf_free_skb(bus->glom);
3074 bus->glom = bus->glomd = NULL;
3076 /* Clear rx control and wake any waiters */
3078 dhd_os_ioctl_resp_wake(bus->dhd);
3080 /* Reset some F2 state stuff */
3081 bus->rxskip = false;
3082 bus->tx_seq = bus->rx_seq = 0;
3085 dhd_os_sdunlock(bus->dhd);
3088 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3090 dhd_bus_t *bus = dhdp->bus;
3097 DHD_TRACE(("%s: Enter\n", __func__));
3104 dhd_os_sdlock(bus->dhd);
3106 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3107 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3108 if (bus->clkstate != CLK_AVAIL)
3111 /* Force clocks on backplane to be sure F2 interrupt propagates */
3113 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3116 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3117 (saveclk | SBSDIO_FORCE_HT), &err);
3120 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3125 /* Enable function 2 (frame transfers) */
3126 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3127 &bus->regs->tosbmailboxdata, retries);
3128 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3130 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable, NULL);
3132 /* Give the dongle some time to do its thing and set IOR2 */
3133 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3136 while (ready != enable && !dhd_timeout_expired(&tmo))
3138 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3141 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3142 __func__, enable, ready, tmo.elapsed));
3144 /* If F2 successfully enabled, set core and enable interrupts */
3145 if (ready == enable) {
3146 /* Set up the interrupt mask and enable interrupts */
3147 bus->hostintmask = HOSTINTMASK;
3148 W_SDREG(bus->hostintmask,
3149 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3150 hostintmask), retries);
3152 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3153 (u8) watermark, &err);
3155 /* Set bus state according to enable result */
3156 dhdp->busstate = DHD_BUS_DATA;
3158 /* bcmsdh_intr_unmask(bus->sdh); */
3160 bus->intdis = false;
3162 DHD_INTR(("%s: enable SDIO device interrupts\n",
3164 bcmsdh_intr_enable(bus->sdh);
3166 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3167 bcmsdh_intr_disable(bus->sdh);
3173 /* Disable F2 again */
3174 enable = SDIO_FUNC_ENABLE_1;
3175 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3179 /* Restore previous clock setting */
3180 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3183 /* If we didn't come up, turn off backplane clock */
3184 if (dhdp->busstate != DHD_BUS_DATA)
3185 dhdsdio_clkctl(bus, CLK_NONE, false);
3189 dhd_os_sdunlock(bus->dhd);
3194 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3196 bcmsdh_info_t *sdh = bus->sdh;
3197 struct sdpcmd_regs *regs = bus->regs;
3203 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3204 (abort ? "abort command, " : ""),
3205 (rtx ? ", send NAK" : "")));
3208 bcmsdh_abort(sdh, SDIO_FUNC_2);
3210 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3214 /* Wait until the packet has been flushed (device/FIFO stable) */
3215 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3216 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3218 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3220 bus->f1regdata += 2;
3222 if ((hi == 0) && (lo == 0))
3225 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3226 DHD_ERROR(("%s: count growing: last 0x%04x now "
3228 __func__, lastrbc, ((hi << 8) + lo)));
3230 lastrbc = (hi << 8) + lo;
3234 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3235 __func__, lastrbc));
3237 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3238 (0xffff - retries)));
3243 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3245 if (retries <= retry_limit)
3249 /* Clear partial in any case */
3252 /* If we can't reach the device, signal failure */
3253 if (err || bcmsdh_regfail(sdh))
3254 bus->dhd->busstate = DHD_BUS_DOWN;
3258 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3260 bcmsdh_info_t *sdh = bus->sdh;
3265 DHD_TRACE(("%s: Enter\n", __func__));
3267 /* Control data already received in aligned rxctl */
3268 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3272 /* Set rxctl for frame (w/optional alignment) */
3273 bus->rxctl = bus->rxbuf;
3275 bus->rxctl += firstread;
3276 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3278 bus->rxctl += (DHD_SDALIGN - pad);
3279 bus->rxctl -= firstread;
3281 ASSERT(bus->rxctl >= bus->rxbuf);
3283 /* Copy the already-read portion over */
3284 memcpy(bus->rxctl, hdr, firstread);
3285 if (len <= firstread)
3288 /* Copy the full data pkt in gSPI case and process ioctl. */
3289 if (bus->bus == SPI_BUS) {
3290 memcpy(bus->rxctl, hdr, len);
3294 /* Raise rdlen to next SDIO block to avoid tail command */
3295 rdlen = len - firstread;
3296 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3297 pad = bus->blocksize - (rdlen % bus->blocksize);
3298 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3299 ((len + pad) < bus->dhd->maxctl))
3301 } else if (rdlen % DHD_SDALIGN) {
3302 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3305 /* Satisfy length-alignment requirements */
3306 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3307 rdlen = roundup(rdlen, ALIGNMENT);
3309 /* Drop if the read is too big or it exceeds our maximum */
3310 if ((rdlen + firstread) > bus->dhd->maxctl) {
3311 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3312 __func__, rdlen, bus->dhd->maxctl));
3313 bus->dhd->rx_errors++;
3314 dhdsdio_rxfail(bus, false, false);
3318 if ((len - doff) > bus->dhd->maxctl) {
3319 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3321 __func__, len, (len - doff), bus->dhd->maxctl));
3322 bus->dhd->rx_errors++;
3324 dhdsdio_rxfail(bus, false, false);
3328 /* Read remainder of frame body into the rxctl buffer */
3329 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3330 F2SYNC, (bus->rxctl + firstread), rdlen,
3333 ASSERT(sdret != -BCME_PENDING);
3335 /* Control frame failures need retransmission */
3337 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3338 __func__, rdlen, sdret));
3339 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3340 dhdsdio_rxfail(bus, true, true);
3347 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3348 printk(KERN_DEBUG "RxCtrl:\n");
3349 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3353 /* Point to valid data and indicate its length */
3355 bus->rxlen = len - doff;
3358 /* Awake any waiters */
3359 dhd_os_ioctl_resp_wake(bus->dhd);
3362 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3368 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3371 u8 chan, seq, doff, sfdoff;
3375 bool usechain = bus->use_rxchain;
3377 /* If packets, issue read(s) and send up packet chain */
3378 /* Return sequence numbers consumed? */
3380 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3383 /* If there's a descriptor, generate the packet chain */
3385 dhd_os_sdlock_rxq(bus->dhd);
3387 pfirst = plast = pnext = NULL;
3388 dlen = (u16) (bus->glomd->len);
3389 dptr = bus->glomd->data;
3390 if (!dlen || (dlen & 1)) {
3391 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3396 for (totlen = num = 0; dlen; num++) {
3397 /* Get (and move past) next length */
3398 sublen = get_unaligned_le16(dptr);
3399 dlen -= sizeof(u16);
3400 dptr += sizeof(u16);
3401 if ((sublen < SDPCM_HDRLEN) ||
3402 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3403 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3404 __func__, num, sublen));
3408 if (sublen % DHD_SDALIGN) {
3409 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3410 __func__, sublen, DHD_SDALIGN));
3415 /* For last frame, adjust read len so total
3416 is a block multiple */
3419 (roundup(totlen, bus->blocksize) - totlen);
3420 totlen = roundup(totlen, bus->blocksize);
3423 /* Allocate/chain packet for next subframe */
3424 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3425 if (pnext == NULL) {
3426 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3427 "num %d len %d\n", __func__,
3431 ASSERT(!(pnext->prev));
3434 pfirst = plast = pnext;
3437 plast->next = pnext;
3441 /* Adhere to start alignment requirements */
3442 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3445 /* If all allocations succeeded, save packet chain
3448 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3449 "subframes\n", __func__, totlen, num));
3450 if (DHD_GLOM_ON() && bus->nextlen) {
3451 if (totlen != bus->nextlen) {
3452 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3453 __func__, bus->nextlen,
3458 pfirst = pnext = NULL;
3461 brcmu_pkt_buf_free_skb(pfirst);
3466 /* Done with descriptor packet */
3467 brcmu_pkt_buf_free_skb(bus->glomd);
3471 dhd_os_sdunlock_rxq(bus->dhd);
3474 /* Ok -- either we just generated a packet chain,
3475 or had one from before */
3477 if (DHD_GLOM_ON()) {
3478 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3480 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3481 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3482 pnext, (u8 *) (pnext->data),
3483 pnext->len, pnext->len));
3488 dlen = (u16) brcmu_pkttotlen(pfirst);
3490 /* Do an SDIO read for the superframe. Configurable iovar to
3491 * read directly into the chained packet, or allocate a large
3492 * packet and and copy into the chain.
3495 errcode = bcmsdh_recv_buf(bus,
3496 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3497 F2SYNC, (u8 *) pfirst->data, dlen,
3498 pfirst, NULL, NULL);
3499 } else if (bus->dataptr) {
3500 errcode = bcmsdh_recv_buf(bus,
3501 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3502 F2SYNC, bus->dataptr, dlen,
3504 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3506 if (sublen != dlen) {
3507 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3508 __func__, dlen, sublen));
3513 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3518 ASSERT(errcode != -BCME_PENDING);
3520 /* On failure, kill the superframe, allow a couple retries */
3522 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3523 __func__, dlen, errcode));
3524 bus->dhd->rx_errors++;
3526 if (bus->glomerr++ < 3) {
3527 dhdsdio_rxfail(bus, true, true);
3530 dhdsdio_rxfail(bus, true, false);
3531 dhd_os_sdlock_rxq(bus->dhd);
3532 brcmu_pkt_buf_free_skb(bus->glom);
3533 dhd_os_sdunlock_rxq(bus->dhd);
3540 if (DHD_GLOM_ON()) {
3541 printk(KERN_DEBUG "SUPERFRAME:\n");
3542 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3543 pfirst->data, min_t(int, pfirst->len, 48));
3547 /* Validate the superframe header */
3548 dptr = (u8 *) (pfirst->data);
3549 sublen = get_unaligned_le16(dptr);
3550 check = get_unaligned_le16(dptr + sizeof(u16));
3552 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3553 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3554 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3555 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3556 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3557 __func__, bus->nextlen, seq));
3560 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3561 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3564 if ((u16)~(sublen ^ check)) {
3565 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3566 "0x%04x/0x%04x\n", __func__, sublen, check));
3568 } else if (roundup(sublen, bus->blocksize) != dlen) {
3569 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3570 "0x%04x, expect 0x%04x\n",
3572 roundup(sublen, bus->blocksize), dlen));
3574 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3575 SDPCM_GLOM_CHANNEL) {
3576 DHD_ERROR(("%s (superframe): bad channel %d\n",
3578 SDPCM_PACKET_CHANNEL(&dptr
3579 [SDPCM_FRAMETAG_LEN])));
3581 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3582 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3585 } else if ((doff < SDPCM_HDRLEN) ||
3586 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3587 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3589 __func__, doff, sublen,
3590 pfirst->len, SDPCM_HDRLEN));
3594 /* Check sequence number of superframe SW header */
3596 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3597 __func__, seq, rxseq));
3602 /* Check window for sanity */
3603 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3604 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3605 __func__, txmax, bus->tx_seq));
3606 txmax = bus->tx_seq + 2;
3608 bus->tx_max = txmax;
3610 /* Remove superframe header, remember offset */
3611 skb_pull(pfirst, doff);
3614 /* Validate all the subframe headers */
3615 for (num = 0, pnext = pfirst; pnext && !errcode;
3616 num++, pnext = pnext->next) {
3617 dptr = (u8 *) (pnext->data);
3618 dlen = (u16) (pnext->len);
3619 sublen = get_unaligned_le16(dptr);
3620 check = get_unaligned_le16(dptr + sizeof(u16));
3621 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3622 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3624 if (DHD_GLOM_ON()) {
3625 printk(KERN_DEBUG "subframe:\n");
3626 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3631 if ((u16)~(sublen ^ check)) {
3632 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3633 "len/check 0x%04x/0x%04x\n",
3634 __func__, num, sublen, check));
3636 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3637 DHD_ERROR(("%s (subframe %d): length mismatch: "
3638 "len 0x%04x, expect 0x%04x\n",
3639 __func__, num, sublen, dlen));
3641 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3642 (chan != SDPCM_EVENT_CHANNEL)) {
3643 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3644 __func__, num, chan));
3646 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3647 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3648 __func__, num, doff, sublen,
3655 /* Terminate frame on error, request
3657 if (bus->glomerr++ < 3) {
3658 /* Restore superframe header space */
3659 skb_push(pfirst, sfdoff);
3660 dhdsdio_rxfail(bus, true, true);
3663 dhdsdio_rxfail(bus, true, false);
3664 dhd_os_sdlock_rxq(bus->dhd);
3665 brcmu_pkt_buf_free_skb(bus->glom);
3666 dhd_os_sdunlock_rxq(bus->dhd);
3674 /* Basic SD framing looks ok - process each packet (header) */
3675 save_pfirst = pfirst;
3679 dhd_os_sdlock_rxq(bus->dhd);
3680 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3681 pnext = pfirst->next;
3682 pfirst->next = NULL;
3684 dptr = (u8 *) (pfirst->data);
3685 sublen = get_unaligned_le16(dptr);
3686 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3687 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3688 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3690 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3692 __func__, num, pfirst, pfirst->data,
3693 pfirst->len, sublen, chan, seq));
3695 ASSERT((chan == SDPCM_DATA_CHANNEL)
3696 || (chan == SDPCM_EVENT_CHANNEL));
3699 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3700 __func__, seq, rxseq));
3705 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3706 printk(KERN_DEBUG "Rx Subframe Data:\n");
3707 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3712 __skb_trim(pfirst, sublen);
3713 skb_pull(pfirst, doff);
3715 if (pfirst->len == 0) {
3716 brcmu_pkt_buf_free_skb(pfirst);
3718 plast->next = pnext;
3720 ASSERT(save_pfirst == pfirst);
3721 save_pfirst = pnext;
3724 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3726 DHD_ERROR(("%s: rx protocol error\n",
3728 bus->dhd->rx_errors++;
3729 brcmu_pkt_buf_free_skb(pfirst);
3731 plast->next = pnext;
3733 ASSERT(save_pfirst == pfirst);
3734 save_pfirst = pnext;
3739 /* this packet will go up, link back into
3740 chain and count it */
3741 pfirst->next = pnext;
3746 if (DHD_GLOM_ON()) {
3747 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3749 __func__, num, pfirst, pfirst->data,
3750 pfirst->len, pfirst->next,
3752 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3754 min_t(int, pfirst->len, 32));
3756 #endif /* DHD_DEBUG */
3758 dhd_os_sdunlock_rxq(bus->dhd);
3760 dhd_os_sdunlock(bus->dhd);
3761 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3762 dhd_os_sdlock(bus->dhd);
3765 bus->rxglomframes++;
3766 bus->rxglompkts += num;
3771 /* Return true if there may be more frames to read */
3772 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3774 bcmsdh_info_t *sdh = bus->sdh;
3776 u16 len, check; /* Extracted hardware header fields */
3777 u8 chan, seq, doff; /* Extracted software header fields */
3778 u8 fcbits; /* Extracted fcbits from software header */
3780 struct sk_buff *pkt; /* Packet for event or data frames */
3781 u16 pad; /* Number of pad bytes to read */
3782 u16 rdlen; /* Total number of bytes to read */
3783 u8 rxseq; /* Next sequence number to expect */
3784 uint rxleft = 0; /* Remaining number of frames allowed */
3785 int sdret; /* Return code from bcmsdh calls */
3786 u8 txmax; /* Maximum tx sequence offered */
3787 bool len_consistent; /* Result of comparing readahead len and
3791 uint rxcount = 0; /* Total frames read */
3793 #if defined(DHD_DEBUG) || defined(SDTEST)
3794 bool sdtest = false; /* To limit message spew from test mode */
3797 DHD_TRACE(("%s: Enter\n", __func__));
3802 /* Allow pktgen to override maxframes */
3803 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3804 maxframes = bus->pktgen_count;
3809 /* Not finished unless we encounter no more frames indication */
3812 for (rxseq = bus->rx_seq, rxleft = maxframes;
3813 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3814 rxseq++, rxleft--) {
3816 /* Handle glomming separately */
3817 if (bus->glom || bus->glomd) {
3819 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3820 __func__, bus->glomd, bus->glom));
3821 cnt = dhdsdio_rxglom(bus, rxseq);
3822 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3824 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3828 /* Try doing single read if we can */
3829 if (dhd_readahead && bus->nextlen) {
3830 u16 nextlen = bus->nextlen;
3833 if (bus->bus == SPI_BUS) {
3834 rdlen = len = nextlen;
3836 rdlen = len = nextlen << 4;
3838 /* Pad read to blocksize for efficiency */
3839 if (bus->roundup && bus->blocksize
3840 && (rdlen > bus->blocksize)) {
3843 (rdlen % bus->blocksize);
3844 if ((pad <= bus->roundup)
3845 && (pad < bus->blocksize)
3846 && ((rdlen + pad + firstread) <
3849 } else if (rdlen % DHD_SDALIGN) {
3851 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3855 /* We use bus->rxctl buffer in WinXP for initial
3856 * control pkt receives.
3857 * Later we use buffer-poll for data as well
3858 * as control packets.
3859 * This is required because dhd receives full
3860 * frame in gSPI unlike SDIO.
3861 * After the frame is received we have to
3862 * distinguish whether it is data
3863 * or non-data frame.
3865 /* Allocate a packet buffer */
3866 dhd_os_sdlock_rxq(bus->dhd);
3867 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3869 if (bus->bus == SPI_BUS) {
3870 bus->usebufpool = false;
3871 bus->rxctl = bus->rxbuf;
3873 bus->rxctl += firstread;
3874 pad = ((unsigned long)bus->rxctl %
3878 (DHD_SDALIGN - pad);
3879 bus->rxctl -= firstread;
3881 ASSERT(bus->rxctl >= bus->rxbuf);
3883 /* Read the entire frame */
3884 sdret = bcmsdh_recv_buf(bus,
3885 bcmsdh_cur_sbwad(sdh),
3886 SDIO_FUNC_2, F2SYNC,
3890 ASSERT(sdret != -BCME_PENDING);
3892 /* Control frame failures need
3895 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3898 /* dhd.rx_ctlerrs is higher */
3900 dhd_os_sdunlock_rxq(bus->dhd);
3901 dhdsdio_rxfail(bus, true,
3909 request rtx of events */
3910 DHD_ERROR(("%s (nextlen): "
3911 "brcmu_pkt_buf_get_skb "
3913 " len %d rdlen %d expected"
3914 " rxseq %d\n", __func__,
3915 len, rdlen, rxseq));
3916 /* Just go try again w/normal
3918 dhd_os_sdunlock_rxq(bus->dhd);
3922 if (bus->bus == SPI_BUS)
3923 bus->usebufpool = true;
3925 ASSERT(!(pkt->prev));
3926 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3927 rxbuf = (u8 *) (pkt->data);
3928 /* Read the entire frame */
3929 sdret = bcmsdh_recv_buf(bus,
3930 bcmsdh_cur_sbwad(sdh),
3931 SDIO_FUNC_2, F2SYNC,
3935 ASSERT(sdret != -BCME_PENDING);
3938 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3939 __func__, rdlen, sdret));
3940 brcmu_pkt_buf_free_skb(pkt);
3941 bus->dhd->rx_errors++;
3942 dhd_os_sdunlock_rxq(bus->dhd);
3943 /* Force retry w/normal header read.
3944 * Don't attempt NAK for
3947 dhdsdio_rxfail(bus, true,
3954 dhd_os_sdunlock_rxq(bus->dhd);
3956 /* Now check the header */
3957 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3959 /* Extract hardware header fields */
3960 len = get_unaligned_le16(bus->rxhdr);
3961 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3963 /* All zeros means readahead info was bad */
3964 if (!(len | check)) {
3965 DHD_INFO(("%s (nextlen): read zeros in HW "
3966 "header???\n", __func__));
3967 dhdsdio_pktfree2(bus, pkt);
3971 /* Validate check bytes */
3972 if ((u16)~(len ^ check)) {
3973 DHD_ERROR(("%s (nextlen): HW hdr error:"
3974 " nextlen/len/check"
3975 " 0x%04x/0x%04x/0x%04x\n",
3976 __func__, nextlen, len, check));
3978 dhdsdio_rxfail(bus, false, false);
3979 dhdsdio_pktfree2(bus, pkt);
3983 /* Validate frame length */
3984 if (len < SDPCM_HDRLEN) {
3985 DHD_ERROR(("%s (nextlen): HW hdr length "
3986 "invalid: %d\n", __func__, len));
3987 dhdsdio_pktfree2(bus, pkt);
3991 /* Check for consistency withreadahead info */
3992 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3993 if (len_consistent) {
3994 /* Mismatch, force retry w/normal
3995 header (may be >4K) */
3996 DHD_ERROR(("%s (nextlen): mismatch, "
3997 "nextlen %d len %d rnd %d; "
3998 "expected rxseq %d\n",
4000 len, roundup(len, 16), rxseq));
4001 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
4002 dhdsdio_pktfree2(bus, pkt);
4006 /* Extract software header fields */
4007 chan = SDPCM_PACKET_CHANNEL(
4008 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4009 seq = SDPCM_PACKET_SEQUENCE(
4010 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4011 doff = SDPCM_DOFFSET_VALUE(
4012 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4013 txmax = SDPCM_WINDOW_VALUE(
4014 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4017 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4018 SDPCM_NEXTLEN_OFFSET];
4019 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4020 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4021 __func__, bus->nextlen, seq));
4025 bus->dhd->rx_readahead_cnt++;
4027 /* Handle Flow Control */
4028 fcbits = SDPCM_FCMASK_VALUE(
4029 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4031 if (bus->flowcontrol != fcbits) {
4032 if (~bus->flowcontrol & fcbits)
4035 if (bus->flowcontrol & ~fcbits)
4039 bus->flowcontrol = fcbits;
4042 /* Check and update sequence number */
4044 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4045 "%d\n", __func__, seq, rxseq));
4050 /* Check window for sanity */
4051 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4052 DHD_ERROR(("%s: got unlikely tx max %d with "
4054 __func__, txmax, bus->tx_seq));
4055 txmax = bus->tx_seq + 2;
4057 bus->tx_max = txmax;
4060 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4061 printk(KERN_DEBUG "Rx Data:\n");
4062 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4064 } else if (DHD_HDRS_ON()) {
4065 printk(KERN_DEBUG "RxHdr:\n");
4066 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4067 bus->rxhdr, SDPCM_HDRLEN);
4071 if (chan == SDPCM_CONTROL_CHANNEL) {
4072 if (bus->bus == SPI_BUS) {
4073 dhdsdio_read_control(bus, rxbuf, len,
4076 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4078 /* Force retry w/normal header read */
4080 dhdsdio_rxfail(bus, false, true);
4082 dhdsdio_pktfree2(bus, pkt);
4086 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4087 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4092 /* Validate data offset */
4093 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4094 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4095 __func__, doff, len, SDPCM_HDRLEN));
4096 dhdsdio_rxfail(bus, false, false);
4097 dhdsdio_pktfree2(bus, pkt);
4101 /* All done with this one -- now deliver the packet */
4104 /* gSPI frames should not be handled in fractions */
4105 if (bus->bus == SPI_BUS)
4108 /* Read frame header (hardware and software) */
4109 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
4110 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4113 ASSERT(sdret != -BCME_PENDING);
4116 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4119 dhdsdio_rxfail(bus, true, true);
4123 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4124 printk(KERN_DEBUG "RxHdr:\n");
4125 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4126 bus->rxhdr, SDPCM_HDRLEN);
4130 /* Extract hardware header fields */
4131 len = get_unaligned_le16(bus->rxhdr);
4132 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4134 /* All zeros means no more frames */
4135 if (!(len | check)) {
4140 /* Validate check bytes */
4141 if ((u16) ~(len ^ check)) {
4142 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4143 __func__, len, check));
4145 dhdsdio_rxfail(bus, false, false);
4149 /* Validate frame length */
4150 if (len < SDPCM_HDRLEN) {
4151 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4156 /* Extract software header fields */
4157 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4158 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4159 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4160 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4162 /* Validate data offset */
4163 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4164 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4166 __func__, doff, len, SDPCM_HDRLEN, seq));
4169 dhdsdio_rxfail(bus, false, false);
4173 /* Save the readahead length if there is one */
4175 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4176 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4177 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4179 __func__, bus->nextlen, seq));
4183 /* Handle Flow Control */
4184 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4186 if (bus->flowcontrol != fcbits) {
4187 if (~bus->flowcontrol & fcbits)
4190 if (bus->flowcontrol & ~fcbits)
4194 bus->flowcontrol = fcbits;
4197 /* Check and update sequence number */
4199 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4205 /* Check window for sanity */
4206 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4207 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4208 __func__, txmax, bus->tx_seq));
4209 txmax = bus->tx_seq + 2;
4211 bus->tx_max = txmax;
4213 /* Call a separate function for control frames */
4214 if (chan == SDPCM_CONTROL_CHANNEL) {
4215 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4219 ASSERT((chan == SDPCM_DATA_CHANNEL)
4220 || (chan == SDPCM_EVENT_CHANNEL)
4221 || (chan == SDPCM_TEST_CHANNEL)
4222 || (chan == SDPCM_GLOM_CHANNEL));
4224 /* Length to read */
4225 rdlen = (len > firstread) ? (len - firstread) : 0;
4227 /* May pad read to blocksize for efficiency */
4228 if (bus->roundup && bus->blocksize &&
4229 (rdlen > bus->blocksize)) {
4230 pad = bus->blocksize - (rdlen % bus->blocksize);
4231 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4232 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4234 } else if (rdlen % DHD_SDALIGN) {
4235 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4238 /* Satisfy length-alignment requirements */
4239 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4240 rdlen = roundup(rdlen, ALIGNMENT);
4242 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4243 /* Too long -- skip this frame */
4244 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4245 __func__, len, rdlen));
4246 bus->dhd->rx_errors++;
4248 dhdsdio_rxfail(bus, false, false);
4252 dhd_os_sdlock_rxq(bus->dhd);
4253 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4255 /* Give up on data, request rtx of events */
4256 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4257 " chan %d\n", __func__, rdlen, chan));
4258 bus->dhd->rx_dropped++;
4259 dhd_os_sdunlock_rxq(bus->dhd);
4260 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4263 dhd_os_sdunlock_rxq(bus->dhd);
4265 ASSERT(!(pkt->prev));
4267 /* Leave room for what we already read, and align remainder */
4268 ASSERT(firstread < pkt->len);
4269 skb_pull(pkt, firstread);
4270 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4272 /* Read the remaining frame data */
4273 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4274 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4277 ASSERT(sdret != -BCME_PENDING);
4280 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4283 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4285 ? "data" : "test")),
4287 dhd_os_sdlock_rxq(bus->dhd);
4288 brcmu_pkt_buf_free_skb(pkt);
4289 dhd_os_sdunlock_rxq(bus->dhd);
4290 bus->dhd->rx_errors++;
4291 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4295 /* Copy the already-read portion */
4296 skb_push(pkt, firstread);
4297 memcpy(pkt->data, bus->rxhdr, firstread);
4300 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4301 printk(KERN_DEBUG "Rx Data:\n");
4302 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4308 /* Save superframe descriptor and allocate packet frame */
4309 if (chan == SDPCM_GLOM_CHANNEL) {
4310 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4311 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4314 if (DHD_GLOM_ON()) {
4315 printk(KERN_DEBUG "Glom Data:\n");
4316 print_hex_dump_bytes("",
4321 __skb_trim(pkt, len);
4322 ASSERT(doff == SDPCM_HDRLEN);
4323 skb_pull(pkt, SDPCM_HDRLEN);
4326 DHD_ERROR(("%s: glom superframe w/o "
4327 "descriptor!\n", __func__));
4328 dhdsdio_rxfail(bus, false, false);
4333 /* Fill in packet len and prio, deliver upward */
4334 __skb_trim(pkt, len);
4335 skb_pull(pkt, doff);
4338 /* Test channel packets are processed separately */
4339 if (chan == SDPCM_TEST_CHANNEL) {
4340 dhdsdio_testrcv(bus, pkt, seq);
4345 if (pkt->len == 0) {
4346 dhd_os_sdlock_rxq(bus->dhd);
4347 brcmu_pkt_buf_free_skb(pkt);
4348 dhd_os_sdunlock_rxq(bus->dhd);
4350 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4351 DHD_ERROR(("%s: rx protocol error\n", __func__));
4352 dhd_os_sdlock_rxq(bus->dhd);
4353 brcmu_pkt_buf_free_skb(pkt);
4354 dhd_os_sdunlock_rxq(bus->dhd);
4355 bus->dhd->rx_errors++;
4359 /* Unlock during rx call */
4360 dhd_os_sdunlock(bus->dhd);
4361 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4362 dhd_os_sdlock(bus->dhd);
4364 rxcount = maxframes - rxleft;
4366 /* Message if we hit the limit */
4367 if (!rxleft && !sdtest)
4368 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4371 #endif /* DHD_DEBUG */
4372 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4373 /* Back off rxseq if awaiting rtx, update rx_seq */
4376 bus->rx_seq = rxseq;
4381 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4383 struct sdpcmd_regs *regs = bus->regs;
4389 DHD_TRACE(("%s: Enter\n", __func__));
4391 /* Read mailbox data and ack that we did so */
4392 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4393 if (retries <= retry_limit)
4394 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4395 bus->f1regdata += 2;
4397 /* Dongle recomposed rx frames, accept them again */
4398 if (hmb_data & HMB_DATA_NAKHANDLED) {
4399 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4402 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4404 bus->rxskip = false;
4405 intstatus |= I_HMB_FRAME_IND;
4409 * DEVREADY does not occur with gSPI.
4411 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4413 (hmb_data & HMB_DATA_VERSION_MASK) >>
4414 HMB_DATA_VERSION_SHIFT;
4415 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4416 DHD_ERROR(("Version mismatch, dongle reports %d, "
4418 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4420 DHD_INFO(("Dongle ready, protocol version %d\n",
4425 * Flow Control has been moved into the RX headers and this out of band
4426 * method isn't used any more.
4427 * remaining backward compatible with older dongles.
4429 if (hmb_data & HMB_DATA_FC) {
4430 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4431 HMB_DATA_FCDATA_SHIFT;
4433 if (fcbits & ~bus->flowcontrol)
4436 if (bus->flowcontrol & ~fcbits)
4440 bus->flowcontrol = fcbits;
4443 /* Shouldn't be any others */
4444 if (hmb_data & ~(HMB_DATA_DEVREADY |
4445 HMB_DATA_NAKHANDLED |
4448 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4449 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4455 bool dhdsdio_dpc(dhd_bus_t *bus)
4457 bcmsdh_info_t *sdh = bus->sdh;
4458 struct sdpcmd_regs *regs = bus->regs;
4459 u32 intstatus, newstatus = 0;
4461 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4462 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4463 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4464 bool rxdone = true; /* Flag for no more read data */
4465 bool resched = false; /* Flag indicating resched wanted */
4467 DHD_TRACE(("%s: Enter\n", __func__));
4469 /* Start with leftover status bits */
4470 intstatus = bus->intstatus;
4472 dhd_os_sdlock(bus->dhd);
4474 /* If waiting for HTAVAIL, check status */
4475 if (bus->clkstate == CLK_PENDING) {
4477 u8 clkctl, devctl = 0;
4480 /* Check for inconsistent device control */
4482 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4484 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4486 bus->dhd->busstate = DHD_BUS_DOWN;
4488 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4490 #endif /* DHD_DEBUG */
4492 /* Read CSR, if clock on switch to AVAIL, else ignore */
4494 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4497 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4499 bus->dhd->busstate = DHD_BUS_DOWN;
4502 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4505 if (SBSDIO_HTAV(clkctl)) {
4507 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4510 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4512 bus->dhd->busstate = DHD_BUS_DOWN;
4514 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4515 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4518 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4520 bus->dhd->busstate = DHD_BUS_DOWN;
4522 bus->clkstate = CLK_AVAIL;
4530 /* Make sure backplane clock is on */
4531 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4532 if (bus->clkstate == CLK_PENDING)
4535 /* Pending interrupt indicates new device status */
4538 R_SDREG(newstatus, ®s->intstatus, retries);
4540 if (bcmsdh_regfail(bus->sdh))
4542 newstatus &= bus->hostintmask;
4543 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4545 W_SDREG(newstatus, ®s->intstatus, retries);
4550 /* Merge new bits with previous */
4551 intstatus |= newstatus;
4554 /* Handle flow-control change: read new state in case our ack
4555 * crossed another change interrupt. If change still set, assume
4556 * FC ON for safety, let next loop through do the debounce.
4558 if (intstatus & I_HMB_FC_CHANGE) {
4559 intstatus &= ~I_HMB_FC_CHANGE;
4560 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4561 R_SDREG(newstatus, ®s->intstatus, retries);
4562 bus->f1regdata += 2;
4564 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4565 intstatus |= (newstatus & bus->hostintmask);
4568 /* Handle host mailbox indication */
4569 if (intstatus & I_HMB_HOST_INT) {
4570 intstatus &= ~I_HMB_HOST_INT;
4571 intstatus |= dhdsdio_hostmail(bus);
4574 /* Generally don't ask for these, can get CRC errors... */
4575 if (intstatus & I_WR_OOSYNC) {
4576 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4577 intstatus &= ~I_WR_OOSYNC;
4580 if (intstatus & I_RD_OOSYNC) {
4581 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4582 intstatus &= ~I_RD_OOSYNC;
4585 if (intstatus & I_SBINT) {
4586 DHD_ERROR(("Dongle reports SBINT\n"));
4587 intstatus &= ~I_SBINT;
4590 /* Would be active due to wake-wlan in gSPI */
4591 if (intstatus & I_CHIPACTIVE) {
4592 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4593 intstatus &= ~I_CHIPACTIVE;
4596 /* Ignore frame indications if rxskip is set */
4598 intstatus &= ~I_HMB_FRAME_IND;
4600 /* On frame indication, read available frames */
4601 if (PKT_AVAILABLE()) {
4602 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4603 if (rxdone || bus->rxskip)
4604 intstatus &= ~I_HMB_FRAME_IND;
4605 rxlimit -= min(framecnt, rxlimit);
4608 /* Keep still-pending events for next scheduling */
4609 bus->intstatus = intstatus;
4612 #if defined(OOB_INTR_ONLY)
4613 bcmsdh_oob_intr_set(1);
4614 #endif /* (OOB_INTR_ONLY) */
4615 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4616 * or clock availability. (Allows tx loop to check ipend if desired.)
4617 * (Unless register access seems hosed, as we may not be able to ACK...)
4619 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4620 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4621 __func__, rxdone, framecnt));
4622 bus->intdis = false;
4623 bcmsdh_intr_enable(sdh);
4626 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4627 (bus->clkstate == CLK_AVAIL)) {
4631 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4632 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4633 (u32) bus->ctrl_frame_len, NULL,
4635 ASSERT(ret != -BCME_PENDING);
4638 /* On failure, abort the command and
4639 terminate the frame */
4640 DHD_INFO(("%s: sdio error %d, abort command and "
4641 "terminate frame.\n", __func__, ret));
4644 bcmsdh_abort(sdh, SDIO_FUNC_2);
4646 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4647 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4651 for (i = 0; i < 3; i++) {
4653 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4654 SBSDIO_FUNC1_WFRAMEBCHI,
4656 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4657 SBSDIO_FUNC1_WFRAMEBCLO,
4659 bus->f1regdata += 2;
4660 if ((hi == 0) && (lo == 0))
4666 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4668 DHD_INFO(("Return_dpc value is : %d\n", ret));
4669 bus->ctrl_frame_stat = false;
4670 dhd_wait_event_wakeup(bus->dhd);
4672 /* Send queued frames (limit 1 if rx may still be pending) */
4673 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4674 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4676 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4677 framecnt = dhdsdio_sendfromq(bus, framecnt);
4678 txlimit -= framecnt;
4681 /* Resched if events or tx frames are pending,
4682 else await next interrupt */
4683 /* On failed register access, all bets are off:
4684 no resched or interrupts */
4685 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4686 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4687 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4688 bus->dhd->busstate = DHD_BUS_DOWN;
4690 } else if (bus->clkstate == CLK_PENDING) {
4691 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4692 "I_CHIPACTIVE interrupt\n", __func__));
4694 } else if (bus->intstatus || bus->ipend ||
4695 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4696 && DATAOK(bus)) || PKT_AVAILABLE()) {
4700 bus->dpc_sched = resched;
4702 /* If we're done for now, turn off clock request. */
4703 if ((bus->clkstate != CLK_PENDING)
4704 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4705 bus->activity = false;
4706 dhdsdio_clkctl(bus, CLK_NONE, false);
4709 dhd_os_sdunlock(bus->dhd);
4714 bool dhd_bus_dpc(struct dhd_bus *bus)
4718 /* Call the DPC directly. */
4719 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4720 resched = dhdsdio_dpc(bus);
4725 void dhdsdio_isr(void *arg)
4727 dhd_bus_t *bus = (dhd_bus_t *) arg;
4730 DHD_TRACE(("%s: Enter\n", __func__));
4733 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4738 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4739 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4743 /* Count the interrupt call */
4747 /* Shouldn't get this interrupt if we're sleeping? */
4748 if (bus->sleeping) {
4749 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4753 /* Disable additional interrupts (is this needed now)? */
4755 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4757 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4759 bcmsdh_intr_disable(sdh);
4762 #if defined(SDIO_ISR_THREAD)
4763 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4764 while (dhdsdio_dpc(bus))
4767 bus->dpc_sched = true;
4768 dhd_sched_dpc(bus->dhd);
4774 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4776 /* Default to specified length, or full range */
4777 if (dhd_pktgen_len) {
4778 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4779 bus->pktgen_minlen = bus->pktgen_maxlen;
4781 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4782 bus->pktgen_minlen = 0;
4784 bus->pktgen_len = (u16) bus->pktgen_minlen;
4786 /* Default to per-watchdog burst with 10s print time */
4787 bus->pktgen_freq = 1;
4788 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4789 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4791 /* Default to echo mode */
4792 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4793 bus->pktgen_stop = 1;
4796 static void dhdsdio_pktgen(dhd_bus_t *bus)
4798 struct sk_buff *pkt;
4804 /* Display current count if appropriate */
4805 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4806 bus->pktgen_ptick = 0;
4807 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4808 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4811 /* For recv mode, just make sure dongle has started sending */
4812 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4813 if (!bus->pktgen_rcvd)
4814 dhdsdio_sdtest_set(bus, true);
4818 /* Otherwise, generate or request the specified number of packets */
4819 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4820 /* Stop if total has been reached */
4821 if (bus->pktgen_total
4822 && (bus->pktgen_sent >= bus->pktgen_total)) {
4823 bus->pktgen_count = 0;
4827 /* Allocate an appropriate-sized packet */
4828 len = bus->pktgen_len;
4829 pkt = brcmu_pkt_buf_get_skb(
4830 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4833 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4837 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4839 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4841 /* Write test header cmd and extra based on mode */
4842 switch (bus->pktgen_mode) {
4843 case DHD_PKTGEN_ECHO:
4844 *data++ = SDPCM_TEST_ECHOREQ;
4845 *data++ = (u8) bus->pktgen_sent;
4848 case DHD_PKTGEN_SEND:
4849 *data++ = SDPCM_TEST_DISCARD;
4850 *data++ = (u8) bus->pktgen_sent;
4853 case DHD_PKTGEN_RXBURST:
4854 *data++ = SDPCM_TEST_BURST;
4855 *data++ = (u8) bus->pktgen_count;
4859 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4861 brcmu_pkt_buf_free_skb(pkt, true);
4862 bus->pktgen_count = 0;
4866 /* Write test header length field */
4867 *data++ = (len >> 0);
4868 *data++ = (len >> 8);
4870 /* Then fill in the remainder -- N/A for burst,
4872 for (fillbyte = 0; fillbyte < len; fillbyte++)
4874 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4877 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4878 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4879 printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4880 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4881 pkt->len - SDPCM_HDRLEN);
4886 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4888 if (bus->pktgen_stop
4889 && bus->pktgen_stop == bus->pktgen_fail)
4890 bus->pktgen_count = 0;
4894 /* Bump length if not fixed, wrap at max */
4895 if (++bus->pktgen_len > bus->pktgen_maxlen)
4896 bus->pktgen_len = (u16) bus->pktgen_minlen;
4898 /* Special case for burst mode: just send one request! */
4899 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4904 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4906 struct sk_buff *pkt;
4909 /* Allocate the packet */
4910 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4913 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4916 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4917 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4919 /* Fill in the test header */
4920 *data++ = SDPCM_TEST_SEND;
4922 *data++ = (bus->pktgen_maxlen >> 0);
4923 *data++ = (bus->pktgen_maxlen >> 8);
4926 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4930 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4940 /* Check for min length */
4942 if (pktlen < SDPCM_TEST_HDRLEN) {
4943 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4945 brcmu_pkt_buf_free_skb(pkt, false);
4949 /* Extract header fields */
4954 len += *data++ << 8;
4956 /* Check length for relevant commands */
4957 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4958 || cmd == SDPCM_TEST_ECHORSP) {
4959 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4960 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4961 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4962 pktlen, seq, cmd, extra, len));
4963 brcmu_pkt_buf_free_skb(pkt, false);
4968 /* Process as per command */
4970 case SDPCM_TEST_ECHOREQ:
4971 /* Rx->Tx turnaround ok (even on NDIS w/current
4973 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4974 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4978 brcmu_pkt_buf_free_skb(pkt, false);
4983 case SDPCM_TEST_ECHORSP:
4984 if (bus->ext_loop) {
4985 brcmu_pkt_buf_free_skb(pkt, false);
4990 for (offset = 0; offset < len; offset++, data++) {
4991 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4992 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4994 SDPCM_TEST_FILL(offset, extra), *data));
4998 brcmu_pkt_buf_free_skb(pkt, false);
5002 case SDPCM_TEST_DISCARD:
5003 brcmu_pkt_buf_free_skb(pkt, false);
5007 case SDPCM_TEST_BURST:
5008 case SDPCM_TEST_SEND:
5010 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
5011 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
5012 pktlen, seq, cmd, extra, len));
5013 brcmu_pkt_buf_free_skb(pkt, false);
5017 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5018 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
5019 if (bus->pktgen_total
5020 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5021 bus->pktgen_count = 0;
5022 dhdsdio_sdtest_set(bus, false);
5028 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
5032 DHD_TIMER(("%s: Enter\n", __func__));
5036 if (bus->dhd->dongle_reset)
5039 /* Ignore the timer if simulating bus down */
5043 dhd_os_sdlock(bus->dhd);
5045 /* Poll period: check device if appropriate. */
5046 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5049 /* Reset poll tick */
5052 /* Check device if no interrupts */
5053 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5055 if (!bus->dpc_sched) {
5057 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5061 devpend & (INTR_STATUS_FUNC1 |
5065 /* If there is something, make like the ISR and
5071 bcmsdh_intr_disable(bus->sdh);
5073 bus->dpc_sched = true;
5074 dhd_sched_dpc(bus->dhd);
5079 /* Update interrupt tracking */
5080 bus->lastintrs = bus->intrcount;
5083 /* Poll for console output periodically */
5084 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5085 bus->console.count += dhd_watchdog_ms;
5086 if (bus->console.count >= dhd_console_ms) {
5087 bus->console.count -= dhd_console_ms;
5088 /* Make sure backplane clock is on */
5089 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5090 if (dhdsdio_readconsole(bus) < 0)
5091 dhd_console_ms = 0; /* On error,
5095 #endif /* DHD_DEBUG */
5098 /* Generate packets if configured */
5099 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5100 /* Make sure backplane clock is on */
5101 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5102 bus->pktgen_tick = 0;
5103 dhdsdio_pktgen(bus);
5107 /* On idle timeout clear activity flag and/or turn off clock */
5108 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5109 if (++bus->idlecount >= bus->idletime) {
5111 if (bus->activity) {
5112 bus->activity = false;
5113 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5115 dhdsdio_clkctl(bus, CLK_NONE, false);
5120 dhd_os_sdunlock(bus->dhd);
5126 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
5128 dhd_bus_t *bus = dhdp->bus;
5131 struct sk_buff *pkt;
5133 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5134 if (bus->console_addr == 0)
5137 /* Exclusive bus access */
5138 dhd_os_sdlock(bus->dhd);
5140 /* Don't allow input if dongle is in reset */
5141 if (bus->dhd->dongle_reset) {
5142 dhd_os_sdunlock(bus->dhd);
5146 /* Request clock to allow SDIO accesses */
5148 /* No pend allowed since txpkt is called later, ht clk has to be on */
5149 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5151 /* Zero cbuf_index */
5152 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5153 val = cpu_to_le32(0);
5154 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5158 /* Write message into cbuf */
5159 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5160 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5164 /* Write length into vcons_in */
5165 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5166 val = cpu_to_le32(msglen);
5167 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5171 /* Bump dongle by sending an empty event pkt.
5172 * sdpcm_sendup (RX) checks for virtual console input.
5174 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5175 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5176 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5179 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5180 bus->activity = false;
5181 dhdsdio_clkctl(bus, CLK_NONE, true);
5184 dhd_os_sdunlock(bus->dhd);
5188 #endif /* DHD_DEBUG */
5190 static bool dhdsdio_chipmatch(u16 chipid)
5192 if (chipid == BCM4325_CHIP_ID)
5194 if (chipid == BCM4329_CHIP_ID)
5196 if (chipid == BCM4319_CHIP_ID)
5201 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5202 u16 slot, u16 func, uint bustype, void *regsva,
5208 /* Init global variables at run-time, not as part of the declaration.
5209 * This is required to support init/de-init of the driver.
5211 * of globals as part of the declaration results in non-deterministic
5212 * behavior since the value of the globals may be different on the
5213 * first time that the driver is initialized vs subsequent
5216 dhd_txbound = DHD_TXBOUND;
5217 dhd_rxbound = DHD_RXBOUND;
5218 dhd_alignctl = true;
5220 dhd_readahead = true;
5222 dhd_dongle_memsize = 0;
5223 dhd_txminmax = DHD_TXMINMAX;
5229 DHD_TRACE(("%s: Enter\n", __func__));
5230 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5232 /* We make assumptions about address window mappings */
5233 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5235 /* BCMSDH passes venid and devid based on CIS parsing -- but
5237 * means early parse could fail, so here we should get either an ID
5238 * we recognize OR (-1) indicating we must request power first.
5240 /* Check the Vendor ID */
5243 case PCI_VENDOR_ID_BROADCOM:
5246 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5250 /* Check the Device ID and make sure it's one that we support */
5252 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5253 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5254 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5255 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5257 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5258 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5259 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5261 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5263 case BCM4319_D11N_ID: /* 4319 802.11n id */
5264 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5265 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5266 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5269 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5274 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5275 __func__, venid, devid));
5279 /* Allocate private bus interface state */
5280 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5282 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5286 bus->cl_devid = (u16) devid;
5288 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5289 bus->usebufpool = false; /* Use bufpool if allocated,
5290 else use locally malloced rxbuf */
5292 /* attempt to attach to the dongle */
5293 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5294 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5298 /* Attach to the dhd/OS/network interface */
5299 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5301 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5305 /* Allocate buffers */
5306 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5307 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5311 if (!(dhdsdio_probe_init(bus, sdh))) {
5312 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5316 /* Register interrupt callback, but mask it (not operational yet). */
5317 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5319 bcmsdh_intr_disable(sdh);
5320 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5322 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5326 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5328 DHD_INFO(("%s: completed!!\n", __func__));
5330 /* if firmware path present try to download and bring up bus */
5331 ret = dhd_bus_start(bus->dhd);
5333 if (ret == -ENOLINK) {
5334 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5338 /* Ok, have the per-port tell the stack we're open for business */
5339 if (dhd_net_attach(bus->dhd, 0) != 0) {
5340 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5347 dhdsdio_release(bus);
5352 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5357 bus->alp_only = true;
5359 /* Return the window to backplane enumeration space for core access */
5360 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5361 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5364 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5365 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5367 #endif /* DHD_DEBUG */
5370 * Force PLL off until dhdsdio_chip_attach()
5371 * programs PLL control regs
5374 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5375 DHD_INIT_CLKCTL1, &err);
5378 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5381 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5382 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5383 "0x%02x read 0x%02x\n",
5384 err, DHD_INIT_CLKCTL1, clkctl));
5388 if (dhdsdio_chip_attach(bus, regsva)) {
5389 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5393 bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5395 if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5396 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5397 __func__, bus->ci->chip));
5401 dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5403 /* Get info on the ARM and SOCRAM cores... */
5404 if (!DHD_NOPMU(bus)) {
5405 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5406 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5407 bus->orig_ramsize = bus->ci->ramsize;
5408 if (!(bus->orig_ramsize)) {
5409 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5413 bus->ramsize = bus->orig_ramsize;
5414 if (dhd_dongle_memsize)
5415 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5417 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5418 bus->ramsize, bus->orig_ramsize));
5421 bus->regs = (void *)bus->ci->buscorebase;
5423 /* Set core control so an SDIO reset does a backplane reset */
5424 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5426 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5428 /* Locate an appropriately-aligned portion of hdrbuf */
5429 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5431 /* Set the poll and/or interrupt flags */
5432 bus->intr = (bool) dhd_intr;
5433 bus->poll = (bool) dhd_poll;
5443 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5445 DHD_TRACE(("%s: Enter\n", __func__));
5447 if (bus->dhd->maxctl) {
5449 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5450 ALIGNMENT) + DHD_SDALIGN;
5451 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5452 if (!(bus->rxbuf)) {
5453 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5454 __func__, bus->rxblen));
5459 /* Allocate buffer to receive glomed packet */
5460 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5461 if (!(bus->databuf)) {
5462 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5463 __func__, MAX_DATA_BUF));
5464 /* release rxbuf which was already located as above */
5470 /* Align the buffer */
5471 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5473 bus->databuf + (DHD_SDALIGN -
5474 ((unsigned long)bus->databuf % DHD_SDALIGN));
5476 bus->dataptr = bus->databuf;
5484 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5488 DHD_TRACE(("%s: Enter\n", __func__));
5491 dhdsdio_pktgen_init(bus);
5494 /* Disable F2 to clear any intermediate frame state on the dongle */
5495 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
5498 bus->dhd->busstate = DHD_BUS_DOWN;
5499 bus->sleeping = false;
5500 bus->rxflow = false;
5501 bus->prev_rxlim_hit = 0;
5503 /* Done with backplane-dependent accesses, can drop clock... */
5504 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5506 /* ...and initialize clock/power states */
5507 bus->clkstate = CLK_SDONLY;
5508 bus->idletime = (s32) dhd_idletime;
5509 bus->idleclock = DHD_IDLE_ACTIVE;
5511 /* Query the F2 block size, set roundup accordingly */
5513 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5514 &bus->blocksize, sizeof(s32), false) != 0) {
5516 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5518 DHD_INFO(("%s: Initial value for %s is %d\n",
5519 __func__, "sd_blocksize", bus->blocksize));
5521 bus->roundup = min(max_roundup, bus->blocksize);
5523 /* Query if bus module supports packet chaining,
5524 default to use if supported */
5525 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5526 &bus->sd_rxchain, sizeof(s32),
5528 bus->sd_rxchain = false;
5530 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5532 (bus->sd_rxchain ? "supports" : "does not support")));
5534 bus->use_rxchain = (bool) bus->sd_rxchain;
5540 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5543 bus->fw_path = fw_path;
5544 bus->nv_path = nv_path;
5546 ret = dhdsdio_download_firmware(bus, bus->sdh);
5552 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5556 /* Download the firmware */
5557 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5559 ret = _dhdsdio_download_firmware(bus) == 0;
5561 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5566 /* Detach and free everything */
5567 static void dhdsdio_release(dhd_bus_t *bus)
5569 DHD_TRACE(("%s: Enter\n", __func__));
5572 /* De-register interrupt handler */
5573 bcmsdh_intr_disable(bus->sdh);
5574 bcmsdh_intr_dereg(bus->sdh);
5577 dhd_detach(bus->dhd);
5578 dhdsdio_release_dongle(bus);
5582 dhdsdio_release_malloc(bus);
5587 DHD_TRACE(("%s: Disconnected\n", __func__));
5590 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5592 DHD_TRACE(("%s: Enter\n", __func__));
5594 if (bus->dhd && bus->dhd->dongle_reset)
5599 bus->rxctl = bus->rxbuf = NULL;
5603 kfree(bus->databuf);
5604 bus->databuf = NULL;
5607 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5609 DHD_TRACE(("%s: Enter\n", __func__));
5611 if (bus->dhd && bus->dhd->dongle_reset)
5615 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5616 dhdsdio_clkctl(bus, CLK_NONE, false);
5617 dhdsdio_chip_detach(bus);
5618 if (bus->vars && bus->varsz)
5623 DHD_TRACE(("%s: Disconnected\n", __func__));
5626 static void dhdsdio_disconnect(void *ptr)
5628 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5630 DHD_TRACE(("%s: Enter\n", __func__));
5634 dhdsdio_release(bus);
5637 DHD_TRACE(("%s: Disconnected\n", __func__));
5640 /* Register/Unregister functions are called by the main DHD entry
5641 * point (e.g. module insertion) to link with the bus driver, in
5642 * order to look for or await the device.
5645 static bcmsdh_driver_t dhd_sdio = {
5650 int dhd_bus_register(void)
5652 DHD_TRACE(("%s: Enter\n", __func__));
5654 return bcmsdh_register(&dhd_sdio);
5657 void dhd_bus_unregister(void)
5659 DHD_TRACE(("%s: Enter\n", __func__));
5661 bcmsdh_unregister();
5664 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5670 u8 *memblock = NULL, *memptr;
5672 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5674 image = dhd_os_open_image(fw_path);
5678 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5679 if (memblock == NULL) {
5680 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5681 __func__, MEMBLOCK));
5684 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5686 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5688 /* Download image */
5690 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5691 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5693 DHD_ERROR(("%s: error %d on writing %d membytes at "
5694 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5705 dhd_os_close_image(image);
5711 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5712 * and ending in a NUL.
5713 * Removes carriage returns, empty lines, comment lines, and converts
5715 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5719 static uint process_nvram_vars(char *varbuf, uint len)
5728 findNewline = false;
5731 for (n = 0; n < len; n++) {
5734 if (varbuf[n] == '\r')
5736 if (findNewline && varbuf[n] != '\n')
5738 findNewline = false;
5739 if (varbuf[n] == '#') {
5743 if (varbuf[n] == '\n') {
5753 buf_len = dp - varbuf;
5755 while (dp < varbuf + n)
5762 EXAMPLE: nvram_array
5765 Use carriage return at the end of each assignment,
5766 and an empty string with
5767 carriage return at the end of array.
5770 unsigned char nvram_array[] = {"name1=value1\n",
5771 "name2=value2\n", "\n"};
5772 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5774 Search "EXAMPLE: nvram_array" to see how the array is activated.
5777 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5779 bus->nvram_params = nvram_params;
5782 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5787 char *memblock = NULL;
5790 bool nvram_file_exists;
5792 nv_path = bus->nv_path;
5794 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5795 if (!nvram_file_exists && (bus->nvram_params == NULL))
5798 if (nvram_file_exists) {
5799 image = dhd_os_open_image(nv_path);
5804 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5805 if (memblock == NULL) {
5806 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5807 __func__, MEMBLOCK));
5811 /* Download variables */
5812 if (nvram_file_exists) {
5813 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5815 len = strlen(bus->nvram_params);
5816 ASSERT(len <= MEMBLOCK);
5819 memcpy(memblock, bus->nvram_params, len);
5822 if (len > 0 && len < MEMBLOCK) {
5823 bufp = (char *)memblock;
5825 len = process_nvram_vars(bufp, len);
5829 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5831 DHD_ERROR(("%s: error downloading vars: %d\n",
5832 __func__, bcmerror));
5835 DHD_ERROR(("%s: error reading nvram file: %d\n",
5844 dhd_os_close_image(image);
5849 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5853 bool embed = false; /* download embedded firmware */
5854 bool dlok = false; /* download firmware succeeded */
5856 /* Out immediately if no image to download */
5857 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5860 /* Keep arm in reset */
5861 if (dhdsdio_download_state(bus, true)) {
5862 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5866 /* External image takes precedence if specified */
5867 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5868 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5869 DHD_ERROR(("%s: dongle image file download failed\n",
5878 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5882 /* EXAMPLE: nvram_array */
5883 /* If a valid nvram_arry is specified as above, it can be passed
5885 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5887 /* External nvram takes precedence if specified */
5888 if (dhdsdio_download_nvram(bus)) {
5889 DHD_ERROR(("%s: dongle nvram file download failed\n",
5893 /* Take arm out of reset */
5894 if (dhdsdio_download_state(bus, false)) {
5895 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5908 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5909 u8 *buf, uint nbytes, struct sk_buff *pkt,
5910 bcmsdh_cmplt_fn_t complete, void *handle)
5912 return bcmsdh_send_buf
5913 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5917 uint dhd_bus_chip(struct dhd_bus *bus)
5919 ASSERT(bus->ci != NULL);
5920 return bus->ci->chip;
5923 void *dhd_bus_pub(struct dhd_bus *bus)
5928 void *dhd_bus_txq(struct dhd_bus *bus)
5933 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5935 return SDPCM_HDRLEN;
5938 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5946 if (!bus->dhd->dongle_reset) {
5947 /* Expect app to have torn down any
5948 connection before calling */
5949 /* Stop the bus, disable F2 */
5950 dhd_bus_stop(bus, false);
5952 /* Clean tx/rx buffer pointers,
5953 detach from the dongle */
5954 dhdsdio_release_dongle(bus);
5956 bus->dhd->dongle_reset = true;
5957 bus->dhd->up = false;
5959 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5960 /* App can now remove power from device */
5964 /* App must have restored power to device before calling */
5966 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5968 if (bus->dhd->dongle_reset) {
5970 /* Reset SD client */
5971 bcmsdh_reset(bus->sdh);
5973 /* Attempt to re-attach & download */
5974 if (dhdsdio_probe_attach(bus, bus->sdh,
5975 (u32 *) SI_ENUM_BASE,
5977 /* Attempt to download binary to the dongle */
5978 if (dhdsdio_probe_init
5980 && dhdsdio_download_firmware(bus,
5983 /* Re-init bus, enable F2 transfer */
5984 dhd_bus_init((dhd_pub_t *) bus->dhd,
5987 #if defined(OOB_INTR_ONLY)
5988 dhd_enable_oob_intr(bus, true);
5989 #endif /* defined(OOB_INTR_ONLY) */
5991 bus->dhd->dongle_reset = false;
5992 bus->dhd->up = true;
5994 DHD_TRACE(("%s: WLAN ON DONE\n",
6001 bcmerror = -EISCONN;
6002 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6003 "is on\n", __func__));
6011 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
6017 * Chipid is assume to be at offset 0 from regs arg
6018 * For different chiptypes or old sdio hosts w/o chipcommon,
6019 * other ways of recognition should be added here.
6021 ci->cccorebase = (u32)regs;
6022 regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
6023 ci->chip = regdata & CID_ID_MASK;
6024 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6026 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6027 __func__, ci->chip, ci->chiprev));
6029 /* Address of cores for new chips should be added here */
6031 case BCM4329_CHIP_ID:
6032 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6033 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6034 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6035 ci->ramsize = BCM4329_RAMSIZE;
6038 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6039 __func__, ci->chip));
6043 regdata = bcmsdh_reg_read(sdh,
6044 CORE_SB(ci->cccorebase, sbidhigh), 4);
6045 ci->ccrev = SBCOREREV(regdata);
6047 regdata = bcmsdh_reg_read(sdh,
6048 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6049 ci->pmurev = regdata & PCAP_REV_MASK;
6051 regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6052 ci->buscorerev = SBCOREREV(regdata);
6053 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6055 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6056 __func__, ci->ccrev, ci->pmurev,
6057 ci->buscorerev, ci->buscoretype));
6059 /* get chipcommon capabilites */
6060 ci->cccaps = bcmsdh_reg_read(sdh,
6061 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6067 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6071 regdata = bcmsdh_reg_read(sdh,
6072 CORE_SB(corebase, sbtmstatelow), 4);
6073 if (regdata & SBTML_RESET)
6076 regdata = bcmsdh_reg_read(sdh,
6077 CORE_SB(corebase, sbtmstatelow), 4);
6078 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6080 * set target reject and spin until busy is clear
6081 * (preserve core-specific bits)
6083 regdata = bcmsdh_reg_read(sdh,
6084 CORE_SB(corebase, sbtmstatelow), 4);
6085 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6086 regdata | SBTML_REJ);
6088 regdata = bcmsdh_reg_read(sdh,
6089 CORE_SB(corebase, sbtmstatelow), 4);
6091 SPINWAIT((bcmsdh_reg_read(sdh,
6092 CORE_SB(corebase, sbtmstatehigh), 4) &
6093 SBTMH_BUSY), 100000);
6095 regdata = bcmsdh_reg_read(sdh,
6096 CORE_SB(corebase, sbtmstatehigh), 4);
6097 if (regdata & SBTMH_BUSY)
6098 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6100 regdata = bcmsdh_reg_read(sdh,
6101 CORE_SB(corebase, sbidlow), 4);
6102 if (regdata & SBIDL_INIT) {
6103 regdata = bcmsdh_reg_read(sdh,
6104 CORE_SB(corebase, sbimstate), 4) |
6106 bcmsdh_reg_write(sdh,
6107 CORE_SB(corebase, sbimstate), 4,
6109 regdata = bcmsdh_reg_read(sdh,
6110 CORE_SB(corebase, sbimstate), 4);
6112 SPINWAIT((bcmsdh_reg_read(sdh,
6113 CORE_SB(corebase, sbimstate), 4) &
6117 /* set reset and reject while enabling the clocks */
6118 bcmsdh_reg_write(sdh,
6119 CORE_SB(corebase, sbtmstatelow), 4,
6120 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6121 SBTML_REJ | SBTML_RESET));
6122 regdata = bcmsdh_reg_read(sdh,
6123 CORE_SB(corebase, sbtmstatelow), 4);
6126 /* clear the initiator reject bit */
6127 regdata = bcmsdh_reg_read(sdh,
6128 CORE_SB(corebase, sbidlow), 4);
6129 if (regdata & SBIDL_INIT) {
6130 regdata = bcmsdh_reg_read(sdh,
6131 CORE_SB(corebase, sbimstate), 4) &
6133 bcmsdh_reg_write(sdh,
6134 CORE_SB(corebase, sbimstate), 4,
6139 /* leave reset and reject asserted */
6140 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6141 (SBTML_REJ | SBTML_RESET));
6146 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6148 struct chip_info *ci;
6152 DHD_TRACE(("%s: Enter\n", __func__));
6154 /* alloc chip_info_t */
6155 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6157 DHD_ERROR(("%s: malloc failed!\n", __func__));
6161 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6163 /* bus/core/clk setup for register access */
6164 /* Try forcing SDIO core to do ALPAvail request only */
6165 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6166 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6169 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6173 /* If register supported, wait for ALPAvail and then force ALP */
6174 /* This may take up to 15 milliseconds */
6175 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6176 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6177 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6179 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6180 SBSDIO_FUNC1_CHIPCLKCSR,
6182 !SBSDIO_ALPAV(clkval)),
6183 PMU_MAX_TRANSITION_DLY);
6184 if (!SBSDIO_ALPAV(clkval)) {
6185 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6190 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6192 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6193 SBSDIO_FUNC1_CHIPCLKCSR,
6197 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6198 __func__, clkset, clkval));
6203 /* Also, disable the extra SDIO pull-ups */
6204 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6207 err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6212 * Make sure any on-chip ARM is off (in case strapping is wrong),
6213 * or downloaded code was already running.
6215 dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6217 bcmsdh_reg_write(bus->sdh,
6218 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6219 bcmsdh_reg_write(bus->sdh,
6220 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6222 /* Disable F2 to clear any intermediate frame state on the dongle */
6223 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6224 SDIO_FUNC_ENABLE_1, NULL);
6226 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6227 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6230 /* Done with backplane-dependent accesses, can drop clock... */
6231 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6243 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6248 * Must do the disable sequence first to work for
6249 * arbitrary current core state.
6251 dhdsdio_chip_disablecore(sdh, corebase);
6254 * Now do the initialization sequence.
6255 * set reset while enabling the clock and
6256 * forcing them on throughout the core
6258 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6259 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6263 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6264 if (regdata & SBTMH_SERR)
6265 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6267 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6268 if (regdata & (SBIM_IBE | SBIM_TO))
6269 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6270 regdata & ~(SBIM_IBE | SBIM_TO));
6272 /* clear reset and allow it to propagate throughout the core */
6273 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6274 (SICF_FGC << SBTML_SICF_SHIFT) |
6275 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6278 /* leave clock enabled */
6279 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6280 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6284 /* SDIO Pad drive strength to select value mappings */
6285 struct sdiod_drive_str {
6286 u8 strength; /* Pad Drive Strength in mA */
6287 u8 sel; /* Chip-specific select value */
6290 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6291 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6299 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6300 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6311 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6312 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6324 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6327 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6328 struct sdiod_drive_str *str_tab = NULL;
6333 if (!(bus->ci->cccaps & CC_CAP_PMU))
6336 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6337 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6338 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6339 str_mask = 0x30000000;
6342 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6343 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6344 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6345 str_mask = 0x00003800;
6348 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6349 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6350 str_mask = 0x00003800;
6354 DHD_ERROR(("No SDIO Drive strength init"
6355 "done for chip %s rev %d pmurev %d\n",
6356 brcmu_chipname(bus->ci->chip, chn, 8),
6357 bus->ci->chiprev, bus->ci->pmurev));
6361 if (str_tab != NULL) {
6362 u32 drivestrength_sel = 0;
6366 for (i = 0; str_tab[i].strength != 0; i++) {
6367 if (drivestrength >= str_tab[i].strength) {
6368 drivestrength_sel = str_tab[i].sel;
6373 bcmsdh_reg_write(bus->sdh,
6374 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6376 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6377 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6378 cc_data_temp &= ~str_mask;
6379 drivestrength_sel <<= str_shift;
6380 cc_data_temp |= drivestrength_sel;
6381 bcmsdh_reg_write(bus->sdh,
6382 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6385 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6386 drivestrength, cc_data_temp));
6391 dhdsdio_chip_detach(struct dhd_bus *bus)
6393 DHD_TRACE(("%s: Enter\n", __func__));
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