2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
29 #include <brcmu_wifi.h>
30 #include <brcmu_utils.h>
35 /* register access macros */
42 /* register access macros */
46 bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
50 __typeof(*(r)) __osl_v; \
51 __asm__ __volatile__("sync"); \
52 __osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
53 __asm__ __volatile__("sync"); \
58 #define W_REG(r, v) do { \
59 bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v)); \
61 #else /* __BIG_ENDIAN */
63 bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
64 #define W_REG(r, v) do { \
65 bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v); \
67 #endif /* __BIG_ENDIAN */
71 * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
72 * transactions. As a fix, a read after write is performed on certain places
73 * in the code. Older chips and the newer 5357 family don't require this fix.
75 #define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
77 #define W_REG_FLUSH(r, v) W_REG((r), (v))
80 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
81 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
83 #define SET_REG(r, mask, val) \
84 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
88 /* ARM trap handling */
90 /* Trap types defined by ARM (see arminc.h) */
92 /* Trap locations in lo memory */
94 #define FIRST_TRAP TR_RST
95 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
97 #if defined(__ARM_ARCH_4T__)
98 #define MAX_TRAP_TYPE (TR_FIQ + 1)
99 #elif defined(__ARM_ARCH_7M__)
100 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
101 #endif /* __ARM_ARCH_7M__ */
103 /* The trap structure is defined here as offsets for assembly */
109 #define TR_REG(n) (TR_REGS + (n) * 4)
110 #define TR_SP TR_REG(13)
111 #define TR_LR TR_REG(14)
112 #define TR_PC TR_REG(15)
114 #define TRAP_T_SIZE 80
116 typedef struct _trap_struct {
139 #define CBUF_LEN (128)
141 #define LOG_BUF_LEN 1024
144 u32 buf; /* Can't be pointer on (64-bit) hosts */
147 char *_buf_compat; /* Redundant pointer for backward compat. */
152 * When there is no UART (e.g. Quickturn),
153 * the host should write a complete
154 * input line directly into cbuf and then write
155 * the length into vcons_in.
156 * This may also be used when there is a real UART
157 * (at risk of conflicting with
158 * the real UART). vcons_out is currently unused.
160 volatile uint vcons_in;
161 volatile uint vcons_out;
163 /* Output (logging) buffer
164 * Console output is written to a ring buffer log_buf at index log_idx.
165 * The host may read the output when it sees log_idx advance.
166 * Output will be lost if the output wraps around faster than the host
171 /* Console input line buffer
172 * Characters are read one at a time into cbuf
173 * until <CR> is received, then
174 * the buffer is processed as a command line.
175 * Also used for virtual UART.
181 #endif /* DHD_DEBUG */
182 #include <chipcommon.h>
186 #include <dngl_stats.h>
189 #include <dhd_proto.h>
194 #ifndef DHDSDIO_MEM_DUMP_FNAME
195 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
198 #define TXQLEN 2048 /* bulk tx queue length */
199 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
200 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
203 #define TXRETRIES 2 /* # of retries for tx frames */
205 #if defined(CONFIG_MACH_SANDGATE2G)
206 #define DHD_RXBOUND 250 /* Default for max rx frames in
209 #define DHD_RXBOUND 50 /* Default for max rx frames in
211 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
213 #define DHD_TXBOUND 20 /* Default for max tx frames in
216 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
218 #define MEMBLOCK 2048 /* Block size used for downloading
220 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
221 biggest possible glom */
223 /* Packet alignment for most efficient SDIO (can change based on platform) */
225 #define DHD_SDALIGN 32
227 #if !ISPOWEROF2(DHD_SDALIGN)
228 #error DHD_SDALIGN is not a power of 2!
231 #ifndef DHD_FIRSTREAD
232 #define DHD_FIRSTREAD 32
234 #if !ISPOWEROF2(DHD_FIRSTREAD)
235 #error DHD_FIRSTREAD is not a power of 2!
238 /* Total length of frame header for dongle protocol */
239 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
241 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
243 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
247 * Software allocation of To SB Mailbox resources
250 /* tosbmailbox bits corresponding to intstatus bits */
251 #define SMB_NAK (1 << 0) /* Frame NAK */
252 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
253 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
254 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
256 /* tosbmailboxdata */
257 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
260 * Software allocation of To Host Mailbox resources
264 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
265 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
266 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
267 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
269 /* tohostmailboxdata */
270 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
271 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
272 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
273 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
275 #define HMB_DATA_FCDATA_MASK 0xff000000
276 #define HMB_DATA_FCDATA_SHIFT 24
278 #define HMB_DATA_VERSION_MASK 0x00ff0000
279 #define HMB_DATA_VERSION_SHIFT 16
282 * Software-defined protocol header
285 /* Current protocol version */
286 #define SDPCM_PROT_VERSION 4
288 /* SW frame header */
289 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
291 #define SDPCM_CHANNEL_MASK 0x00000f00
292 #define SDPCM_CHANNEL_SHIFT 8
293 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
295 #define SDPCM_NEXTLEN_OFFSET 2
297 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
298 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
299 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
300 #define SDPCM_DOFFSET_MASK 0xff000000
301 #define SDPCM_DOFFSET_SHIFT 24
302 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
303 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
304 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
305 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
307 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
309 /* logical channel numbers */
310 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
311 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
312 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
313 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
314 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
316 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
318 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
320 /* For TEST_CHANNEL packets, define another 4-byte header */
321 #define SDPCM_TEST_HDRLEN 4 /*
322 * Generally: Cmd(1), Ext(1), Len(2);
323 * Semantics of Ext byte depend on
324 * command. Len is current or requested
325 * frame length, not including test
326 * header; sent little-endian.
328 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
329 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
330 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
331 #define SDPCM_TEST_BURST 0x04 /*
332 * Receiver to send a burst.
333 * Ext is a frame count
335 #define SDPCM_TEST_SEND 0x05 /*
336 * Receiver sets send mode.
337 * Ext is boolean on/off
340 /* Handy macro for filling in datagen packets with a pattern */
341 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
344 * Shared structure between dongle and the host.
345 * The structure contains pointers to trap or assert information.
347 #define SDPCM_SHARED_VERSION 0x0002
348 #define SDPCM_SHARED_VERSION_MASK 0x00FF
349 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
350 #define SDPCM_SHARED_ASSERT 0x0200
351 #define SDPCM_SHARED_TRAP 0x0400
354 /* Space for header read, limit for data packets */
356 #define MAX_HDR_READ 32
358 #if !ISPOWEROF2(MAX_HDR_READ)
359 #error MAX_HDR_READ is not a power of 2!
362 #define MAX_RX_DATASZ 2048
364 /* Maximum milliseconds to wait for F2 to come up */
365 #define DHD_WAIT_F2RDY 3000
367 /* Bump up limit on waiting for HT to account for first startup;
368 * if the image is doing a CRC calculation before programming the PMU
369 * for HT availability, it could take a couple hundred ms more, so
370 * max out at a 1 second (1000000us).
372 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
373 #undef PMU_MAX_TRANSITION_DLY
374 #define PMU_MAX_TRANSITION_DLY 1000000
377 /* Value for ChipClockCSR during initial setup */
378 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
379 SBSDIO_ALP_AVAIL_REQ)
380 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
382 /* Flags for SDH calls */
383 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
386 #define SBIM_IBE 0x20000 /* inbanderror */
387 #define SBIM_TO 0x40000 /* timeout */
388 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
389 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
392 #define SBTML_RESET 0x0001 /* reset */
393 #define SBTML_REJ_MASK 0x0006 /* reject field */
394 #define SBTML_REJ 0x0002 /* reject */
395 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
397 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
400 #define SBTMH_SERR 0x0001 /* serror */
401 #define SBTMH_INT 0x0002 /* interrupt */
402 #define SBTMH_BUSY 0x0004 /* busy */
403 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
405 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
408 #define SBIDL_INIT 0x80 /* initiator */
411 #define SBIDH_RC_MASK 0x000f /* revision code */
412 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
413 #define SBIDH_RCE_SHIFT 8
414 #define SBCOREREV(sbidh) \
415 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
416 #define SBIDH_CC_MASK 0x8ff0 /* core code */
417 #define SBIDH_CC_SHIFT 4
418 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
419 #define SBIDH_VC_SHIFT 16
422 * Conversion of 802.1D priority to precedence level
424 #define PRIO2PREC(prio) \
425 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
428 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
429 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
432 /* Core reg address translation */
433 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
434 #define CORE_BUS_REG(base, field) \
435 (base + offsetof(struct sdpcmd_regs, field))
436 #define CORE_SB(base, field) \
437 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
440 /* Device console log buffer state */
441 typedef struct dhd_console {
442 uint count; /* Poll interval msec counter */
443 uint log_addr; /* Log struct address (fixed) */
444 rte_log_t log; /* Log struct (host copy) */
445 uint bufsize; /* Size of log buffer */
446 u8 *buf; /* Log buffer (host copy) */
447 uint last; /* Last buffer read index */
449 #endif /* DHD_DEBUG */
451 struct sdpcm_shared {
455 u32 assert_file_addr;
457 u32 console_addr; /* Address of rte_cons_t */
463 /* misc chip info needed by some of the routines */
479 /* Private data for SDIO bus interaction */
480 typedef struct dhd_bus {
483 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
484 struct chip_info *ci; /* Chip info struct */
485 char *vars; /* Variables (from CIS and/or other) */
486 uint varsz; /* Size of variables buffer */
487 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
489 struct sdpcmd_regs *regs; /* SDIO core */
490 uint sdpcmrev; /* SDIO core revision */
491 uint armrev; /* CPU core revision */
492 uint ramrev; /* SOCRAM core revision */
493 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
494 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
496 u32 bus; /* gSPI or SDIO bus */
497 u32 hostintmask; /* Copy of Host Interrupt Mask */
498 u32 intstatus; /* Intstatus bits (events) pending */
499 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
500 bool fcstate; /* State of dongle flow-control */
502 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
503 char *fw_path; /* module_param: path to firmware image */
504 char *nv_path; /* module_param: path to nvram vars file */
505 const char *nvram_params; /* user specified nvram params. */
507 uint blocksize; /* Block size of SDIO transfers */
508 uint roundup; /* Max roundup limit */
510 struct pktq txq; /* Queue length used for flow-control */
511 u8 flowcontrol; /* per prio flow control bitmask */
512 u8 tx_seq; /* Transmit sequence number (next) */
513 u8 tx_max; /* Maximum transmit sequence allowed */
515 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
516 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
517 u16 nextlen; /* Next Read Len from last header */
518 u8 rx_seq; /* Receive sequence number (expected) */
519 bool rxskip; /* Skip receive (awaiting NAK ACK) */
521 struct sk_buff *glomd; /* Packet containing glomming descriptor */
522 struct sk_buff *glom; /* Packet chain for glommed superframe */
523 uint glomerr; /* Glom packet read errors */
525 u8 *rxbuf; /* Buffer for receiving control packets */
526 uint rxblen; /* Allocated length of rxbuf */
527 u8 *rxctl; /* Aligned pointer into rxbuf */
528 u8 *databuf; /* Buffer for receiving big glom packet */
529 u8 *dataptr; /* Aligned pointer into databuf */
530 uint rxlen; /* Length of valid data in buffer */
532 u8 sdpcm_ver; /* Bus protocol reported by dongle */
534 bool intr; /* Use interrupts */
535 bool poll; /* Use polling */
536 bool ipend; /* Device interrupt is pending */
537 bool intdis; /* Interrupts disabled by isr */
538 uint intrcount; /* Count of device interrupt callbacks */
539 uint lastintrs; /* Count as of last watchdog timer */
540 uint spurious; /* Count of spurious interrupts */
541 uint pollrate; /* Ticks between device polls */
542 uint polltick; /* Tick counter */
543 uint pollcnt; /* Count of active polls */
546 dhd_console_t console; /* Console output polling support */
547 uint console_addr; /* Console address from shared struct */
548 #endif /* DHD_DEBUG */
550 uint regfails; /* Count of R_REG/W_REG failures */
552 uint clkstate; /* State of sd and backplane clock(s) */
553 bool activity; /* Activity flag for clock down */
554 s32 idletime; /* Control for activity timeout */
555 s32 idlecount; /* Activity timeout counter */
556 s32 idleclock; /* How to set bus driver when idle */
557 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
558 bool use_rxchain; /* If dhd should use PKT chains */
559 bool sleeping; /* Is SDIO bus sleeping? */
560 bool rxflow_mode; /* Rx flow control mode */
561 bool rxflow; /* Is rx flow control on */
562 uint prev_rxlim_hit; /* Is prev rx limit exceeded
563 (per dpc schedule) */
564 bool alp_only; /* Don't use HT clock (ALP only) */
565 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
569 /* external loopback */
573 /* pktgen configuration */
574 uint pktgen_freq; /* Ticks between bursts */
575 uint pktgen_count; /* Packets to send each burst */
576 uint pktgen_print; /* Bursts between count displays */
577 uint pktgen_total; /* Stop after this many */
578 uint pktgen_minlen; /* Minimum packet data len */
579 uint pktgen_maxlen; /* Maximum packet data len */
580 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
581 uint pktgen_stop; /* Number of tx failures causing stop */
583 /* active pktgen fields */
584 uint pktgen_tick; /* Tick counter for bursts */
585 uint pktgen_ptick; /* Burst counter for printing */
586 uint pktgen_sent; /* Number of test packets generated */
587 uint pktgen_rcvd; /* Number of test packets received */
588 uint pktgen_fail; /* Number of failed send attempts */
589 u16 pktgen_len; /* Length of next packet to send */
592 /* Some additional counters */
593 uint tx_sderrs; /* Count of tx attempts with sd errors */
594 uint fcqueued; /* Tx packets that got queued */
595 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
596 uint rx_toolong; /* Receive frames too long to receive */
597 uint rxc_errors; /* SDIO errors when reading control frames */
598 uint rx_hdrfail; /* SDIO errors on header reads */
599 uint rx_badhdr; /* Bad received headers (roosync?) */
600 uint rx_badseq; /* Mismatched rx sequence number */
601 uint fc_rcvd; /* Number of flow-control events received */
602 uint fc_xoff; /* Number which turned on flow-control */
603 uint fc_xon; /* Number which turned off flow-control */
604 uint rxglomfail; /* Failed deglom attempts */
605 uint rxglomframes; /* Number of glom frames (superframes) */
606 uint rxglompkts; /* Number of packets from glom frames */
607 uint f2rxhdrs; /* Number of header reads */
608 uint f2rxdata; /* Number of frame data reads */
609 uint f2txdata; /* Number of f2 frame writes */
610 uint f1regdata; /* Number of f1 register accesses */
614 bool ctrl_frame_stat;
617 typedef volatile struct _sbconfig {
619 u32 sbipsflag; /* initiator port ocp slave flag */
621 u32 sbtpsflag; /* target port ocp slave flag */
623 u32 sbtmerrloga; /* (sonics >= 2.3) */
625 u32 sbtmerrlog; /* (sonics >= 2.3) */
627 u32 sbadmatch3; /* address match3 */
629 u32 sbadmatch2; /* address match2 */
631 u32 sbadmatch1; /* address match1 */
633 u32 sbimstate; /* initiator agent state */
634 u32 sbintvec; /* interrupt mask */
635 u32 sbtmstatelow; /* target state */
636 u32 sbtmstatehigh; /* target state */
637 u32 sbbwa0; /* bandwidth allocation table0 */
639 u32 sbimconfiglow; /* initiator configuration */
640 u32 sbimconfighigh; /* initiator configuration */
641 u32 sbadmatch0; /* address match0 */
643 u32 sbtmconfiglow; /* target configuration */
644 u32 sbtmconfighigh; /* target configuration */
645 u32 sbbconfig; /* broadcast configuration */
647 u32 sbbstate; /* broadcast state */
649 u32 sbactcnfg; /* activate configuration */
651 u32 sbflagst; /* current sbflags */
653 u32 sbidlow; /* identification */
654 u32 sbidhigh; /* identification */
660 #define CLK_PENDING 2 /* Not used yet */
663 #define DHD_NOPMU(dhd) (false)
666 static int qcount[NUMPRIO];
667 static int tx_packets[NUMPRIO];
668 #endif /* DHD_DEBUG */
670 /* Deferred transmit */
671 const uint dhd_deferred_tx = 1;
673 extern uint dhd_watchdog_ms;
674 extern void dhd_os_wd_timer(void *bus, uint wdtick);
681 /* override the RAM size if possible */
682 #define DONGLE_MIN_MEMSIZE (128 * 1024)
683 int dhd_dongle_memsize;
685 static bool dhd_alignctl;
689 static bool retrydata;
690 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
692 static const uint watermark = 8;
693 static const uint firstread = DHD_FIRSTREAD;
695 #define HDATLEN (firstread - (SDPCM_HDRLEN))
697 /* Retry count for register access failures */
698 static const uint retry_limit = 2;
700 /* Force even SD lengths (some host controllers mess up on odd bytes) */
701 static bool forcealign;
705 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
706 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
709 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
710 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
711 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
712 #define PKTALIGN(_p, _len, _align) \
715 datalign = (unsigned long)((_p)->data); \
716 datalign = roundup(datalign, (_align)) - datalign; \
717 ASSERT(datalign < (_align)); \
718 ASSERT((_p)->len >= ((_len) + datalign)); \
720 skb_pull((_p), datalign); \
721 __skb_trim((_p), (_len)); \
724 /* Limit on rounding up frames */
725 static const uint max_roundup = 512;
727 /* Try doing readahead */
728 static bool dhd_readahead;
730 /* To check if there's window offered */
731 #define DATAOK(bus) \
732 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
733 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
735 /* Macros to get register read/write status */
736 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
737 #define R_SDREG(regvar, regaddr, retryvar) \
741 regvar = R_REG(regaddr); \
742 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
744 bus->regfails += (retryvar-1); \
745 if (retryvar > retry_limit) { \
746 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
747 __func__, __LINE__)); \
753 #define W_SDREG(regval, regaddr, retryvar) \
757 W_REG(regaddr, regval); \
758 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
760 bus->regfails += (retryvar-1); \
761 if (retryvar > retry_limit) \
762 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
763 __func__, __LINE__)); \
767 #define DHD_BUS SDIO_BUS
769 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
771 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
774 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
775 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
779 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
780 static int dhdsdio_mem_dump(dhd_bus_t *bus);
781 #endif /* DHD_DEBUG */
782 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
784 static void dhdsdio_release(dhd_bus_t *bus);
785 static void dhdsdio_release_malloc(dhd_bus_t *bus);
786 static void dhdsdio_disconnect(void *ptr);
787 static bool dhdsdio_chipmatch(u16 chipid);
788 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
789 void *regsva, u16 devid);
790 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
791 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
792 static void dhdsdio_release_dongle(dhd_bus_t *bus);
794 static uint process_nvram_vars(char *varbuf, uint len);
796 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
797 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
798 uint flags, u8 *buf, uint nbytes,
799 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
802 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
803 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
805 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
806 static int dhdsdio_download_nvram(struct dhd_bus *bus);
807 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
808 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
809 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
810 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
812 static void dhdsdio_chip_detach(struct dhd_bus *bus);
814 /* Packet free applicable unconditionally for sdio and sdspi.
815 * Conditional if bufpool was present for gspi bus.
817 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
819 dhd_os_sdlock_rxq(bus->dhd);
820 if ((bus->bus != SPI_BUS) || bus->usebufpool)
821 brcmu_pkt_buf_free_skb(pkt);
822 dhd_os_sdunlock_rxq(bus->dhd);
825 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
827 s32 min_size = DONGLE_MIN_MEMSIZE;
828 /* Restrict the memsize to user specified limit */
829 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
830 dhd_dongle_memsize, min_size));
831 if ((dhd_dongle_memsize > min_size) &&
832 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
833 bus->ramsize = dhd_dongle_memsize;
836 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
839 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
840 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
842 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
843 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
845 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
846 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
851 /* Turn backplane clock on or off */
852 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
855 u8 clkctl, clkreq, devctl;
858 DHD_TRACE(("%s: Enter\n", __func__));
860 #if defined(OOB_INTR_ONLY)
867 /* Request HT Avail */
869 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
871 if ((bus->ci->chip == BCM4329_CHIP_ID)
872 && (bus->ci->chiprev == 0))
873 clkreq |= SBSDIO_FORCE_ALP;
875 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
878 DHD_ERROR(("%s: HT Avail request error: %d\n",
883 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
884 && (bus->ci->buscorerev == 9))) {
886 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
889 /* Check current status */
891 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
894 DHD_ERROR(("%s: HT Avail read error: %d\n",
899 /* Go to pending and await interrupt if appropriate */
900 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
901 /* Allow only clock-available interrupt */
903 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
906 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
911 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
912 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
914 DHD_INFO(("CLKCTL: set PENDING\n"));
915 bus->clkstate = CLK_PENDING;
918 } else if (bus->clkstate == CLK_PENDING) {
919 /* Cancel CA-only interrupt filter */
921 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
923 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
924 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
928 /* Otherwise, wait here (polling) for HT Avail */
929 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
930 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
932 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
933 SBSDIO_FUNC1_CHIPCLKCSR,
935 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
936 PMU_MAX_TRANSITION_DLY);
939 DHD_ERROR(("%s: HT Avail request error: %d\n",
943 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
944 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
945 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
949 /* Mark clock available */
950 bus->clkstate = CLK_AVAIL;
951 DHD_INFO(("CLKCTL: turned ON\n"));
953 #if defined(DHD_DEBUG)
954 if (bus->alp_only == true) {
955 #if !defined(BCMLXSDMMC)
956 if (!SBSDIO_ALPONLY(clkctl)) {
957 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
960 #endif /* !defined(BCMLXSDMMC) */
962 if (SBSDIO_ALPONLY(clkctl)) {
963 DHD_ERROR(("%s: HT Clock should be on.\n",
967 #endif /* defined (DHD_DEBUG) */
969 bus->activity = true;
973 if (bus->clkstate == CLK_PENDING) {
974 /* Cancel CA-only interrupt filter */
976 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
978 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
979 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
983 bus->clkstate = CLK_SDONLY;
984 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
986 DHD_INFO(("CLKCTL: turned OFF\n"));
988 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
996 /* Change idle/active SD state */
997 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
999 DHD_TRACE(("%s: Enter\n", __func__));
1002 bus->clkstate = CLK_SDONLY;
1004 bus->clkstate = CLK_NONE;
1009 /* Transition SD and backplane clock readiness */
1010 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
1013 uint oldstate = bus->clkstate;
1014 #endif /* DHD_DEBUG */
1016 DHD_TRACE(("%s: Enter\n", __func__));
1018 /* Early exit if we're already there */
1019 if (bus->clkstate == target) {
1020 if (target == CLK_AVAIL) {
1021 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1022 bus->activity = true;
1029 /* Make sure SD clock is available */
1030 if (bus->clkstate == CLK_NONE)
1031 dhdsdio_sdclk(bus, true);
1032 /* Now request HT Avail on the backplane */
1033 dhdsdio_htclk(bus, true, pendok);
1034 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1035 bus->activity = true;
1039 /* Remove HT request, or bring up SD clock */
1040 if (bus->clkstate == CLK_NONE)
1041 dhdsdio_sdclk(bus, true);
1042 else if (bus->clkstate == CLK_AVAIL)
1043 dhdsdio_htclk(bus, false, false);
1045 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
1046 bus->clkstate, target));
1047 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
1051 /* Make sure to remove HT request */
1052 if (bus->clkstate == CLK_AVAIL)
1053 dhdsdio_htclk(bus, false, false);
1054 /* Now remove the SD clock */
1055 dhdsdio_sdclk(bus, false);
1056 dhd_os_wd_timer(bus->dhd, 0);
1060 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1061 #endif /* DHD_DEBUG */
1066 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1068 bcmsdh_info_t *sdh = bus->sdh;
1069 struct sdpcmd_regs *regs = bus->regs;
1072 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1073 (sleep ? "SLEEP" : "WAKE"),
1074 (bus->sleeping ? "SLEEP" : "WAKE")));
1076 /* Done if we're already in the requested state */
1077 if (sleep == bus->sleeping)
1080 /* Going to sleep: set the alarm and turn off the lights... */
1082 /* Don't sleep if something is pending */
1083 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1086 /* Disable SDIO interrupts (no longer interested) */
1087 bcmsdh_intr_disable(bus->sdh);
1089 /* Make sure the controller has the bus up */
1090 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1092 /* Tell device to start using OOB wakeup */
1093 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1094 if (retries > retry_limit)
1095 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1097 /* Turn off our contribution to the HT clock request */
1098 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1100 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1101 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1103 /* Isolate the bus */
1104 if (bus->ci->chip != BCM4329_CHIP_ID
1105 && bus->ci->chip != BCM4319_CHIP_ID) {
1106 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1107 SBSDIO_DEVCTL_PADS_ISO, NULL);
1111 bus->sleeping = true;
1114 /* Waking up: bus power up is ok, set local state */
1116 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1119 /* Force pad isolation off if possible
1120 (in case power never toggled) */
1121 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1122 && (bus->ci->buscorerev >= 10))
1123 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
1126 /* Make sure the controller has the bus up */
1127 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1129 /* Send misc interrupt to indicate OOB not needed */
1130 W_SDREG(0, ®s->tosbmailboxdata, retries);
1131 if (retries <= retry_limit)
1132 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1134 if (retries > retry_limit)
1135 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1137 /* Make sure we have SD bus access */
1138 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1141 bus->sleeping = false;
1143 /* Enable interrupts again */
1144 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1145 bus->intdis = false;
1146 bcmsdh_intr_enable(bus->sdh);
1153 #if defined(OOB_INTR_ONLY)
1154 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1157 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1159 sdpcmd_regs_t *regs = bus->regs;
1162 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1163 if (enable == true) {
1165 /* Tell device to start using OOB wakeup */
1166 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1167 if (retries > retry_limit)
1168 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1171 /* Send misc interrupt to indicate OOB not needed */
1172 W_SDREG(0, ®s->tosbmailboxdata, retries);
1173 if (retries <= retry_limit)
1174 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1177 /* Turn off our contribution to the HT clock request */
1178 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1179 #endif /* !defined(HW_OOB) */
1181 #endif /* defined(OOB_INTR_ONLY) */
1183 #define BUS_WAKE(bus) \
1185 if ((bus)->sleeping) \
1186 dhdsdio_bussleep((bus), false); \
1189 /* Writes a HW/SW header into the packet and sends it. */
1190 /* Assumes: (a) header space already there, (b) caller holds lock */
1191 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1200 struct sk_buff *new;
1203 DHD_TRACE(("%s: Enter\n", __func__));
1207 if (bus->dhd->dongle_reset) {
1212 frame = (u8 *) (pkt->data);
1214 /* Add alignment padding, allocate new packet if needed */
1215 pad = ((unsigned long)frame % DHD_SDALIGN);
1217 if (skb_headroom(pkt) < pad) {
1218 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1219 __func__, skb_headroom(pkt), pad));
1220 bus->dhd->tx_realloc++;
1221 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1223 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1225 __func__, pkt->len + DHD_SDALIGN));
1230 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1231 memcpy(new->data, pkt->data, pkt->len);
1233 brcmu_pkt_buf_free_skb(pkt);
1234 /* free the pkt if canned one is not used */
1237 frame = (u8 *) (pkt->data);
1238 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1242 frame = (u8 *) (pkt->data);
1244 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1245 memset(frame, 0, pad + SDPCM_HDRLEN);
1248 ASSERT(pad < DHD_SDALIGN);
1250 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1251 len = (u16) (pkt->len);
1252 *(u16 *) frame = cpu_to_le16(len);
1253 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1255 /* Software tag: channel, sequence number, data offset */
1257 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1259 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1261 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1262 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1265 tx_packets[pkt->priority]++;
1266 if (DHD_BYTES_ON() &&
1267 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1268 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1269 printk(KERN_DEBUG "Tx Frame:\n");
1270 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1271 } else if (DHD_HDRS_ON()) {
1272 printk(KERN_DEBUG "TxHdr:\n");
1273 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1274 frame, min_t(u16, len, 16));
1278 /* Raise len to next SDIO block to eliminate tail command */
1279 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1280 u16 pad = bus->blocksize - (len % bus->blocksize);
1281 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1283 if (pad <= skb_tailroom(pkt))
1284 #endif /* NOTUSED */
1286 } else if (len % DHD_SDALIGN) {
1287 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1290 /* Some controllers have trouble with odd bytes -- round to even */
1291 if (forcealign && (len & (ALIGNMENT - 1))) {
1293 if (skb_tailroom(pkt))
1295 len = roundup(len, ALIGNMENT);
1298 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1305 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1306 F2SYNC, frame, len, pkt, NULL, NULL);
1308 ASSERT(ret != -BCME_PENDING);
1311 /* On failure, abort the command
1312 and terminate the frame */
1313 DHD_INFO(("%s: sdio error %d, abort command and "
1314 "terminate frame.\n", __func__, ret));
1317 bcmsdh_abort(sdh, SDIO_FUNC_2);
1318 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1319 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1323 for (i = 0; i < 3; i++) {
1325 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1326 SBSDIO_FUNC1_WFRAMEBCHI,
1328 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1329 SBSDIO_FUNC1_WFRAMEBCLO,
1331 bus->f1regdata += 2;
1332 if ((hi == 0) && (lo == 0))
1338 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1340 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1343 /* restore pkt buffer pointer before calling tx complete routine */
1344 skb_pull(pkt, SDPCM_HDRLEN + pad);
1345 dhd_os_sdunlock(bus->dhd);
1346 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1347 dhd_os_sdlock(bus->dhd);
1350 brcmu_pkt_buf_free_skb(pkt);
1355 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1360 DHD_TRACE(("%s: Enter\n", __func__));
1365 /* Push the test header if doing loopback */
1366 if (bus->ext_loop) {
1368 skb_push(pkt, SDPCM_TEST_HDRLEN);
1370 *data++ = SDPCM_TEST_ECHOREQ;
1371 *data++ = (u8) bus->loopid++;
1372 *data++ = (datalen >> 0);
1373 *data++ = (datalen >> 8);
1374 datalen += SDPCM_TEST_HDRLEN;
1378 /* Add space for the header */
1379 skb_push(pkt, SDPCM_HDRLEN);
1380 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1382 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1384 /* Check for existing queue, current flow-control,
1385 pending event, or pending clock */
1386 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1387 || bus->dpc_sched || (!DATAOK(bus))
1388 || (bus->flowcontrol & NBITVAL(prec))
1389 || (bus->clkstate != CLK_AVAIL)) {
1390 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1391 pktq_len(&bus->txq)));
1394 /* Priority based enq */
1395 dhd_os_sdlock_txq(bus->dhd);
1396 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1397 skb_pull(pkt, SDPCM_HDRLEN);
1398 dhd_txcomplete(bus->dhd, pkt, false);
1399 brcmu_pkt_buf_free_skb(pkt);
1400 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1405 dhd_os_sdunlock_txq(bus->dhd);
1407 if (pktq_len(&bus->txq) >= TXHI)
1408 dhd_txflowcontrol(bus->dhd, 0, ON);
1411 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1412 qcount[prec] = pktq_plen(&bus->txq, prec);
1414 /* Schedule DPC if needed to send queued packet(s) */
1415 if (dhd_deferred_tx && !bus->dpc_sched) {
1416 bus->dpc_sched = true;
1417 dhd_sched_dpc(bus->dhd);
1420 /* Lock: we're about to use shared data/code (and SDIO) */
1421 dhd_os_sdlock(bus->dhd);
1423 /* Otherwise, send it now */
1425 /* Make sure back plane ht clk is on, no pending allowed */
1426 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1429 DHD_TRACE(("%s: calling txpkt\n", __func__));
1430 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1432 ret = dhdsdio_txpkt(bus, pkt,
1433 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1434 SDPCM_DATA_CHANNEL), true);
1437 bus->dhd->tx_errors++;
1439 bus->dhd->dstats.tx_bytes += datalen;
1441 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1442 bus->activity = false;
1443 dhdsdio_clkctl(bus, CLK_NONE, true);
1446 dhd_os_sdunlock(bus->dhd);
1452 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1454 struct sk_buff *pkt;
1457 int ret = 0, prec_out;
1462 dhd_pub_t *dhd = bus->dhd;
1463 struct sdpcmd_regs *regs = bus->regs;
1465 DHD_TRACE(("%s: Enter\n", __func__));
1467 tx_prec_map = ~bus->flowcontrol;
1469 /* Send frames until the limit or some other event */
1470 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1471 dhd_os_sdlock_txq(bus->dhd);
1472 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1474 dhd_os_sdunlock_txq(bus->dhd);
1477 dhd_os_sdunlock_txq(bus->dhd);
1478 datalen = pkt->len - SDPCM_HDRLEN;
1481 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1483 ret = dhdsdio_txpkt(bus, pkt,
1484 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1485 SDPCM_DATA_CHANNEL), true);
1488 bus->dhd->tx_errors++;
1490 bus->dhd->dstats.tx_bytes += datalen;
1492 /* In poll mode, need to check for other events */
1493 if (!bus->intr && cnt) {
1494 /* Check device status, signal pending interrupt */
1495 R_SDREG(intstatus, ®s->intstatus, retries);
1497 if (bcmsdh_regfail(bus->sdh))
1499 if (intstatus & bus->hostintmask)
1504 /* Deflow-control stack if needed */
1505 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1506 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1507 dhd_txflowcontrol(dhd, 0, OFF);
1512 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1518 bcmsdh_info_t *sdh = bus->sdh;
1523 DHD_TRACE(("%s: Enter\n", __func__));
1525 if (bus->dhd->dongle_reset)
1528 /* Back the pointer to make a room for bus header */
1529 frame = msg - SDPCM_HDRLEN;
1530 len = (msglen += SDPCM_HDRLEN);
1532 /* Add alignment padding (optional for ctl frames) */
1534 doff = ((unsigned long)frame % DHD_SDALIGN);
1539 memset(frame, 0, doff + SDPCM_HDRLEN);
1541 ASSERT(doff < DHD_SDALIGN);
1543 doff += SDPCM_HDRLEN;
1545 /* Round send length to next SDIO block */
1546 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1547 u16 pad = bus->blocksize - (len % bus->blocksize);
1548 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1550 } else if (len % DHD_SDALIGN) {
1551 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1554 /* Satisfy length-alignment requirements */
1555 if (forcealign && (len & (ALIGNMENT - 1)))
1556 len = roundup(len, ALIGNMENT);
1558 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1560 /* Need to lock here to protect txseq and SDIO tx calls */
1561 dhd_os_sdlock(bus->dhd);
1565 /* Make sure backplane clock is on */
1566 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1568 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1569 *(u16 *) frame = cpu_to_le16((u16) msglen);
1570 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1572 /* Software tag: channel, sequence number, data offset */
1574 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1576 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1577 SDPCM_DOFFSET_MASK);
1578 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1579 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1582 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1583 __func__, bus->tx_max, bus->tx_seq));
1584 bus->ctrl_frame_stat = true;
1586 bus->ctrl_frame_buf = frame;
1587 bus->ctrl_frame_len = len;
1589 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1591 if (bus->ctrl_frame_stat == false) {
1592 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1595 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1602 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1603 printk(KERN_DEBUG "Tx Frame:\n");
1604 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1606 } else if (DHD_HDRS_ON()) {
1607 printk(KERN_DEBUG "TxHdr:\n");
1608 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1609 frame, min_t(u16, len, 16));
1614 bus->ctrl_frame_stat = false;
1616 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1617 SDIO_FUNC_2, F2SYNC, frame, len,
1620 ASSERT(ret != -BCME_PENDING);
1623 /* On failure, abort the command and
1624 terminate the frame */
1625 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1629 bcmsdh_abort(sdh, SDIO_FUNC_2);
1631 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1632 SBSDIO_FUNC1_FRAMECTRL,
1636 for (i = 0; i < 3; i++) {
1638 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1639 SBSDIO_FUNC1_WFRAMEBCHI,
1641 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1642 SBSDIO_FUNC1_WFRAMEBCLO,
1644 bus->f1regdata += 2;
1645 if ((hi == 0) && (lo == 0))
1652 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1654 } while ((ret < 0) && retries++ < TXRETRIES);
1657 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1658 bus->activity = false;
1659 dhdsdio_clkctl(bus, CLK_NONE, true);
1662 dhd_os_sdunlock(bus->dhd);
1665 bus->dhd->tx_ctlerrs++;
1667 bus->dhd->tx_ctlpkts++;
1669 return ret ? -EIO : 0;
1672 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1678 DHD_TRACE(("%s: Enter\n", __func__));
1680 if (bus->dhd->dongle_reset)
1683 /* Wait until control frame is available */
1684 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1686 dhd_os_sdlock(bus->dhd);
1688 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1690 dhd_os_sdunlock(bus->dhd);
1693 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1694 __func__, rxlen, msglen));
1695 } else if (timeleft == 0) {
1696 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1698 dhd_os_sdlock(bus->dhd);
1699 dhdsdio_checkdied(bus, NULL, 0);
1700 dhd_os_sdunlock(bus->dhd);
1701 #endif /* DHD_DEBUG */
1702 } else if (pending == true) {
1703 DHD_CTL(("%s: cancelled\n", __func__));
1704 return -ERESTARTSYS;
1706 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1708 dhd_os_sdlock(bus->dhd);
1709 dhdsdio_checkdied(bus, NULL, 0);
1710 dhd_os_sdunlock(bus->dhd);
1711 #endif /* DHD_DEBUG */
1715 bus->dhd->rx_ctlpkts++;
1717 bus->dhd->rx_ctlerrs++;
1719 return rxlen ? (int)rxlen : -ETIMEDOUT;
1758 const struct brcmu_iovar dhdsdio_iovars[] = {
1759 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1760 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1761 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1762 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1763 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1764 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1765 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1766 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1767 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1768 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1769 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1770 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1771 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1772 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1773 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1774 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1776 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1778 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1780 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1782 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1784 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1786 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1788 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1790 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1793 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1795 #endif /* DHD_DEBUG */
1796 #endif /* DHD_DEBUG */
1798 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1800 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1808 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1813 brcmu_bprintf(strbuf, "%s N/A", desc);
1816 q2 = (100 * (num - (q1 * div))) / div;
1817 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1821 void dhd_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1823 dhd_bus_t *bus = dhdp->bus;
1825 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1826 brcmu_bprintf(strbuf,
1827 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1828 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1829 brcmu_bprintf(strbuf,
1830 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1831 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1832 bus->rxskip, bus->rxlen, bus->rx_seq);
1833 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1834 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1835 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1836 bus->pollrate, bus->pollcnt, bus->regfails);
1838 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1839 brcmu_bprintf(strbuf,
1840 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1841 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1843 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1844 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1845 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1846 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1847 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1848 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1849 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1851 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1852 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1854 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1855 (bus->f2rxhdrs + bus->f2rxdata));
1856 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1858 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1859 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1860 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1862 brcmu_bprintf(strbuf, "\n");
1864 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1865 bus->dhd->rx_packets);
1866 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1868 brcmu_bprintf(strbuf, "\n");
1870 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1872 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1874 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1875 (bus->f2txdata + bus->f1regdata));
1876 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1878 brcmu_bprintf(strbuf, "\n");
1880 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1881 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1882 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1883 dhd_dump_pct(strbuf, ", pkts/f1sd",
1884 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1886 dhd_dump_pct(strbuf, ", pkts/sd",
1887 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1888 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1890 dhd_dump_pct(strbuf, ", pkts/int",
1891 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1893 brcmu_bprintf(strbuf, "\n\n");
1897 if (bus->pktgen_count) {
1898 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1899 brcmu_bprintf(strbuf,
1900 "freq %d count %d print %d total %d min %d len %d\n",
1901 bus->pktgen_freq, bus->pktgen_count,
1902 bus->pktgen_print, bus->pktgen_total,
1903 bus->pktgen_minlen, bus->pktgen_maxlen);
1904 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1905 bus->pktgen_sent, bus->pktgen_rcvd,
1910 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1912 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1913 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1915 #endif /* DHD_DEBUG */
1916 brcmu_bprintf(strbuf,
1917 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1918 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1922 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1924 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1926 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1927 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1928 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1929 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1930 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1931 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1935 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1937 dhd_pktgen_t pktgen;
1939 pktgen.version = DHD_PKTGEN_VERSION;
1940 pktgen.freq = bus->pktgen_freq;
1941 pktgen.count = bus->pktgen_count;
1942 pktgen.print = bus->pktgen_print;
1943 pktgen.total = bus->pktgen_total;
1944 pktgen.minlen = bus->pktgen_minlen;
1945 pktgen.maxlen = bus->pktgen_maxlen;
1946 pktgen.numsent = bus->pktgen_sent;
1947 pktgen.numrcvd = bus->pktgen_rcvd;
1948 pktgen.numfail = bus->pktgen_fail;
1949 pktgen.mode = bus->pktgen_mode;
1950 pktgen.stop = bus->pktgen_stop;
1952 memcpy(arg, &pktgen, sizeof(pktgen));
1957 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1959 dhd_pktgen_t pktgen;
1960 uint oldcnt, oldmode;
1962 memcpy(&pktgen, arg, sizeof(pktgen));
1963 if (pktgen.version != DHD_PKTGEN_VERSION)
1966 oldcnt = bus->pktgen_count;
1967 oldmode = bus->pktgen_mode;
1969 bus->pktgen_freq = pktgen.freq;
1970 bus->pktgen_count = pktgen.count;
1971 bus->pktgen_print = pktgen.print;
1972 bus->pktgen_total = pktgen.total;
1973 bus->pktgen_minlen = pktgen.minlen;
1974 bus->pktgen_maxlen = pktgen.maxlen;
1975 bus->pktgen_mode = pktgen.mode;
1976 bus->pktgen_stop = pktgen.stop;
1978 bus->pktgen_tick = bus->pktgen_ptick = 0;
1979 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1980 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1982 /* Clear counts for a new pktgen (mode change, or was stopped) */
1983 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1984 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1991 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1998 /* Determine initial transfer parameters */
1999 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2000 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2001 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2005 /* Set the backplane window to include the start address */
2006 bcmerror = dhdsdio_set_siaddr_window(bus, address);
2008 DHD_ERROR(("%s: window change failed\n", __func__));
2012 /* Do the transfer(s) */
2014 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
2015 __func__, (write ? "write" : "read"), dsize,
2016 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
2018 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
2020 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2024 /* Adjust for next transfer (if any) */
2029 bcmerror = dhdsdio_set_siaddr_window(bus, address);
2031 DHD_ERROR(("%s: window change failed\n",
2036 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2041 /* Return the window to backplane enumeration space for core access */
2042 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
2043 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2044 __func__, bcmsdh_cur_sbwad(bus->sdh)));
2051 static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2056 /* Read last word in memory to determine address of
2057 sdpcm_shared structure */
2058 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
2062 addr = le32_to_cpu(addr);
2064 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2067 * Check if addr is valid.
2068 * NVRAM length at the end of memory should have been overwritten.
2070 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2071 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2076 /* Read rte_shared structure */
2077 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
2078 sizeof(struct sdpcm_shared));
2083 sh->flags = le32_to_cpu(sh->flags);
2084 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2085 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2086 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2087 sh->assert_line = le32_to_cpu(sh->assert_line);
2088 sh->console_addr = le32_to_cpu(sh->console_addr);
2089 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2091 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2092 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2093 "is different than sdpcm_shared version %d in dongle\n",
2094 __func__, SDPCM_SHARED_VERSION,
2095 sh->flags & SDPCM_SHARED_VERSION_MASK));
2102 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2106 char *mbuffer = NULL;
2107 uint maxstrlen = 256;
2110 struct sdpcm_shared sdpcm_shared;
2111 struct brcmu_strbuf strbuf;
2113 DHD_TRACE(("%s: Enter\n", __func__));
2117 * Called after a rx ctrl timeout. "data" is NULL.
2118 * allocate memory to trace the trap or assert.
2121 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2122 if (mbuffer == NULL) {
2123 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2130 str = kmalloc(maxstrlen, GFP_ATOMIC);
2132 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2137 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
2141 brcmu_binit(&strbuf, data, size);
2143 brcmu_bprintf(&strbuf,
2144 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2145 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2147 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2148 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2149 * (Avoids conflict with real asserts for programmatic
2150 * parsing of output.)
2152 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2155 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2157 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2158 * (Avoids conflict with real asserts for programmatic
2159 * parsing of output.)
2161 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2162 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2165 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2166 /* Download assert */
2167 brcmu_bprintf(&strbuf, "Dongle assert");
2168 if (sdpcm_shared.assert_exp_addr != 0) {
2170 bcmerror = dhdsdio_membytes(bus, false,
2171 sdpcm_shared.assert_exp_addr,
2172 (u8 *) str, maxstrlen);
2176 str[maxstrlen - 1] = '\0';
2177 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2180 if (sdpcm_shared.assert_file_addr != 0) {
2182 bcmerror = dhdsdio_membytes(bus, false,
2183 sdpcm_shared.assert_file_addr,
2184 (u8 *) str, maxstrlen);
2188 str[maxstrlen - 1] = '\0';
2189 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2192 brcmu_bprintf(&strbuf, " line %d ",
2193 sdpcm_shared.assert_line);
2196 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2197 bcmerror = dhdsdio_membytes(bus, false,
2198 sdpcm_shared.trap_addr, (u8 *)&tr,
2203 brcmu_bprintf(&strbuf,
2204 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2205 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2206 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2207 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2208 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2209 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2214 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2215 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2218 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2219 /* Mem dump to a file on device */
2220 dhdsdio_mem_dump(bus);
2222 #endif /* DHD_DEBUG */
2231 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2234 int size; /* Full mem size */
2235 int start = 0; /* Start address */
2236 int read_size = 0; /* Read size of each iteration */
2237 u8 *buf = NULL, *databuf = NULL;
2239 /* Get full mem size */
2240 size = bus->ramsize;
2241 buf = kmalloc(size, GFP_ATOMIC);
2243 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2247 /* Read mem content */
2248 printk(KERN_DEBUG "Dump dongle memory");
2251 read_size = min(MEMBLOCK, size);
2252 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2254 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2260 /* Decrement size and increment start address */
2263 databuf += read_size;
2265 printk(KERN_DEBUG "Done\n");
2267 /* free buf before return !!! */
2268 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2269 DHD_ERROR(("%s: Error writing to files\n", __func__));
2273 /* buf free handled in write_to_file, not here */
2277 #define CONSOLE_LINE_MAX 192
2279 static int dhdsdio_readconsole(dhd_bus_t *bus)
2281 dhd_console_t *c = &bus->console;
2282 u8 line[CONSOLE_LINE_MAX], ch;
2286 /* Don't do anything until FWREADY updates console address */
2287 if (bus->console_addr == 0)
2290 /* Read console log struct */
2291 addr = bus->console_addr + offsetof(rte_cons_t, log);
2292 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2297 /* Allocate console buffer (one time only) */
2298 if (c->buf == NULL) {
2299 c->bufsize = le32_to_cpu(c->log.buf_size);
2300 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2305 idx = le32_to_cpu(c->log.idx);
2307 /* Protect against corrupt value */
2308 if (idx > c->bufsize)
2311 /* Skip reading the console buffer if the index pointer
2316 /* Read the console buffer */
2317 addr = le32_to_cpu(c->log.buf);
2318 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2322 while (c->last != idx) {
2323 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2324 if (c->last == idx) {
2325 /* This would output a partial line.
2327 * the buffer pointer and output this
2328 * line next time around.
2333 c->last = c->bufsize - n;
2336 ch = c->buf[c->last];
2337 c->last = (c->last + 1) % c->bufsize;
2344 if (line[n - 1] == '\r')
2347 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2354 #endif /* DHD_DEBUG */
2356 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2360 DHD_TRACE(("%s: Enter\n", __func__));
2362 /* Basic sanity checks */
2364 bcmerror = -EISCONN;
2368 bcmerror = -EOVERFLOW;
2372 /* Free the old ones and replace with passed variables */
2375 bus->vars = kmalloc(len, GFP_ATOMIC);
2376 bus->varsz = bus->vars ? len : 0;
2377 if (bus->vars == NULL) {
2382 /* Copy the passed variables, which should include the
2383 terminating double-null */
2384 memcpy(bus->vars, arg, bus->varsz);
2390 dhdsdio_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2391 const char *name, void *params, int plen, void *arg, int len,
2398 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2399 "len %d val_size %d\n",
2400 __func__, actionid, name, params, plen, arg, len, val_size));
2402 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2406 if (plen >= (int)sizeof(int_val))
2407 memcpy(&int_val, params, sizeof(int_val));
2409 bool_val = (int_val != 0) ? true : false;
2411 /* Some ioctls use the bus */
2412 dhd_os_sdlock(bus->dhd);
2414 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2415 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2416 actionid == IOV_GVAL(IOV_DEVRESET))) {
2421 /* Handle sleep stuff before any clock mucking */
2422 if (vi->varid == IOV_SLEEP) {
2423 if (IOV_ISSET(actionid)) {
2424 bcmerror = dhdsdio_bussleep(bus, bool_val);
2426 int_val = (s32) bus->sleeping;
2427 memcpy(arg, &int_val, val_size);
2432 /* Request clock to allow SDIO accesses */
2433 if (!bus->dhd->dongle_reset) {
2435 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2439 case IOV_GVAL(IOV_INTR):
2440 int_val = (s32) bus->intr;
2441 memcpy(arg, &int_val, val_size);
2444 case IOV_SVAL(IOV_INTR):
2445 bus->intr = bool_val;
2446 bus->intdis = false;
2449 DHD_INTR(("%s: enable SDIO device interrupts\n",
2451 bcmsdh_intr_enable(bus->sdh);
2453 DHD_INTR(("%s: disable SDIO interrupts\n",
2455 bcmsdh_intr_disable(bus->sdh);
2460 case IOV_GVAL(IOV_POLLRATE):
2461 int_val = (s32) bus->pollrate;
2462 memcpy(arg, &int_val, val_size);
2465 case IOV_SVAL(IOV_POLLRATE):
2466 bus->pollrate = (uint) int_val;
2467 bus->poll = (bus->pollrate != 0);
2470 case IOV_GVAL(IOV_IDLETIME):
2471 int_val = bus->idletime;
2472 memcpy(arg, &int_val, val_size);
2475 case IOV_SVAL(IOV_IDLETIME):
2476 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2479 bus->idletime = int_val;
2482 case IOV_GVAL(IOV_IDLECLOCK):
2483 int_val = (s32) bus->idleclock;
2484 memcpy(arg, &int_val, val_size);
2487 case IOV_SVAL(IOV_IDLECLOCK):
2488 bus->idleclock = int_val;
2491 case IOV_GVAL(IOV_SD1IDLE):
2492 int_val = (s32) sd1idle;
2493 memcpy(arg, &int_val, val_size);
2496 case IOV_SVAL(IOV_SD1IDLE):
2500 case IOV_SVAL(IOV_MEMBYTES):
2501 case IOV_GVAL(IOV_MEMBYTES):
2507 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2509 ASSERT(plen >= 2 * sizeof(int));
2511 address = (u32) int_val;
2512 memcpy(&int_val, (char *)params + sizeof(int_val),
2514 size = (uint) int_val;
2516 /* Do some validation */
2517 dsize = set ? plen - (2 * sizeof(int)) : len;
2519 DHD_ERROR(("%s: error on %s membytes, addr "
2520 "0x%08x size %d dsize %d\n",
2521 __func__, (set ? "set" : "get"),
2522 address, size, dsize));
2527 DHD_INFO(("%s: Request to %s %d bytes at address "
2529 __func__, (set ? "write" : "read"), size, address));
2531 /* If we know about SOCRAM, check for a fit */
2532 if ((bus->orig_ramsize) &&
2533 ((address > bus->orig_ramsize)
2534 || (address + size > bus->orig_ramsize))) {
2535 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2536 "bytes at 0x%08x\n",
2537 __func__, bus->orig_ramsize, size, address));
2542 /* Generate the actual data pointer */
2544 set ? (u8 *) params +
2545 2 * sizeof(int) : (u8 *) arg;
2547 /* Call to do the transfer */
2549 dhdsdio_membytes(bus, set, address, data, size);
2554 case IOV_GVAL(IOV_MEMSIZE):
2555 int_val = (s32) bus->ramsize;
2556 memcpy(arg, &int_val, val_size);
2559 case IOV_GVAL(IOV_SDIOD_DRIVE):
2560 int_val = (s32) dhd_sdiod_drive_strength;
2561 memcpy(arg, &int_val, val_size);
2564 case IOV_SVAL(IOV_SDIOD_DRIVE):
2565 dhd_sdiod_drive_strength = int_val;
2566 dhdsdio_sdiod_drive_strength_init(bus,
2567 dhd_sdiod_drive_strength);
2570 case IOV_SVAL(IOV_DOWNLOAD):
2571 bcmerror = dhdsdio_download_state(bus, bool_val);
2574 case IOV_SVAL(IOV_VARS):
2575 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2578 case IOV_GVAL(IOV_READAHEAD):
2579 int_val = (s32) dhd_readahead;
2580 memcpy(arg, &int_val, val_size);
2583 case IOV_SVAL(IOV_READAHEAD):
2584 if (bool_val && !dhd_readahead)
2586 dhd_readahead = bool_val;
2589 case IOV_GVAL(IOV_SDRXCHAIN):
2590 int_val = (s32) bus->use_rxchain;
2591 memcpy(arg, &int_val, val_size);
2594 case IOV_SVAL(IOV_SDRXCHAIN):
2595 if (bool_val && !bus->sd_rxchain)
2596 bcmerror = -ENOTSUPP;
2598 bus->use_rxchain = bool_val;
2600 case IOV_GVAL(IOV_ALIGNCTL):
2601 int_val = (s32) dhd_alignctl;
2602 memcpy(arg, &int_val, val_size);
2605 case IOV_SVAL(IOV_ALIGNCTL):
2606 dhd_alignctl = bool_val;
2609 case IOV_GVAL(IOV_SDALIGN):
2610 int_val = DHD_SDALIGN;
2611 memcpy(arg, &int_val, val_size);
2615 case IOV_GVAL(IOV_VARS):
2616 if (bus->varsz < (uint) len)
2617 memcpy(arg, bus->vars, bus->varsz);
2619 bcmerror = -EOVERFLOW;
2621 #endif /* DHD_DEBUG */
2624 case IOV_GVAL(IOV_SDREG):
2629 sd_ptr = (sdreg_t *) params;
2631 addr = (unsigned long)bus->regs + sd_ptr->offset;
2632 size = sd_ptr->func;
2633 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2634 if (bcmsdh_regfail(bus->sdh))
2636 memcpy(arg, &int_val, sizeof(s32));
2640 case IOV_SVAL(IOV_SDREG):
2645 sd_ptr = (sdreg_t *) params;
2647 addr = (unsigned long)bus->regs + sd_ptr->offset;
2648 size = sd_ptr->func;
2649 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2650 if (bcmsdh_regfail(bus->sdh))
2655 /* Same as above, but offset is not backplane
2657 case IOV_GVAL(IOV_SBREG):
2662 memcpy(&sdreg, params, sizeof(sdreg));
2664 addr = SI_ENUM_BASE + sdreg.offset;
2666 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2667 if (bcmsdh_regfail(bus->sdh))
2669 memcpy(arg, &int_val, sizeof(s32));
2673 case IOV_SVAL(IOV_SBREG):
2678 memcpy(&sdreg, params, sizeof(sdreg));
2680 addr = SI_ENUM_BASE + sdreg.offset;
2682 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2683 if (bcmsdh_regfail(bus->sdh))
2688 case IOV_GVAL(IOV_SDCIS):
2692 strcat(arg, "\nFunc 0\n");
2693 bcmsdh_cis_read(bus->sdh, 0x10,
2694 (u8 *) arg + strlen(arg),
2695 SBSDIO_CIS_SIZE_LIMIT);
2696 strcat(arg, "\nFunc 1\n");
2697 bcmsdh_cis_read(bus->sdh, 0x11,
2698 (u8 *) arg + strlen(arg),
2699 SBSDIO_CIS_SIZE_LIMIT);
2700 strcat(arg, "\nFunc 2\n");
2701 bcmsdh_cis_read(bus->sdh, 0x12,
2702 (u8 *) arg + strlen(arg),
2703 SBSDIO_CIS_SIZE_LIMIT);
2707 case IOV_GVAL(IOV_FORCEEVEN):
2708 int_val = (s32) forcealign;
2709 memcpy(arg, &int_val, val_size);
2712 case IOV_SVAL(IOV_FORCEEVEN):
2713 forcealign = bool_val;
2716 case IOV_GVAL(IOV_TXBOUND):
2717 int_val = (s32) dhd_txbound;
2718 memcpy(arg, &int_val, val_size);
2721 case IOV_SVAL(IOV_TXBOUND):
2722 dhd_txbound = (uint) int_val;
2725 case IOV_GVAL(IOV_RXBOUND):
2726 int_val = (s32) dhd_rxbound;
2727 memcpy(arg, &int_val, val_size);
2730 case IOV_SVAL(IOV_RXBOUND):
2731 dhd_rxbound = (uint) int_val;
2734 case IOV_GVAL(IOV_TXMINMAX):
2735 int_val = (s32) dhd_txminmax;
2736 memcpy(arg, &int_val, val_size);
2739 case IOV_SVAL(IOV_TXMINMAX):
2740 dhd_txminmax = (uint) int_val;
2742 #endif /* DHD_DEBUG */
2745 case IOV_GVAL(IOV_EXTLOOP):
2746 int_val = (s32) bus->ext_loop;
2747 memcpy(arg, &int_val, val_size);
2750 case IOV_SVAL(IOV_EXTLOOP):
2751 bus->ext_loop = bool_val;
2754 case IOV_GVAL(IOV_PKTGEN):
2755 bcmerror = dhdsdio_pktgen_get(bus, arg);
2758 case IOV_SVAL(IOV_PKTGEN):
2759 bcmerror = dhdsdio_pktgen_set(bus, arg);
2763 case IOV_SVAL(IOV_DEVRESET):
2764 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2766 __func__, bool_val, bus->dhd->dongle_reset,
2767 bus->dhd->busstate));
2769 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2773 case IOV_GVAL(IOV_DEVRESET):
2774 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2776 /* Get its status */
2777 int_val = (bool) bus->dhd->dongle_reset;
2778 memcpy(arg, &int_val, val_size);
2783 bcmerror = -ENOTSUPP;
2788 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2789 bus->activity = false;
2790 dhdsdio_clkctl(bus, CLK_NONE, true);
2793 dhd_os_sdunlock(bus->dhd);
2795 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2796 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2801 static int dhdsdio_write_vars(dhd_bus_t *bus)
2809 char *nvram_ularray;
2810 #endif /* DHD_DEBUG */
2812 /* Even if there are no vars are to be written, we still
2813 need to set the ramsize. */
2814 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2815 varaddr = (bus->ramsize - 4) - varsize;
2818 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2822 memcpy(vbuffer, bus->vars, bus->varsz);
2824 /* Write the vars list */
2826 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2828 /* Verify NVRAM bytes */
2829 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2830 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2834 /* Upload image to verify downloaded contents. */
2835 memset(nvram_ularray, 0xaa, varsize);
2837 /* Read the vars list to temp buffer for comparison */
2839 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2842 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2843 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2845 /* Compare the org NVRAM with the one read from RAM */
2846 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2847 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2850 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2853 kfree(nvram_ularray);
2854 #endif /* DHD_DEBUG */
2859 /* adjust to the user specified RAM */
2860 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2861 bus->orig_ramsize, bus->ramsize));
2862 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2863 varsize = ((bus->orig_ramsize - 4) - varaddr);
2866 * Determine the length token:
2867 * Varsize, converted to words, in lower 16-bits, checksum
2873 varsizew = varsize / 4;
2874 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2875 varsizew = cpu_to_le32(varsizew);
2878 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2881 /* Write the length token to the last word */
2882 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2883 (u8 *)&varsizew, 4);
2888 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2894 /* To enter download state, disable ARM and reset SOCRAM.
2895 * To exit download state, simply reset ARM (default is RAM boot).
2898 bus->alp_only = true;
2900 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2902 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2904 /* Clear the top bit of memory */
2907 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2911 regdata = bcmsdh_reg_read(bus->sdh,
2912 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2913 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2914 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2915 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2916 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2922 bcmerror = dhdsdio_write_vars(bus);
2924 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2928 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2930 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2932 /* Allow HT Clock now that the ARM is running. */
2933 bus->alp_only = false;
2935 bus->dhd->busstate = DHD_BUS_LOAD;
2942 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2943 void *params, int plen, void *arg, int len, bool set)
2945 dhd_bus_t *bus = dhdp->bus;
2946 const struct brcmu_iovar *vi = NULL;
2951 DHD_TRACE(("%s: Enter\n", __func__));
2956 /* Get MUST have return space */
2957 ASSERT(set || (arg && len));
2959 /* Set does NOT take qualifiers */
2960 ASSERT(!set || (!params && !plen));
2962 /* Look up var locally; if not found pass to host driver */
2963 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2965 dhd_os_sdlock(bus->dhd);
2969 /* Turn on clock in case SD command needs backplane */
2970 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2973 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2976 /* Similar check for blocksize change */
2977 if (set && strcmp(name, "sd_blocksize") == 0) {
2980 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2981 &bus->blocksize, sizeof(s32),
2984 DHD_ERROR(("%s: fail on %s get\n", __func__,
2987 DHD_INFO(("%s: noted %s update, value now %d\n",
2988 __func__, "sd_blocksize",
2992 bus->roundup = min(max_roundup, bus->blocksize);
2994 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2995 bus->activity = false;
2996 dhdsdio_clkctl(bus, CLK_NONE, true);
2999 dhd_os_sdunlock(bus->dhd);
3003 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
3004 name, (set ? "set" : "get"), len, plen));
3006 /* set up 'params' pointer in case this is a set command so that
3007 * the convenience int and bool code can be common to set and get
3009 if (params == NULL) {
3014 if (vi->type == IOVT_VOID)
3016 else if (vi->type == IOVT_BUFFER)
3019 /* all other types are integer sized */
3020 val_size = sizeof(int);
3022 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3024 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
3031 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
3033 u32 local_hostintmask;
3038 DHD_TRACE(("%s: Enter\n", __func__));
3041 dhd_os_sdlock(bus->dhd);
3045 /* Enable clock for device interrupts */
3046 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3048 /* Disable and clear interrupts at the chip level also */
3049 W_SDREG(0, &bus->regs->hostintmask, retries);
3050 local_hostintmask = bus->hostintmask;
3051 bus->hostintmask = 0;
3053 /* Change our idea of bus state */
3054 bus->dhd->busstate = DHD_BUS_DOWN;
3056 /* Force clocks on backplane to be sure F2 interrupt propagates */
3058 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3061 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3062 (saveclk | SBSDIO_FORCE_HT), &err);
3065 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3069 /* Turn off the bus (F2), free any pending packets */
3070 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3071 bcmsdh_intr_disable(bus->sdh);
3072 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3073 SDIO_FUNC_ENABLE_1, NULL);
3075 /* Clear any pending interrupts now that F2 is disabled */
3076 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3078 /* Turn off the backplane clock (only) */
3079 dhdsdio_clkctl(bus, CLK_SDONLY, false);
3081 /* Clear the data packet queues */
3082 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3084 /* Clear any held glomming stuff */
3086 brcmu_pkt_buf_free_skb(bus->glomd);
3089 brcmu_pkt_buf_free_skb(bus->glom);
3091 bus->glom = bus->glomd = NULL;
3093 /* Clear rx control and wake any waiters */
3095 dhd_os_ioctl_resp_wake(bus->dhd);
3097 /* Reset some F2 state stuff */
3098 bus->rxskip = false;
3099 bus->tx_seq = bus->rx_seq = 0;
3102 dhd_os_sdunlock(bus->dhd);
3105 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3107 dhd_bus_t *bus = dhdp->bus;
3114 DHD_TRACE(("%s: Enter\n", __func__));
3121 dhd_os_sdlock(bus->dhd);
3123 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3124 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3125 if (bus->clkstate != CLK_AVAIL)
3128 /* Force clocks on backplane to be sure F2 interrupt propagates */
3130 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3133 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3134 (saveclk | SBSDIO_FORCE_HT), &err);
3137 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3142 /* Enable function 2 (frame transfers) */
3143 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3144 &bus->regs->tosbmailboxdata, retries);
3145 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3147 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable, NULL);
3149 /* Give the dongle some time to do its thing and set IOR2 */
3150 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3153 while (ready != enable && !dhd_timeout_expired(&tmo))
3155 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3158 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3159 __func__, enable, ready, tmo.elapsed));
3161 /* If F2 successfully enabled, set core and enable interrupts */
3162 if (ready == enable) {
3163 /* Set up the interrupt mask and enable interrupts */
3164 bus->hostintmask = HOSTINTMASK;
3165 W_SDREG(bus->hostintmask,
3166 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3167 hostintmask), retries);
3169 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3170 (u8) watermark, &err);
3172 /* Set bus state according to enable result */
3173 dhdp->busstate = DHD_BUS_DATA;
3175 /* bcmsdh_intr_unmask(bus->sdh); */
3177 bus->intdis = false;
3179 DHD_INTR(("%s: enable SDIO device interrupts\n",
3181 bcmsdh_intr_enable(bus->sdh);
3183 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3184 bcmsdh_intr_disable(bus->sdh);
3190 /* Disable F2 again */
3191 enable = SDIO_FUNC_ENABLE_1;
3192 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3196 /* Restore previous clock setting */
3197 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3200 /* If we didn't come up, turn off backplane clock */
3201 if (dhdp->busstate != DHD_BUS_DATA)
3202 dhdsdio_clkctl(bus, CLK_NONE, false);
3206 dhd_os_sdunlock(bus->dhd);
3211 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3213 bcmsdh_info_t *sdh = bus->sdh;
3214 struct sdpcmd_regs *regs = bus->regs;
3220 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3221 (abort ? "abort command, " : ""),
3222 (rtx ? ", send NAK" : "")));
3225 bcmsdh_abort(sdh, SDIO_FUNC_2);
3227 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3231 /* Wait until the packet has been flushed (device/FIFO stable) */
3232 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3233 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3235 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3237 bus->f1regdata += 2;
3239 if ((hi == 0) && (lo == 0))
3242 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3243 DHD_ERROR(("%s: count growing: last 0x%04x now "
3245 __func__, lastrbc, ((hi << 8) + lo)));
3247 lastrbc = (hi << 8) + lo;
3251 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3252 __func__, lastrbc));
3254 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3255 (0xffff - retries)));
3260 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3262 if (retries <= retry_limit)
3266 /* Clear partial in any case */
3269 /* If we can't reach the device, signal failure */
3270 if (err || bcmsdh_regfail(sdh))
3271 bus->dhd->busstate = DHD_BUS_DOWN;
3275 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3277 bcmsdh_info_t *sdh = bus->sdh;
3282 DHD_TRACE(("%s: Enter\n", __func__));
3284 /* Control data already received in aligned rxctl */
3285 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3289 /* Set rxctl for frame (w/optional alignment) */
3290 bus->rxctl = bus->rxbuf;
3292 bus->rxctl += firstread;
3293 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3295 bus->rxctl += (DHD_SDALIGN - pad);
3296 bus->rxctl -= firstread;
3298 ASSERT(bus->rxctl >= bus->rxbuf);
3300 /* Copy the already-read portion over */
3301 memcpy(bus->rxctl, hdr, firstread);
3302 if (len <= firstread)
3305 /* Copy the full data pkt in gSPI case and process ioctl. */
3306 if (bus->bus == SPI_BUS) {
3307 memcpy(bus->rxctl, hdr, len);
3311 /* Raise rdlen to next SDIO block to avoid tail command */
3312 rdlen = len - firstread;
3313 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3314 pad = bus->blocksize - (rdlen % bus->blocksize);
3315 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3316 ((len + pad) < bus->dhd->maxctl))
3318 } else if (rdlen % DHD_SDALIGN) {
3319 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3322 /* Satisfy length-alignment requirements */
3323 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3324 rdlen = roundup(rdlen, ALIGNMENT);
3326 /* Drop if the read is too big or it exceeds our maximum */
3327 if ((rdlen + firstread) > bus->dhd->maxctl) {
3328 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3329 __func__, rdlen, bus->dhd->maxctl));
3330 bus->dhd->rx_errors++;
3331 dhdsdio_rxfail(bus, false, false);
3335 if ((len - doff) > bus->dhd->maxctl) {
3336 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3338 __func__, len, (len - doff), bus->dhd->maxctl));
3339 bus->dhd->rx_errors++;
3341 dhdsdio_rxfail(bus, false, false);
3345 /* Read remainder of frame body into the rxctl buffer */
3346 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3347 F2SYNC, (bus->rxctl + firstread), rdlen,
3350 ASSERT(sdret != -BCME_PENDING);
3352 /* Control frame failures need retransmission */
3354 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3355 __func__, rdlen, sdret));
3356 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3357 dhdsdio_rxfail(bus, true, true);
3364 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3365 printk(KERN_DEBUG "RxCtrl:\n");
3366 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3370 /* Point to valid data and indicate its length */
3372 bus->rxlen = len - doff;
3375 /* Awake any waiters */
3376 dhd_os_ioctl_resp_wake(bus->dhd);
3379 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3385 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3388 u8 chan, seq, doff, sfdoff;
3392 bool usechain = bus->use_rxchain;
3394 /* If packets, issue read(s) and send up packet chain */
3395 /* Return sequence numbers consumed? */
3397 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3400 /* If there's a descriptor, generate the packet chain */
3402 dhd_os_sdlock_rxq(bus->dhd);
3404 pfirst = plast = pnext = NULL;
3405 dlen = (u16) (bus->glomd->len);
3406 dptr = bus->glomd->data;
3407 if (!dlen || (dlen & 1)) {
3408 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3413 for (totlen = num = 0; dlen; num++) {
3414 /* Get (and move past) next length */
3415 sublen = get_unaligned_le16(dptr);
3416 dlen -= sizeof(u16);
3417 dptr += sizeof(u16);
3418 if ((sublen < SDPCM_HDRLEN) ||
3419 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3420 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3421 __func__, num, sublen));
3425 if (sublen % DHD_SDALIGN) {
3426 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3427 __func__, sublen, DHD_SDALIGN));
3432 /* For last frame, adjust read len so total
3433 is a block multiple */
3436 (roundup(totlen, bus->blocksize) - totlen);
3437 totlen = roundup(totlen, bus->blocksize);
3440 /* Allocate/chain packet for next subframe */
3441 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3442 if (pnext == NULL) {
3443 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3444 "num %d len %d\n", __func__,
3448 ASSERT(!(pnext->prev));
3451 pfirst = plast = pnext;
3454 plast->next = pnext;
3458 /* Adhere to start alignment requirements */
3459 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3462 /* If all allocations succeeded, save packet chain
3465 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3466 "subframes\n", __func__, totlen, num));
3467 if (DHD_GLOM_ON() && bus->nextlen) {
3468 if (totlen != bus->nextlen) {
3469 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3470 __func__, bus->nextlen,
3475 pfirst = pnext = NULL;
3478 brcmu_pkt_buf_free_skb(pfirst);
3483 /* Done with descriptor packet */
3484 brcmu_pkt_buf_free_skb(bus->glomd);
3488 dhd_os_sdunlock_rxq(bus->dhd);
3491 /* Ok -- either we just generated a packet chain,
3492 or had one from before */
3494 if (DHD_GLOM_ON()) {
3495 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3497 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3498 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3499 pnext, (u8 *) (pnext->data),
3500 pnext->len, pnext->len));
3505 dlen = (u16) brcmu_pkttotlen(pfirst);
3507 /* Do an SDIO read for the superframe. Configurable iovar to
3508 * read directly into the chained packet, or allocate a large
3509 * packet and and copy into the chain.
3512 errcode = bcmsdh_recv_buf(bus,
3513 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3514 F2SYNC, (u8 *) pfirst->data, dlen,
3515 pfirst, NULL, NULL);
3516 } else if (bus->dataptr) {
3517 errcode = bcmsdh_recv_buf(bus,
3518 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3519 F2SYNC, bus->dataptr, dlen,
3521 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3523 if (sublen != dlen) {
3524 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3525 __func__, dlen, sublen));
3530 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3535 ASSERT(errcode != -BCME_PENDING);
3537 /* On failure, kill the superframe, allow a couple retries */
3539 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3540 __func__, dlen, errcode));
3541 bus->dhd->rx_errors++;
3543 if (bus->glomerr++ < 3) {
3544 dhdsdio_rxfail(bus, true, true);
3547 dhdsdio_rxfail(bus, true, false);
3548 dhd_os_sdlock_rxq(bus->dhd);
3549 brcmu_pkt_buf_free_skb(bus->glom);
3550 dhd_os_sdunlock_rxq(bus->dhd);
3557 if (DHD_GLOM_ON()) {
3558 printk(KERN_DEBUG "SUPERFRAME:\n");
3559 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3560 pfirst->data, min_t(int, pfirst->len, 48));
3564 /* Validate the superframe header */
3565 dptr = (u8 *) (pfirst->data);
3566 sublen = get_unaligned_le16(dptr);
3567 check = get_unaligned_le16(dptr + sizeof(u16));
3569 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3570 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3571 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3572 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3573 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3574 __func__, bus->nextlen, seq));
3577 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3578 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3581 if ((u16)~(sublen ^ check)) {
3582 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3583 "0x%04x/0x%04x\n", __func__, sublen, check));
3585 } else if (roundup(sublen, bus->blocksize) != dlen) {
3586 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3587 "0x%04x, expect 0x%04x\n",
3589 roundup(sublen, bus->blocksize), dlen));
3591 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3592 SDPCM_GLOM_CHANNEL) {
3593 DHD_ERROR(("%s (superframe): bad channel %d\n",
3595 SDPCM_PACKET_CHANNEL(&dptr
3596 [SDPCM_FRAMETAG_LEN])));
3598 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3599 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3602 } else if ((doff < SDPCM_HDRLEN) ||
3603 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3604 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3606 __func__, doff, sublen,
3607 pfirst->len, SDPCM_HDRLEN));
3611 /* Check sequence number of superframe SW header */
3613 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3614 __func__, seq, rxseq));
3619 /* Check window for sanity */
3620 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3621 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3622 __func__, txmax, bus->tx_seq));
3623 txmax = bus->tx_seq + 2;
3625 bus->tx_max = txmax;
3627 /* Remove superframe header, remember offset */
3628 skb_pull(pfirst, doff);
3631 /* Validate all the subframe headers */
3632 for (num = 0, pnext = pfirst; pnext && !errcode;
3633 num++, pnext = pnext->next) {
3634 dptr = (u8 *) (pnext->data);
3635 dlen = (u16) (pnext->len);
3636 sublen = get_unaligned_le16(dptr);
3637 check = get_unaligned_le16(dptr + sizeof(u16));
3638 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3639 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3641 if (DHD_GLOM_ON()) {
3642 printk(KERN_DEBUG "subframe:\n");
3643 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3648 if ((u16)~(sublen ^ check)) {
3649 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3650 "len/check 0x%04x/0x%04x\n",
3651 __func__, num, sublen, check));
3653 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3654 DHD_ERROR(("%s (subframe %d): length mismatch: "
3655 "len 0x%04x, expect 0x%04x\n",
3656 __func__, num, sublen, dlen));
3658 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3659 (chan != SDPCM_EVENT_CHANNEL)) {
3660 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3661 __func__, num, chan));
3663 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3664 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3665 __func__, num, doff, sublen,
3672 /* Terminate frame on error, request
3674 if (bus->glomerr++ < 3) {
3675 /* Restore superframe header space */
3676 skb_push(pfirst, sfdoff);
3677 dhdsdio_rxfail(bus, true, true);
3680 dhdsdio_rxfail(bus, true, false);
3681 dhd_os_sdlock_rxq(bus->dhd);
3682 brcmu_pkt_buf_free_skb(bus->glom);
3683 dhd_os_sdunlock_rxq(bus->dhd);
3691 /* Basic SD framing looks ok - process each packet (header) */
3692 save_pfirst = pfirst;
3696 dhd_os_sdlock_rxq(bus->dhd);
3697 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3698 pnext = pfirst->next;
3699 pfirst->next = NULL;
3701 dptr = (u8 *) (pfirst->data);
3702 sublen = get_unaligned_le16(dptr);
3703 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3704 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3705 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3707 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3709 __func__, num, pfirst, pfirst->data,
3710 pfirst->len, sublen, chan, seq));
3712 ASSERT((chan == SDPCM_DATA_CHANNEL)
3713 || (chan == SDPCM_EVENT_CHANNEL));
3716 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3717 __func__, seq, rxseq));
3722 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3723 printk(KERN_DEBUG "Rx Subframe Data:\n");
3724 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3729 __skb_trim(pfirst, sublen);
3730 skb_pull(pfirst, doff);
3732 if (pfirst->len == 0) {
3733 brcmu_pkt_buf_free_skb(pfirst);
3735 plast->next = pnext;
3737 ASSERT(save_pfirst == pfirst);
3738 save_pfirst = pnext;
3741 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3743 DHD_ERROR(("%s: rx protocol error\n",
3745 bus->dhd->rx_errors++;
3746 brcmu_pkt_buf_free_skb(pfirst);
3748 plast->next = pnext;
3750 ASSERT(save_pfirst == pfirst);
3751 save_pfirst = pnext;
3756 /* this packet will go up, link back into
3757 chain and count it */
3758 pfirst->next = pnext;
3763 if (DHD_GLOM_ON()) {
3764 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3766 __func__, num, pfirst, pfirst->data,
3767 pfirst->len, pfirst->next,
3769 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3771 min_t(int, pfirst->len, 32));
3773 #endif /* DHD_DEBUG */
3775 dhd_os_sdunlock_rxq(bus->dhd);
3777 dhd_os_sdunlock(bus->dhd);
3778 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3779 dhd_os_sdlock(bus->dhd);
3782 bus->rxglomframes++;
3783 bus->rxglompkts += num;
3788 /* Return true if there may be more frames to read */
3789 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3791 bcmsdh_info_t *sdh = bus->sdh;
3793 u16 len, check; /* Extracted hardware header fields */
3794 u8 chan, seq, doff; /* Extracted software header fields */
3795 u8 fcbits; /* Extracted fcbits from software header */
3797 struct sk_buff *pkt; /* Packet for event or data frames */
3798 u16 pad; /* Number of pad bytes to read */
3799 u16 rdlen; /* Total number of bytes to read */
3800 u8 rxseq; /* Next sequence number to expect */
3801 uint rxleft = 0; /* Remaining number of frames allowed */
3802 int sdret; /* Return code from bcmsdh calls */
3803 u8 txmax; /* Maximum tx sequence offered */
3804 bool len_consistent; /* Result of comparing readahead len and
3808 uint rxcount = 0; /* Total frames read */
3810 #if defined(DHD_DEBUG) || defined(SDTEST)
3811 bool sdtest = false; /* To limit message spew from test mode */
3814 DHD_TRACE(("%s: Enter\n", __func__));
3819 /* Allow pktgen to override maxframes */
3820 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3821 maxframes = bus->pktgen_count;
3826 /* Not finished unless we encounter no more frames indication */
3829 for (rxseq = bus->rx_seq, rxleft = maxframes;
3830 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3831 rxseq++, rxleft--) {
3833 /* Handle glomming separately */
3834 if (bus->glom || bus->glomd) {
3836 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3837 __func__, bus->glomd, bus->glom));
3838 cnt = dhdsdio_rxglom(bus, rxseq);
3839 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3841 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3845 /* Try doing single read if we can */
3846 if (dhd_readahead && bus->nextlen) {
3847 u16 nextlen = bus->nextlen;
3850 if (bus->bus == SPI_BUS) {
3851 rdlen = len = nextlen;
3853 rdlen = len = nextlen << 4;
3855 /* Pad read to blocksize for efficiency */
3856 if (bus->roundup && bus->blocksize
3857 && (rdlen > bus->blocksize)) {
3860 (rdlen % bus->blocksize);
3861 if ((pad <= bus->roundup)
3862 && (pad < bus->blocksize)
3863 && ((rdlen + pad + firstread) <
3866 } else if (rdlen % DHD_SDALIGN) {
3868 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3872 /* We use bus->rxctl buffer in WinXP for initial
3873 * control pkt receives.
3874 * Later we use buffer-poll for data as well
3875 * as control packets.
3876 * This is required because dhd receives full
3877 * frame in gSPI unlike SDIO.
3878 * After the frame is received we have to
3879 * distinguish whether it is data
3880 * or non-data frame.
3882 /* Allocate a packet buffer */
3883 dhd_os_sdlock_rxq(bus->dhd);
3884 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3886 if (bus->bus == SPI_BUS) {
3887 bus->usebufpool = false;
3888 bus->rxctl = bus->rxbuf;
3890 bus->rxctl += firstread;
3891 pad = ((unsigned long)bus->rxctl %
3895 (DHD_SDALIGN - pad);
3896 bus->rxctl -= firstread;
3898 ASSERT(bus->rxctl >= bus->rxbuf);
3900 /* Read the entire frame */
3901 sdret = bcmsdh_recv_buf(bus,
3902 bcmsdh_cur_sbwad(sdh),
3903 SDIO_FUNC_2, F2SYNC,
3907 ASSERT(sdret != -BCME_PENDING);
3909 /* Control frame failures need
3912 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3915 /* dhd.rx_ctlerrs is higher */
3917 dhd_os_sdunlock_rxq(bus->dhd);
3918 dhdsdio_rxfail(bus, true,
3926 request rtx of events */
3927 DHD_ERROR(("%s (nextlen): "
3928 "brcmu_pkt_buf_get_skb "
3930 " len %d rdlen %d expected"
3931 " rxseq %d\n", __func__,
3932 len, rdlen, rxseq));
3933 /* Just go try again w/normal
3935 dhd_os_sdunlock_rxq(bus->dhd);
3939 if (bus->bus == SPI_BUS)
3940 bus->usebufpool = true;
3942 ASSERT(!(pkt->prev));
3943 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3944 rxbuf = (u8 *) (pkt->data);
3945 /* Read the entire frame */
3946 sdret = bcmsdh_recv_buf(bus,
3947 bcmsdh_cur_sbwad(sdh),
3948 SDIO_FUNC_2, F2SYNC,
3952 ASSERT(sdret != -BCME_PENDING);
3955 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3956 __func__, rdlen, sdret));
3957 brcmu_pkt_buf_free_skb(pkt);
3958 bus->dhd->rx_errors++;
3959 dhd_os_sdunlock_rxq(bus->dhd);
3960 /* Force retry w/normal header read.
3961 * Don't attempt NAK for
3964 dhdsdio_rxfail(bus, true,
3971 dhd_os_sdunlock_rxq(bus->dhd);
3973 /* Now check the header */
3974 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3976 /* Extract hardware header fields */
3977 len = get_unaligned_le16(bus->rxhdr);
3978 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3980 /* All zeros means readahead info was bad */
3981 if (!(len | check)) {
3982 DHD_INFO(("%s (nextlen): read zeros in HW "
3983 "header???\n", __func__));
3984 dhdsdio_pktfree2(bus, pkt);
3988 /* Validate check bytes */
3989 if ((u16)~(len ^ check)) {
3990 DHD_ERROR(("%s (nextlen): HW hdr error:"
3991 " nextlen/len/check"
3992 " 0x%04x/0x%04x/0x%04x\n",
3993 __func__, nextlen, len, check));
3995 dhdsdio_rxfail(bus, false, false);
3996 dhdsdio_pktfree2(bus, pkt);
4000 /* Validate frame length */
4001 if (len < SDPCM_HDRLEN) {
4002 DHD_ERROR(("%s (nextlen): HW hdr length "
4003 "invalid: %d\n", __func__, len));
4004 dhdsdio_pktfree2(bus, pkt);
4008 /* Check for consistency withreadahead info */
4009 len_consistent = (nextlen != (roundup(len, 16) >> 4));
4010 if (len_consistent) {
4011 /* Mismatch, force retry w/normal
4012 header (may be >4K) */
4013 DHD_ERROR(("%s (nextlen): mismatch, "
4014 "nextlen %d len %d rnd %d; "
4015 "expected rxseq %d\n",
4017 len, roundup(len, 16), rxseq));
4018 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
4019 dhdsdio_pktfree2(bus, pkt);
4023 /* Extract software header fields */
4024 chan = SDPCM_PACKET_CHANNEL(
4025 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4026 seq = SDPCM_PACKET_SEQUENCE(
4027 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4028 doff = SDPCM_DOFFSET_VALUE(
4029 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4030 txmax = SDPCM_WINDOW_VALUE(
4031 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4034 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4035 SDPCM_NEXTLEN_OFFSET];
4036 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4037 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4038 __func__, bus->nextlen, seq));
4042 bus->dhd->rx_readahead_cnt++;
4044 /* Handle Flow Control */
4045 fcbits = SDPCM_FCMASK_VALUE(
4046 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4048 if (bus->flowcontrol != fcbits) {
4049 if (~bus->flowcontrol & fcbits)
4052 if (bus->flowcontrol & ~fcbits)
4056 bus->flowcontrol = fcbits;
4059 /* Check and update sequence number */
4061 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4062 "%d\n", __func__, seq, rxseq));
4067 /* Check window for sanity */
4068 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4069 DHD_ERROR(("%s: got unlikely tx max %d with "
4071 __func__, txmax, bus->tx_seq));
4072 txmax = bus->tx_seq + 2;
4074 bus->tx_max = txmax;
4077 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4078 printk(KERN_DEBUG "Rx Data:\n");
4079 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4081 } else if (DHD_HDRS_ON()) {
4082 printk(KERN_DEBUG "RxHdr:\n");
4083 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4084 bus->rxhdr, SDPCM_HDRLEN);
4088 if (chan == SDPCM_CONTROL_CHANNEL) {
4089 if (bus->bus == SPI_BUS) {
4090 dhdsdio_read_control(bus, rxbuf, len,
4093 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4095 /* Force retry w/normal header read */
4097 dhdsdio_rxfail(bus, false, true);
4099 dhdsdio_pktfree2(bus, pkt);
4103 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4104 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4109 /* Validate data offset */
4110 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4111 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4112 __func__, doff, len, SDPCM_HDRLEN));
4113 dhdsdio_rxfail(bus, false, false);
4114 dhdsdio_pktfree2(bus, pkt);
4118 /* All done with this one -- now deliver the packet */
4121 /* gSPI frames should not be handled in fractions */
4122 if (bus->bus == SPI_BUS)
4125 /* Read frame header (hardware and software) */
4126 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
4127 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4130 ASSERT(sdret != -BCME_PENDING);
4133 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4136 dhdsdio_rxfail(bus, true, true);
4140 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4141 printk(KERN_DEBUG "RxHdr:\n");
4142 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4143 bus->rxhdr, SDPCM_HDRLEN);
4147 /* Extract hardware header fields */
4148 len = get_unaligned_le16(bus->rxhdr);
4149 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4151 /* All zeros means no more frames */
4152 if (!(len | check)) {
4157 /* Validate check bytes */
4158 if ((u16) ~(len ^ check)) {
4159 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4160 __func__, len, check));
4162 dhdsdio_rxfail(bus, false, false);
4166 /* Validate frame length */
4167 if (len < SDPCM_HDRLEN) {
4168 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4173 /* Extract software header fields */
4174 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4175 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4176 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4177 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4179 /* Validate data offset */
4180 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4181 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4183 __func__, doff, len, SDPCM_HDRLEN, seq));
4186 dhdsdio_rxfail(bus, false, false);
4190 /* Save the readahead length if there is one */
4192 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4193 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4194 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4196 __func__, bus->nextlen, seq));
4200 /* Handle Flow Control */
4201 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4203 if (bus->flowcontrol != fcbits) {
4204 if (~bus->flowcontrol & fcbits)
4207 if (bus->flowcontrol & ~fcbits)
4211 bus->flowcontrol = fcbits;
4214 /* Check and update sequence number */
4216 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4222 /* Check window for sanity */
4223 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4224 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4225 __func__, txmax, bus->tx_seq));
4226 txmax = bus->tx_seq + 2;
4228 bus->tx_max = txmax;
4230 /* Call a separate function for control frames */
4231 if (chan == SDPCM_CONTROL_CHANNEL) {
4232 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4236 ASSERT((chan == SDPCM_DATA_CHANNEL)
4237 || (chan == SDPCM_EVENT_CHANNEL)
4238 || (chan == SDPCM_TEST_CHANNEL)
4239 || (chan == SDPCM_GLOM_CHANNEL));
4241 /* Length to read */
4242 rdlen = (len > firstread) ? (len - firstread) : 0;
4244 /* May pad read to blocksize for efficiency */
4245 if (bus->roundup && bus->blocksize &&
4246 (rdlen > bus->blocksize)) {
4247 pad = bus->blocksize - (rdlen % bus->blocksize);
4248 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4249 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4251 } else if (rdlen % DHD_SDALIGN) {
4252 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4255 /* Satisfy length-alignment requirements */
4256 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4257 rdlen = roundup(rdlen, ALIGNMENT);
4259 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4260 /* Too long -- skip this frame */
4261 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4262 __func__, len, rdlen));
4263 bus->dhd->rx_errors++;
4265 dhdsdio_rxfail(bus, false, false);
4269 dhd_os_sdlock_rxq(bus->dhd);
4270 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4272 /* Give up on data, request rtx of events */
4273 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4274 " chan %d\n", __func__, rdlen, chan));
4275 bus->dhd->rx_dropped++;
4276 dhd_os_sdunlock_rxq(bus->dhd);
4277 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4280 dhd_os_sdunlock_rxq(bus->dhd);
4282 ASSERT(!(pkt->prev));
4284 /* Leave room for what we already read, and align remainder */
4285 ASSERT(firstread < pkt->len);
4286 skb_pull(pkt, firstread);
4287 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4289 /* Read the remaining frame data */
4290 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4291 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4294 ASSERT(sdret != -BCME_PENDING);
4297 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4300 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4302 ? "data" : "test")),
4304 dhd_os_sdlock_rxq(bus->dhd);
4305 brcmu_pkt_buf_free_skb(pkt);
4306 dhd_os_sdunlock_rxq(bus->dhd);
4307 bus->dhd->rx_errors++;
4308 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4312 /* Copy the already-read portion */
4313 skb_push(pkt, firstread);
4314 memcpy(pkt->data, bus->rxhdr, firstread);
4317 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4318 printk(KERN_DEBUG "Rx Data:\n");
4319 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4325 /* Save superframe descriptor and allocate packet frame */
4326 if (chan == SDPCM_GLOM_CHANNEL) {
4327 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4328 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4331 if (DHD_GLOM_ON()) {
4332 printk(KERN_DEBUG "Glom Data:\n");
4333 print_hex_dump_bytes("",
4338 __skb_trim(pkt, len);
4339 ASSERT(doff == SDPCM_HDRLEN);
4340 skb_pull(pkt, SDPCM_HDRLEN);
4343 DHD_ERROR(("%s: glom superframe w/o "
4344 "descriptor!\n", __func__));
4345 dhdsdio_rxfail(bus, false, false);
4350 /* Fill in packet len and prio, deliver upward */
4351 __skb_trim(pkt, len);
4352 skb_pull(pkt, doff);
4355 /* Test channel packets are processed separately */
4356 if (chan == SDPCM_TEST_CHANNEL) {
4357 dhdsdio_testrcv(bus, pkt, seq);
4362 if (pkt->len == 0) {
4363 dhd_os_sdlock_rxq(bus->dhd);
4364 brcmu_pkt_buf_free_skb(pkt);
4365 dhd_os_sdunlock_rxq(bus->dhd);
4367 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4368 DHD_ERROR(("%s: rx protocol error\n", __func__));
4369 dhd_os_sdlock_rxq(bus->dhd);
4370 brcmu_pkt_buf_free_skb(pkt);
4371 dhd_os_sdunlock_rxq(bus->dhd);
4372 bus->dhd->rx_errors++;
4376 /* Unlock during rx call */
4377 dhd_os_sdunlock(bus->dhd);
4378 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4379 dhd_os_sdlock(bus->dhd);
4381 rxcount = maxframes - rxleft;
4383 /* Message if we hit the limit */
4384 if (!rxleft && !sdtest)
4385 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4388 #endif /* DHD_DEBUG */
4389 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4390 /* Back off rxseq if awaiting rtx, update rx_seq */
4393 bus->rx_seq = rxseq;
4398 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4400 struct sdpcmd_regs *regs = bus->regs;
4406 DHD_TRACE(("%s: Enter\n", __func__));
4408 /* Read mailbox data and ack that we did so */
4409 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4410 if (retries <= retry_limit)
4411 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4412 bus->f1regdata += 2;
4414 /* Dongle recomposed rx frames, accept them again */
4415 if (hmb_data & HMB_DATA_NAKHANDLED) {
4416 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4419 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4421 bus->rxskip = false;
4422 intstatus |= I_HMB_FRAME_IND;
4426 * DEVREADY does not occur with gSPI.
4428 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4430 (hmb_data & HMB_DATA_VERSION_MASK) >>
4431 HMB_DATA_VERSION_SHIFT;
4432 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4433 DHD_ERROR(("Version mismatch, dongle reports %d, "
4435 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4437 DHD_INFO(("Dongle ready, protocol version %d\n",
4442 * Flow Control has been moved into the RX headers and this out of band
4443 * method isn't used any more.
4444 * remaining backward compatible with older dongles.
4446 if (hmb_data & HMB_DATA_FC) {
4447 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4448 HMB_DATA_FCDATA_SHIFT;
4450 if (fcbits & ~bus->flowcontrol)
4453 if (bus->flowcontrol & ~fcbits)
4457 bus->flowcontrol = fcbits;
4460 /* Shouldn't be any others */
4461 if (hmb_data & ~(HMB_DATA_DEVREADY |
4462 HMB_DATA_NAKHANDLED |
4465 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4466 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4472 bool dhdsdio_dpc(dhd_bus_t *bus)
4474 bcmsdh_info_t *sdh = bus->sdh;
4475 struct sdpcmd_regs *regs = bus->regs;
4476 u32 intstatus, newstatus = 0;
4478 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4479 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4480 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4481 bool rxdone = true; /* Flag for no more read data */
4482 bool resched = false; /* Flag indicating resched wanted */
4484 DHD_TRACE(("%s: Enter\n", __func__));
4486 /* Start with leftover status bits */
4487 intstatus = bus->intstatus;
4489 dhd_os_sdlock(bus->dhd);
4491 /* If waiting for HTAVAIL, check status */
4492 if (bus->clkstate == CLK_PENDING) {
4494 u8 clkctl, devctl = 0;
4497 /* Check for inconsistent device control */
4499 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4501 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4503 bus->dhd->busstate = DHD_BUS_DOWN;
4505 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4507 #endif /* DHD_DEBUG */
4509 /* Read CSR, if clock on switch to AVAIL, else ignore */
4511 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4514 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4516 bus->dhd->busstate = DHD_BUS_DOWN;
4519 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4522 if (SBSDIO_HTAV(clkctl)) {
4524 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4527 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4529 bus->dhd->busstate = DHD_BUS_DOWN;
4531 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4532 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4535 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4537 bus->dhd->busstate = DHD_BUS_DOWN;
4539 bus->clkstate = CLK_AVAIL;
4547 /* Make sure backplane clock is on */
4548 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4549 if (bus->clkstate == CLK_PENDING)
4552 /* Pending interrupt indicates new device status */
4555 R_SDREG(newstatus, ®s->intstatus, retries);
4557 if (bcmsdh_regfail(bus->sdh))
4559 newstatus &= bus->hostintmask;
4560 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4562 W_SDREG(newstatus, ®s->intstatus, retries);
4567 /* Merge new bits with previous */
4568 intstatus |= newstatus;
4571 /* Handle flow-control change: read new state in case our ack
4572 * crossed another change interrupt. If change still set, assume
4573 * FC ON for safety, let next loop through do the debounce.
4575 if (intstatus & I_HMB_FC_CHANGE) {
4576 intstatus &= ~I_HMB_FC_CHANGE;
4577 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4578 R_SDREG(newstatus, ®s->intstatus, retries);
4579 bus->f1regdata += 2;
4581 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4582 intstatus |= (newstatus & bus->hostintmask);
4585 /* Handle host mailbox indication */
4586 if (intstatus & I_HMB_HOST_INT) {
4587 intstatus &= ~I_HMB_HOST_INT;
4588 intstatus |= dhdsdio_hostmail(bus);
4591 /* Generally don't ask for these, can get CRC errors... */
4592 if (intstatus & I_WR_OOSYNC) {
4593 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4594 intstatus &= ~I_WR_OOSYNC;
4597 if (intstatus & I_RD_OOSYNC) {
4598 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4599 intstatus &= ~I_RD_OOSYNC;
4602 if (intstatus & I_SBINT) {
4603 DHD_ERROR(("Dongle reports SBINT\n"));
4604 intstatus &= ~I_SBINT;
4607 /* Would be active due to wake-wlan in gSPI */
4608 if (intstatus & I_CHIPACTIVE) {
4609 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4610 intstatus &= ~I_CHIPACTIVE;
4613 /* Ignore frame indications if rxskip is set */
4615 intstatus &= ~I_HMB_FRAME_IND;
4617 /* On frame indication, read available frames */
4618 if (PKT_AVAILABLE()) {
4619 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4620 if (rxdone || bus->rxskip)
4621 intstatus &= ~I_HMB_FRAME_IND;
4622 rxlimit -= min(framecnt, rxlimit);
4625 /* Keep still-pending events for next scheduling */
4626 bus->intstatus = intstatus;
4629 #if defined(OOB_INTR_ONLY)
4630 bcmsdh_oob_intr_set(1);
4631 #endif /* (OOB_INTR_ONLY) */
4632 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4633 * or clock availability. (Allows tx loop to check ipend if desired.)
4634 * (Unless register access seems hosed, as we may not be able to ACK...)
4636 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4637 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4638 __func__, rxdone, framecnt));
4639 bus->intdis = false;
4640 bcmsdh_intr_enable(sdh);
4643 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4644 (bus->clkstate == CLK_AVAIL)) {
4648 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4649 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4650 (u32) bus->ctrl_frame_len, NULL,
4652 ASSERT(ret != -BCME_PENDING);
4655 /* On failure, abort the command and
4656 terminate the frame */
4657 DHD_INFO(("%s: sdio error %d, abort command and "
4658 "terminate frame.\n", __func__, ret));
4661 bcmsdh_abort(sdh, SDIO_FUNC_2);
4663 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4664 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4668 for (i = 0; i < 3; i++) {
4670 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4671 SBSDIO_FUNC1_WFRAMEBCHI,
4673 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4674 SBSDIO_FUNC1_WFRAMEBCLO,
4676 bus->f1regdata += 2;
4677 if ((hi == 0) && (lo == 0))
4683 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4685 DHD_INFO(("Return_dpc value is : %d\n", ret));
4686 bus->ctrl_frame_stat = false;
4687 dhd_wait_event_wakeup(bus->dhd);
4689 /* Send queued frames (limit 1 if rx may still be pending) */
4690 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4691 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4693 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4694 framecnt = dhdsdio_sendfromq(bus, framecnt);
4695 txlimit -= framecnt;
4698 /* Resched if events or tx frames are pending,
4699 else await next interrupt */
4700 /* On failed register access, all bets are off:
4701 no resched or interrupts */
4702 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4703 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4704 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4705 bus->dhd->busstate = DHD_BUS_DOWN;
4707 } else if (bus->clkstate == CLK_PENDING) {
4708 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4709 "I_CHIPACTIVE interrupt\n", __func__));
4711 } else if (bus->intstatus || bus->ipend ||
4712 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4713 && DATAOK(bus)) || PKT_AVAILABLE()) {
4717 bus->dpc_sched = resched;
4719 /* If we're done for now, turn off clock request. */
4720 if ((bus->clkstate != CLK_PENDING)
4721 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4722 bus->activity = false;
4723 dhdsdio_clkctl(bus, CLK_NONE, false);
4726 dhd_os_sdunlock(bus->dhd);
4731 bool dhd_bus_dpc(struct dhd_bus *bus)
4735 /* Call the DPC directly. */
4736 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4737 resched = dhdsdio_dpc(bus);
4742 void dhdsdio_isr(void *arg)
4744 dhd_bus_t *bus = (dhd_bus_t *) arg;
4747 DHD_TRACE(("%s: Enter\n", __func__));
4750 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4755 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4756 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4760 /* Count the interrupt call */
4764 /* Shouldn't get this interrupt if we're sleeping? */
4765 if (bus->sleeping) {
4766 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4770 /* Disable additional interrupts (is this needed now)? */
4772 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4774 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4776 bcmsdh_intr_disable(sdh);
4779 #if defined(SDIO_ISR_THREAD)
4780 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4781 while (dhdsdio_dpc(bus))
4784 bus->dpc_sched = true;
4785 dhd_sched_dpc(bus->dhd);
4791 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4793 /* Default to specified length, or full range */
4794 if (dhd_pktgen_len) {
4795 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4796 bus->pktgen_minlen = bus->pktgen_maxlen;
4798 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4799 bus->pktgen_minlen = 0;
4801 bus->pktgen_len = (u16) bus->pktgen_minlen;
4803 /* Default to per-watchdog burst with 10s print time */
4804 bus->pktgen_freq = 1;
4805 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4806 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4808 /* Default to echo mode */
4809 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4810 bus->pktgen_stop = 1;
4813 static void dhdsdio_pktgen(dhd_bus_t *bus)
4815 struct sk_buff *pkt;
4821 /* Display current count if appropriate */
4822 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4823 bus->pktgen_ptick = 0;
4824 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4825 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4828 /* For recv mode, just make sure dongle has started sending */
4829 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4830 if (!bus->pktgen_rcvd)
4831 dhdsdio_sdtest_set(bus, true);
4835 /* Otherwise, generate or request the specified number of packets */
4836 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4837 /* Stop if total has been reached */
4838 if (bus->pktgen_total
4839 && (bus->pktgen_sent >= bus->pktgen_total)) {
4840 bus->pktgen_count = 0;
4844 /* Allocate an appropriate-sized packet */
4845 len = bus->pktgen_len;
4846 pkt = brcmu_pkt_buf_get_skb(
4847 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4850 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4854 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4856 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4858 /* Write test header cmd and extra based on mode */
4859 switch (bus->pktgen_mode) {
4860 case DHD_PKTGEN_ECHO:
4861 *data++ = SDPCM_TEST_ECHOREQ;
4862 *data++ = (u8) bus->pktgen_sent;
4865 case DHD_PKTGEN_SEND:
4866 *data++ = SDPCM_TEST_DISCARD;
4867 *data++ = (u8) bus->pktgen_sent;
4870 case DHD_PKTGEN_RXBURST:
4871 *data++ = SDPCM_TEST_BURST;
4872 *data++ = (u8) bus->pktgen_count;
4876 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4878 brcmu_pkt_buf_free_skb(pkt, true);
4879 bus->pktgen_count = 0;
4883 /* Write test header length field */
4884 *data++ = (len >> 0);
4885 *data++ = (len >> 8);
4887 /* Then fill in the remainder -- N/A for burst,
4889 for (fillbyte = 0; fillbyte < len; fillbyte++)
4891 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4894 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4895 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4896 printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4897 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4898 pkt->len - SDPCM_HDRLEN);
4903 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4905 if (bus->pktgen_stop
4906 && bus->pktgen_stop == bus->pktgen_fail)
4907 bus->pktgen_count = 0;
4911 /* Bump length if not fixed, wrap at max */
4912 if (++bus->pktgen_len > bus->pktgen_maxlen)
4913 bus->pktgen_len = (u16) bus->pktgen_minlen;
4915 /* Special case for burst mode: just send one request! */
4916 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4921 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4923 struct sk_buff *pkt;
4926 /* Allocate the packet */
4927 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4930 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4933 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4934 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4936 /* Fill in the test header */
4937 *data++ = SDPCM_TEST_SEND;
4939 *data++ = (bus->pktgen_maxlen >> 0);
4940 *data++ = (bus->pktgen_maxlen >> 8);
4943 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4947 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4957 /* Check for min length */
4959 if (pktlen < SDPCM_TEST_HDRLEN) {
4960 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4962 brcmu_pkt_buf_free_skb(pkt, false);
4966 /* Extract header fields */
4971 len += *data++ << 8;
4973 /* Check length for relevant commands */
4974 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4975 || cmd == SDPCM_TEST_ECHORSP) {
4976 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4977 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4978 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4979 pktlen, seq, cmd, extra, len));
4980 brcmu_pkt_buf_free_skb(pkt, false);
4985 /* Process as per command */
4987 case SDPCM_TEST_ECHOREQ:
4988 /* Rx->Tx turnaround ok (even on NDIS w/current
4990 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4991 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4995 brcmu_pkt_buf_free_skb(pkt, false);
5000 case SDPCM_TEST_ECHORSP:
5001 if (bus->ext_loop) {
5002 brcmu_pkt_buf_free_skb(pkt, false);
5007 for (offset = 0; offset < len; offset++, data++) {
5008 if (*data != SDPCM_TEST_FILL(offset, extra)) {
5009 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
5011 SDPCM_TEST_FILL(offset, extra), *data));
5015 brcmu_pkt_buf_free_skb(pkt, false);
5019 case SDPCM_TEST_DISCARD:
5020 brcmu_pkt_buf_free_skb(pkt, false);
5024 case SDPCM_TEST_BURST:
5025 case SDPCM_TEST_SEND:
5027 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
5028 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
5029 pktlen, seq, cmd, extra, len));
5030 brcmu_pkt_buf_free_skb(pkt, false);
5034 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5035 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
5036 if (bus->pktgen_total
5037 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5038 bus->pktgen_count = 0;
5039 dhdsdio_sdtest_set(bus, false);
5045 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
5049 DHD_TIMER(("%s: Enter\n", __func__));
5053 if (bus->dhd->dongle_reset)
5056 /* Ignore the timer if simulating bus down */
5060 dhd_os_sdlock(bus->dhd);
5062 /* Poll period: check device if appropriate. */
5063 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5066 /* Reset poll tick */
5069 /* Check device if no interrupts */
5070 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5072 if (!bus->dpc_sched) {
5074 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5078 devpend & (INTR_STATUS_FUNC1 |
5082 /* If there is something, make like the ISR and
5088 bcmsdh_intr_disable(bus->sdh);
5090 bus->dpc_sched = true;
5091 dhd_sched_dpc(bus->dhd);
5096 /* Update interrupt tracking */
5097 bus->lastintrs = bus->intrcount;
5100 /* Poll for console output periodically */
5101 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5102 bus->console.count += dhd_watchdog_ms;
5103 if (bus->console.count >= dhd_console_ms) {
5104 bus->console.count -= dhd_console_ms;
5105 /* Make sure backplane clock is on */
5106 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5107 if (dhdsdio_readconsole(bus) < 0)
5108 dhd_console_ms = 0; /* On error,
5112 #endif /* DHD_DEBUG */
5115 /* Generate packets if configured */
5116 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5117 /* Make sure backplane clock is on */
5118 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5119 bus->pktgen_tick = 0;
5120 dhdsdio_pktgen(bus);
5124 /* On idle timeout clear activity flag and/or turn off clock */
5125 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5126 if (++bus->idlecount >= bus->idletime) {
5128 if (bus->activity) {
5129 bus->activity = false;
5130 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5132 dhdsdio_clkctl(bus, CLK_NONE, false);
5137 dhd_os_sdunlock(bus->dhd);
5143 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
5145 dhd_bus_t *bus = dhdp->bus;
5148 struct sk_buff *pkt;
5150 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5151 if (bus->console_addr == 0)
5154 /* Exclusive bus access */
5155 dhd_os_sdlock(bus->dhd);
5157 /* Don't allow input if dongle is in reset */
5158 if (bus->dhd->dongle_reset) {
5159 dhd_os_sdunlock(bus->dhd);
5163 /* Request clock to allow SDIO accesses */
5165 /* No pend allowed since txpkt is called later, ht clk has to be on */
5166 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5168 /* Zero cbuf_index */
5169 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5170 val = cpu_to_le32(0);
5171 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5175 /* Write message into cbuf */
5176 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5177 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5181 /* Write length into vcons_in */
5182 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5183 val = cpu_to_le32(msglen);
5184 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5188 /* Bump dongle by sending an empty event pkt.
5189 * sdpcm_sendup (RX) checks for virtual console input.
5191 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5192 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5193 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5196 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5197 bus->activity = false;
5198 dhdsdio_clkctl(bus, CLK_NONE, true);
5201 dhd_os_sdunlock(bus->dhd);
5205 #endif /* DHD_DEBUG */
5207 static bool dhdsdio_chipmatch(u16 chipid)
5209 if (chipid == BCM4325_CHIP_ID)
5211 if (chipid == BCM4329_CHIP_ID)
5213 if (chipid == BCM4319_CHIP_ID)
5218 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5219 u16 slot, u16 func, uint bustype, void *regsva,
5225 /* Init global variables at run-time, not as part of the declaration.
5226 * This is required to support init/de-init of the driver.
5228 * of globals as part of the declaration results in non-deterministic
5229 * behavior since the value of the globals may be different on the
5230 * first time that the driver is initialized vs subsequent
5233 dhd_txbound = DHD_TXBOUND;
5234 dhd_rxbound = DHD_RXBOUND;
5235 dhd_alignctl = true;
5237 dhd_readahead = true;
5239 dhd_dongle_memsize = 0;
5240 dhd_txminmax = DHD_TXMINMAX;
5246 DHD_TRACE(("%s: Enter\n", __func__));
5247 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5249 /* We make assumptions about address window mappings */
5250 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5252 /* BCMSDH passes venid and devid based on CIS parsing -- but
5254 * means early parse could fail, so here we should get either an ID
5255 * we recognize OR (-1) indicating we must request power first.
5257 /* Check the Vendor ID */
5260 case PCI_VENDOR_ID_BROADCOM:
5263 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5267 /* Check the Device ID and make sure it's one that we support */
5269 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5270 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5271 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5272 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5274 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5275 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5276 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5278 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5280 case BCM4319_D11N_ID: /* 4319 802.11n id */
5281 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5282 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5283 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5286 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5291 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5292 __func__, venid, devid));
5296 /* Allocate private bus interface state */
5297 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5299 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5303 bus->cl_devid = (u16) devid;
5305 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5306 bus->usebufpool = false; /* Use bufpool if allocated,
5307 else use locally malloced rxbuf */
5309 /* attempt to attach to the dongle */
5310 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5311 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5315 /* Attach to the dhd/OS/network interface */
5316 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5318 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5322 /* Allocate buffers */
5323 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5324 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5328 if (!(dhdsdio_probe_init(bus, sdh))) {
5329 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5333 /* Register interrupt callback, but mask it (not operational yet). */
5334 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5336 bcmsdh_intr_disable(sdh);
5337 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5339 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5343 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5345 DHD_INFO(("%s: completed!!\n", __func__));
5347 /* if firmware path present try to download and bring up bus */
5348 ret = dhd_bus_start(bus->dhd);
5350 if (ret == -ENOLINK) {
5351 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5355 /* Ok, have the per-port tell the stack we're open for business */
5356 if (dhd_net_attach(bus->dhd, 0) != 0) {
5357 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5364 dhdsdio_release(bus);
5369 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5374 bus->alp_only = true;
5376 /* Return the window to backplane enumeration space for core access */
5377 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5378 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5381 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5382 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5384 #endif /* DHD_DEBUG */
5387 * Force PLL off until dhdsdio_chip_attach()
5388 * programs PLL control regs
5391 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5392 DHD_INIT_CLKCTL1, &err);
5395 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5398 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5399 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5400 "0x%02x read 0x%02x\n",
5401 err, DHD_INIT_CLKCTL1, clkctl));
5405 if (dhdsdio_chip_attach(bus, regsva)) {
5406 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5410 bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5412 if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5413 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5414 __func__, bus->ci->chip));
5418 dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5420 /* Get info on the ARM and SOCRAM cores... */
5421 if (!DHD_NOPMU(bus)) {
5422 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5423 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5424 bus->orig_ramsize = bus->ci->ramsize;
5425 if (!(bus->orig_ramsize)) {
5426 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5430 bus->ramsize = bus->orig_ramsize;
5431 if (dhd_dongle_memsize)
5432 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5434 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5435 bus->ramsize, bus->orig_ramsize));
5438 bus->regs = (void *)bus->ci->buscorebase;
5440 /* Set core control so an SDIO reset does a backplane reset */
5441 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5443 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5445 /* Locate an appropriately-aligned portion of hdrbuf */
5446 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5448 /* Set the poll and/or interrupt flags */
5449 bus->intr = (bool) dhd_intr;
5450 bus->poll = (bool) dhd_poll;
5460 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5462 DHD_TRACE(("%s: Enter\n", __func__));
5464 if (bus->dhd->maxctl) {
5466 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5467 ALIGNMENT) + DHD_SDALIGN;
5468 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5469 if (!(bus->rxbuf)) {
5470 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5471 __func__, bus->rxblen));
5476 /* Allocate buffer to receive glomed packet */
5477 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5478 if (!(bus->databuf)) {
5479 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5480 __func__, MAX_DATA_BUF));
5481 /* release rxbuf which was already located as above */
5487 /* Align the buffer */
5488 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5490 bus->databuf + (DHD_SDALIGN -
5491 ((unsigned long)bus->databuf % DHD_SDALIGN));
5493 bus->dataptr = bus->databuf;
5501 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5505 DHD_TRACE(("%s: Enter\n", __func__));
5508 dhdsdio_pktgen_init(bus);
5511 /* Disable F2 to clear any intermediate frame state on the dongle */
5512 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
5515 bus->dhd->busstate = DHD_BUS_DOWN;
5516 bus->sleeping = false;
5517 bus->rxflow = false;
5518 bus->prev_rxlim_hit = 0;
5520 /* Done with backplane-dependent accesses, can drop clock... */
5521 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5523 /* ...and initialize clock/power states */
5524 bus->clkstate = CLK_SDONLY;
5525 bus->idletime = (s32) dhd_idletime;
5526 bus->idleclock = DHD_IDLE_ACTIVE;
5528 /* Query the F2 block size, set roundup accordingly */
5530 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5531 &bus->blocksize, sizeof(s32), false) != 0) {
5533 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5535 DHD_INFO(("%s: Initial value for %s is %d\n",
5536 __func__, "sd_blocksize", bus->blocksize));
5538 bus->roundup = min(max_roundup, bus->blocksize);
5540 /* Query if bus module supports packet chaining,
5541 default to use if supported */
5542 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5543 &bus->sd_rxchain, sizeof(s32),
5545 bus->sd_rxchain = false;
5547 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5549 (bus->sd_rxchain ? "supports" : "does not support")));
5551 bus->use_rxchain = (bool) bus->sd_rxchain;
5557 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5560 bus->fw_path = fw_path;
5561 bus->nv_path = nv_path;
5563 ret = dhdsdio_download_firmware(bus, bus->sdh);
5569 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5573 /* Download the firmware */
5574 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5576 ret = _dhdsdio_download_firmware(bus) == 0;
5578 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5583 /* Detach and free everything */
5584 static void dhdsdio_release(dhd_bus_t *bus)
5586 DHD_TRACE(("%s: Enter\n", __func__));
5589 /* De-register interrupt handler */
5590 bcmsdh_intr_disable(bus->sdh);
5591 bcmsdh_intr_dereg(bus->sdh);
5594 dhd_detach(bus->dhd);
5595 dhdsdio_release_dongle(bus);
5599 dhdsdio_release_malloc(bus);
5604 DHD_TRACE(("%s: Disconnected\n", __func__));
5607 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5609 DHD_TRACE(("%s: Enter\n", __func__));
5611 if (bus->dhd && bus->dhd->dongle_reset)
5616 bus->rxctl = bus->rxbuf = NULL;
5620 kfree(bus->databuf);
5621 bus->databuf = NULL;
5624 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5626 DHD_TRACE(("%s: Enter\n", __func__));
5628 if (bus->dhd && bus->dhd->dongle_reset)
5632 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5633 dhdsdio_clkctl(bus, CLK_NONE, false);
5634 dhdsdio_chip_detach(bus);
5635 if (bus->vars && bus->varsz)
5640 DHD_TRACE(("%s: Disconnected\n", __func__));
5643 static void dhdsdio_disconnect(void *ptr)
5645 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5647 DHD_TRACE(("%s: Enter\n", __func__));
5651 dhdsdio_release(bus);
5654 DHD_TRACE(("%s: Disconnected\n", __func__));
5657 /* Register/Unregister functions are called by the main DHD entry
5658 * point (e.g. module insertion) to link with the bus driver, in
5659 * order to look for or await the device.
5662 static bcmsdh_driver_t dhd_sdio = {
5667 int dhd_bus_register(void)
5669 DHD_TRACE(("%s: Enter\n", __func__));
5671 return bcmsdh_register(&dhd_sdio);
5674 void dhd_bus_unregister(void)
5676 DHD_TRACE(("%s: Enter\n", __func__));
5678 bcmsdh_unregister();
5681 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5687 u8 *memblock = NULL, *memptr;
5689 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5691 image = dhd_os_open_image(fw_path);
5695 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5696 if (memblock == NULL) {
5697 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5698 __func__, MEMBLOCK));
5701 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5703 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5705 /* Download image */
5707 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5708 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5710 DHD_ERROR(("%s: error %d on writing %d membytes at "
5711 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5722 dhd_os_close_image(image);
5728 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5729 * and ending in a NUL.
5730 * Removes carriage returns, empty lines, comment lines, and converts
5732 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5736 static uint process_nvram_vars(char *varbuf, uint len)
5745 findNewline = false;
5748 for (n = 0; n < len; n++) {
5751 if (varbuf[n] == '\r')
5753 if (findNewline && varbuf[n] != '\n')
5755 findNewline = false;
5756 if (varbuf[n] == '#') {
5760 if (varbuf[n] == '\n') {
5770 buf_len = dp - varbuf;
5772 while (dp < varbuf + n)
5779 EXAMPLE: nvram_array
5782 Use carriage return at the end of each assignment,
5783 and an empty string with
5784 carriage return at the end of array.
5787 unsigned char nvram_array[] = {"name1=value1\n",
5788 "name2=value2\n", "\n"};
5789 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5791 Search "EXAMPLE: nvram_array" to see how the array is activated.
5794 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5796 bus->nvram_params = nvram_params;
5799 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5804 char *memblock = NULL;
5807 bool nvram_file_exists;
5809 nv_path = bus->nv_path;
5811 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5812 if (!nvram_file_exists && (bus->nvram_params == NULL))
5815 if (nvram_file_exists) {
5816 image = dhd_os_open_image(nv_path);
5821 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5822 if (memblock == NULL) {
5823 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5824 __func__, MEMBLOCK));
5828 /* Download variables */
5829 if (nvram_file_exists) {
5830 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5832 len = strlen(bus->nvram_params);
5833 ASSERT(len <= MEMBLOCK);
5836 memcpy(memblock, bus->nvram_params, len);
5839 if (len > 0 && len < MEMBLOCK) {
5840 bufp = (char *)memblock;
5842 len = process_nvram_vars(bufp, len);
5846 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5848 DHD_ERROR(("%s: error downloading vars: %d\n",
5849 __func__, bcmerror));
5852 DHD_ERROR(("%s: error reading nvram file: %d\n",
5861 dhd_os_close_image(image);
5866 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5870 bool embed = false; /* download embedded firmware */
5871 bool dlok = false; /* download firmware succeeded */
5873 /* Out immediately if no image to download */
5874 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5877 /* Keep arm in reset */
5878 if (dhdsdio_download_state(bus, true)) {
5879 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5883 /* External image takes precedence if specified */
5884 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5885 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5886 DHD_ERROR(("%s: dongle image file download failed\n",
5895 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5899 /* EXAMPLE: nvram_array */
5900 /* If a valid nvram_arry is specified as above, it can be passed
5902 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5904 /* External nvram takes precedence if specified */
5905 if (dhdsdio_download_nvram(bus)) {
5906 DHD_ERROR(("%s: dongle nvram file download failed\n",
5910 /* Take arm out of reset */
5911 if (dhdsdio_download_state(bus, false)) {
5912 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5925 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5926 u8 *buf, uint nbytes, struct sk_buff *pkt,
5927 bcmsdh_cmplt_fn_t complete, void *handle)
5929 return bcmsdh_send_buf
5930 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5934 uint dhd_bus_chip(struct dhd_bus *bus)
5936 ASSERT(bus->ci != NULL);
5937 return bus->ci->chip;
5940 void *dhd_bus_pub(struct dhd_bus *bus)
5945 void *dhd_bus_txq(struct dhd_bus *bus)
5950 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5952 return SDPCM_HDRLEN;
5955 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5963 if (!bus->dhd->dongle_reset) {
5964 /* Expect app to have torn down any
5965 connection before calling */
5966 /* Stop the bus, disable F2 */
5967 dhd_bus_stop(bus, false);
5969 /* Clean tx/rx buffer pointers,
5970 detach from the dongle */
5971 dhdsdio_release_dongle(bus);
5973 bus->dhd->dongle_reset = true;
5974 bus->dhd->up = false;
5976 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5977 /* App can now remove power from device */
5981 /* App must have restored power to device before calling */
5983 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5985 if (bus->dhd->dongle_reset) {
5987 /* Reset SD client */
5988 bcmsdh_reset(bus->sdh);
5990 /* Attempt to re-attach & download */
5991 if (dhdsdio_probe_attach(bus, bus->sdh,
5992 (u32 *) SI_ENUM_BASE,
5994 /* Attempt to download binary to the dongle */
5995 if (dhdsdio_probe_init
5997 && dhdsdio_download_firmware(bus,
6000 /* Re-init bus, enable F2 transfer */
6001 dhd_bus_init((dhd_pub_t *) bus->dhd,
6004 #if defined(OOB_INTR_ONLY)
6005 dhd_enable_oob_intr(bus, true);
6006 #endif /* defined(OOB_INTR_ONLY) */
6008 bus->dhd->dongle_reset = false;
6009 bus->dhd->up = true;
6011 DHD_TRACE(("%s: WLAN ON DONE\n",
6018 bcmerror = -EISCONN;
6019 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6020 "is on\n", __func__));
6028 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
6034 * Chipid is assume to be at offset 0 from regs arg
6035 * For different chiptypes or old sdio hosts w/o chipcommon,
6036 * other ways of recognition should be added here.
6038 ci->cccorebase = (u32)regs;
6039 regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
6040 ci->chip = regdata & CID_ID_MASK;
6041 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6043 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6044 __func__, ci->chip, ci->chiprev));
6046 /* Address of cores for new chips should be added here */
6048 case BCM4329_CHIP_ID:
6049 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6050 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6051 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6052 ci->ramsize = BCM4329_RAMSIZE;
6055 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6056 __func__, ci->chip));
6060 regdata = bcmsdh_reg_read(sdh,
6061 CORE_SB(ci->cccorebase, sbidhigh), 4);
6062 ci->ccrev = SBCOREREV(regdata);
6064 regdata = bcmsdh_reg_read(sdh,
6065 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6066 ci->pmurev = regdata & PCAP_REV_MASK;
6068 regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6069 ci->buscorerev = SBCOREREV(regdata);
6070 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6072 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6073 __func__, ci->ccrev, ci->pmurev,
6074 ci->buscorerev, ci->buscoretype));
6076 /* get chipcommon capabilites */
6077 ci->cccaps = bcmsdh_reg_read(sdh,
6078 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6084 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6088 regdata = bcmsdh_reg_read(sdh,
6089 CORE_SB(corebase, sbtmstatelow), 4);
6090 if (regdata & SBTML_RESET)
6093 regdata = bcmsdh_reg_read(sdh,
6094 CORE_SB(corebase, sbtmstatelow), 4);
6095 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6097 * set target reject and spin until busy is clear
6098 * (preserve core-specific bits)
6100 regdata = bcmsdh_reg_read(sdh,
6101 CORE_SB(corebase, sbtmstatelow), 4);
6102 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6103 regdata | SBTML_REJ);
6105 regdata = bcmsdh_reg_read(sdh,
6106 CORE_SB(corebase, sbtmstatelow), 4);
6108 SPINWAIT((bcmsdh_reg_read(sdh,
6109 CORE_SB(corebase, sbtmstatehigh), 4) &
6110 SBTMH_BUSY), 100000);
6112 regdata = bcmsdh_reg_read(sdh,
6113 CORE_SB(corebase, sbtmstatehigh), 4);
6114 if (regdata & SBTMH_BUSY)
6115 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6117 regdata = bcmsdh_reg_read(sdh,
6118 CORE_SB(corebase, sbidlow), 4);
6119 if (regdata & SBIDL_INIT) {
6120 regdata = bcmsdh_reg_read(sdh,
6121 CORE_SB(corebase, sbimstate), 4) |
6123 bcmsdh_reg_write(sdh,
6124 CORE_SB(corebase, sbimstate), 4,
6126 regdata = bcmsdh_reg_read(sdh,
6127 CORE_SB(corebase, sbimstate), 4);
6129 SPINWAIT((bcmsdh_reg_read(sdh,
6130 CORE_SB(corebase, sbimstate), 4) &
6134 /* set reset and reject while enabling the clocks */
6135 bcmsdh_reg_write(sdh,
6136 CORE_SB(corebase, sbtmstatelow), 4,
6137 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6138 SBTML_REJ | SBTML_RESET));
6139 regdata = bcmsdh_reg_read(sdh,
6140 CORE_SB(corebase, sbtmstatelow), 4);
6143 /* clear the initiator reject bit */
6144 regdata = bcmsdh_reg_read(sdh,
6145 CORE_SB(corebase, sbidlow), 4);
6146 if (regdata & SBIDL_INIT) {
6147 regdata = bcmsdh_reg_read(sdh,
6148 CORE_SB(corebase, sbimstate), 4) &
6150 bcmsdh_reg_write(sdh,
6151 CORE_SB(corebase, sbimstate), 4,
6156 /* leave reset and reject asserted */
6157 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6158 (SBTML_REJ | SBTML_RESET));
6163 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6165 struct chip_info *ci;
6169 DHD_TRACE(("%s: Enter\n", __func__));
6171 /* alloc chip_info_t */
6172 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6174 DHD_ERROR(("%s: malloc failed!\n", __func__));
6178 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6180 /* bus/core/clk setup for register access */
6181 /* Try forcing SDIO core to do ALPAvail request only */
6182 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6183 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6186 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6190 /* If register supported, wait for ALPAvail and then force ALP */
6191 /* This may take up to 15 milliseconds */
6192 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6193 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6194 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6196 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6197 SBSDIO_FUNC1_CHIPCLKCSR,
6199 !SBSDIO_ALPAV(clkval)),
6200 PMU_MAX_TRANSITION_DLY);
6201 if (!SBSDIO_ALPAV(clkval)) {
6202 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6207 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6209 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6210 SBSDIO_FUNC1_CHIPCLKCSR,
6214 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6215 __func__, clkset, clkval));
6220 /* Also, disable the extra SDIO pull-ups */
6221 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6224 err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6229 * Make sure any on-chip ARM is off (in case strapping is wrong),
6230 * or downloaded code was already running.
6232 dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6234 bcmsdh_reg_write(bus->sdh,
6235 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6236 bcmsdh_reg_write(bus->sdh,
6237 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6239 /* Disable F2 to clear any intermediate frame state on the dongle */
6240 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6241 SDIO_FUNC_ENABLE_1, NULL);
6243 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6244 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6247 /* Done with backplane-dependent accesses, can drop clock... */
6248 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6260 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6265 * Must do the disable sequence first to work for
6266 * arbitrary current core state.
6268 dhdsdio_chip_disablecore(sdh, corebase);
6271 * Now do the initialization sequence.
6272 * set reset while enabling the clock and
6273 * forcing them on throughout the core
6275 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6276 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6280 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6281 if (regdata & SBTMH_SERR)
6282 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6284 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6285 if (regdata & (SBIM_IBE | SBIM_TO))
6286 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6287 regdata & ~(SBIM_IBE | SBIM_TO));
6289 /* clear reset and allow it to propagate throughout the core */
6290 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6291 (SICF_FGC << SBTML_SICF_SHIFT) |
6292 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6295 /* leave clock enabled */
6296 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6297 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6301 /* SDIO Pad drive strength to select value mappings */
6302 struct sdiod_drive_str {
6303 u8 strength; /* Pad Drive Strength in mA */
6304 u8 sel; /* Chip-specific select value */
6307 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6308 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6316 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6317 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6328 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6329 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6341 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6344 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6345 struct sdiod_drive_str *str_tab = NULL;
6350 if (!(bus->ci->cccaps & CC_CAP_PMU))
6353 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6354 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6355 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6356 str_mask = 0x30000000;
6359 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6360 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6361 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6362 str_mask = 0x00003800;
6365 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6366 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6367 str_mask = 0x00003800;
6371 DHD_ERROR(("No SDIO Drive strength init"
6372 "done for chip %s rev %d pmurev %d\n",
6373 brcmu_chipname(bus->ci->chip, chn, 8),
6374 bus->ci->chiprev, bus->ci->pmurev));
6378 if (str_tab != NULL) {
6379 u32 drivestrength_sel = 0;
6383 for (i = 0; str_tab[i].strength != 0; i++) {
6384 if (drivestrength >= str_tab[i].strength) {
6385 drivestrength_sel = str_tab[i].sel;
6390 bcmsdh_reg_write(bus->sdh,
6391 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6393 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6394 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6395 cc_data_temp &= ~str_mask;
6396 drivestrength_sel <<= str_shift;
6397 cc_data_temp |= drivestrength_sel;
6398 bcmsdh_reg_write(bus->sdh,
6399 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6402 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6403 drivestrength, cc_data_temp));
6408 dhdsdio_chip_detach(struct dhd_bus *bus)
6410 DHD_TRACE(("%s: Enter\n", __func__));
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