2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include BCMEMBEDIMAGE
23 #endif /* BCMEMBEDIMAGE */
27 #include <bcmendian.h>
34 #include <hndrte_armtrap.h>
35 #include <hndrte_cons.h>
36 #endif /* DHD_DEBUG */
42 #include <sbsdpcmdev.h>
45 #include <proto/ethernet.h>
46 #include <proto/802.1d.h>
47 #include <proto/802.11.h>
49 #include <dngl_stats.h>
52 #include <dhd_proto.h>
56 #include <siutils_priv.h>
58 #ifndef DHDSDIO_MEM_DUMP_FNAME
59 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
62 #define QLEN 256 /* bulk rx and tx queue lengths */
63 #define FCHI (QLEN - 10)
64 #define FCLOW (FCHI / 2)
67 #define TXRETRIES 2 /* # of retries for tx frames */
69 #if defined(CONFIG_MACH_SANDGATE2G)
70 #define DHD_RXBOUND 250 /* Default for max rx frames in
73 #define DHD_RXBOUND 50 /* Default for max rx frames in
75 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
77 #define DHD_TXBOUND 20 /* Default for max tx frames in
80 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
82 #define MEMBLOCK 2048 /* Block size used for downloading
84 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
85 biggest possible glom */
87 /* Packet alignment for most efficient SDIO (can change based on platform) */
89 #define DHD_SDALIGN 32
91 #if !ISPOWEROF2(DHD_SDALIGN)
92 #error DHD_SDALIGN is not a power of 2!
96 #define DHD_FIRSTREAD 32
98 #if !ISPOWEROF2(DHD_FIRSTREAD)
99 #error DHD_FIRSTREAD is not a power of 2!
102 /* Total length of frame header for dongle protocol */
103 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
105 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
107 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
110 /* Space for header read, limit for data packets */
112 #define MAX_HDR_READ 32
114 #if !ISPOWEROF2(MAX_HDR_READ)
115 #error MAX_HDR_READ is not a power of 2!
118 #define MAX_RX_DATASZ 2048
120 /* Maximum milliseconds to wait for F2 to come up */
121 #define DHD_WAIT_F2RDY 3000
123 /* Bump up limit on waiting for HT to account for first startup;
124 * if the image is doing a CRC calculation before programming the PMU
125 * for HT availability, it could take a couple hundred ms more, so
126 * max out at a 1 second (1000000us).
128 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
129 #undef PMU_MAX_TRANSITION_DLY
130 #define PMU_MAX_TRANSITION_DLY 1000000
133 /* Value for ChipClockCSR during initial setup */
134 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
135 SBSDIO_ALP_AVAIL_REQ)
136 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
138 /* Flags for SDH calls */
139 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
141 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
142 * bufpool was present for gspi bus.
144 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
145 PKTFREE(bus->dhd->osh, pkt, false);
146 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
147 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
151 /* Device console log buffer state */
152 typedef struct dhd_console {
153 uint count; /* Poll interval msec counter */
154 uint log_addr; /* Log struct address (fixed) */
155 hndrte_log_t log; /* Log struct (host copy) */
156 uint bufsize; /* Size of log buffer */
157 u8 *buf; /* Log buffer (host copy) */
158 uint last; /* Last buffer read index */
160 #endif /* DHD_DEBUG */
162 /* Private data for SDIO bus interaction */
163 typedef struct dhd_bus {
166 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
167 si_t *sih; /* Handle for SI calls */
168 char *vars; /* Variables (from CIS and/or other) */
169 uint varsz; /* Size of variables buffer */
170 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
172 sdpcmd_regs_t *regs; /* Registers for SDIO core */
173 uint sdpcmrev; /* SDIO core revision */
174 uint armrev; /* CPU core revision */
175 uint ramrev; /* SOCRAM core revision */
176 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
177 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
179 u32 bus; /* gSPI or SDIO bus */
180 u32 hostintmask; /* Copy of Host Interrupt Mask */
181 u32 intstatus; /* Intstatus bits (events) pending */
182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
183 bool fcstate; /* State of dongle flow-control */
185 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
186 char *fw_path; /* module_param: path to firmware image */
187 char *nv_path; /* module_param: path to nvram vars file */
188 const char *nvram_params; /* user specified nvram params. */
190 uint blocksize; /* Block size of SDIO transfers */
191 uint roundup; /* Max roundup limit */
193 struct pktq txq; /* Queue length used for flow-control */
194 u8 flowcontrol; /* per prio flow control bitmask */
195 u8 tx_seq; /* Transmit sequence number (next) */
196 u8 tx_max; /* Maximum transmit sequence allowed */
198 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
199 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
200 u16 nextlen; /* Next Read Len from last header */
201 u8 rx_seq; /* Receive sequence number (expected) */
202 bool rxskip; /* Skip receive (awaiting NAK ACK) */
204 void *glomd; /* Packet containing glomming descriptor */
205 void *glom; /* Packet chain for glommed superframe */
206 uint glomerr; /* Glom packet read errors */
208 u8 *rxbuf; /* Buffer for receiving control packets */
209 uint rxblen; /* Allocated length of rxbuf */
210 u8 *rxctl; /* Aligned pointer into rxbuf */
211 u8 *databuf; /* Buffer for receiving big glom packet */
212 u8 *dataptr; /* Aligned pointer into databuf */
213 uint rxlen; /* Length of valid data in buffer */
215 u8 sdpcm_ver; /* Bus protocol reported by dongle */
217 bool intr; /* Use interrupts */
218 bool poll; /* Use polling */
219 bool ipend; /* Device interrupt is pending */
220 bool intdis; /* Interrupts disabled by isr */
221 uint intrcount; /* Count of device interrupt callbacks */
222 uint lastintrs; /* Count as of last watchdog timer */
223 uint spurious; /* Count of spurious interrupts */
224 uint pollrate; /* Ticks between device polls */
225 uint polltick; /* Tick counter */
226 uint pollcnt; /* Count of active polls */
229 dhd_console_t console; /* Console output polling support */
230 uint console_addr; /* Console address from shared struct */
231 #endif /* DHD_DEBUG */
233 uint regfails; /* Count of R_REG/W_REG failures */
235 uint clkstate; /* State of sd and backplane clock(s) */
236 bool activity; /* Activity flag for clock down */
237 s32 idletime; /* Control for activity timeout */
238 s32 idlecount; /* Activity timeout counter */
239 s32 idleclock; /* How to set bus driver when idle */
240 s32 sd_divisor; /* Speed control to bus driver */
241 s32 sd_mode; /* Mode control to bus driver */
242 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
243 bool use_rxchain; /* If dhd should use PKT chains */
244 bool sleeping; /* Is SDIO bus sleeping? */
245 bool rxflow_mode; /* Rx flow control mode */
246 bool rxflow; /* Is rx flow control on */
247 uint prev_rxlim_hit; /* Is prev rx limit exceeded
248 (per dpc schedule) */
249 bool alp_only; /* Don't use HT clock (ALP only) */
250 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
254 /* external loopback */
258 /* pktgen configuration */
259 uint pktgen_freq; /* Ticks between bursts */
260 uint pktgen_count; /* Packets to send each burst */
261 uint pktgen_print; /* Bursts between count displays */
262 uint pktgen_total; /* Stop after this many */
263 uint pktgen_minlen; /* Minimum packet data len */
264 uint pktgen_maxlen; /* Maximum packet data len */
265 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
266 uint pktgen_stop; /* Number of tx failures causing stop */
268 /* active pktgen fields */
269 uint pktgen_tick; /* Tick counter for bursts */
270 uint pktgen_ptick; /* Burst counter for printing */
271 uint pktgen_sent; /* Number of test packets generated */
272 uint pktgen_rcvd; /* Number of test packets received */
273 uint pktgen_fail; /* Number of failed send attempts */
274 u16 pktgen_len; /* Length of next packet to send */
277 /* Some additional counters */
278 uint tx_sderrs; /* Count of tx attempts with sd errors */
279 uint fcqueued; /* Tx packets that got queued */
280 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
281 uint rx_toolong; /* Receive frames too long to receive */
282 uint rxc_errors; /* SDIO errors when reading control frames */
283 uint rx_hdrfail; /* SDIO errors on header reads */
284 uint rx_badhdr; /* Bad received headers (roosync?) */
285 uint rx_badseq; /* Mismatched rx sequence number */
286 uint fc_rcvd; /* Number of flow-control events received */
287 uint fc_xoff; /* Number which turned on flow-control */
288 uint fc_xon; /* Number which turned off flow-control */
289 uint rxglomfail; /* Failed deglom attempts */
290 uint rxglomframes; /* Number of glom frames (superframes) */
291 uint rxglompkts; /* Number of packets from glom frames */
292 uint f2rxhdrs; /* Number of header reads */
293 uint f2rxdata; /* Number of frame data reads */
294 uint f2txdata; /* Number of f2 frame writes */
295 uint f1regdata; /* Number of f1 register accesses */
299 bool ctrl_frame_stat;
305 #define CLK_PENDING 2 /* Not used yet */
308 #define DHD_NOPMU(dhd) (false)
311 static int qcount[NUMPRIO];
312 static int tx_packets[NUMPRIO];
313 #endif /* DHD_DEBUG */
315 /* Deferred transmit */
316 const uint dhd_deferred_tx = 1;
318 extern uint dhd_watchdog_ms;
319 extern void dhd_os_wd_timer(void *bus, uint wdtick);
326 /* override the RAM size if possible */
327 #define DONGLE_MIN_MEMSIZE (128 * 1024)
328 int dhd_dongle_memsize;
330 static bool dhd_doflow;
331 static bool dhd_alignctl;
335 static bool retrydata;
336 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
338 static const uint watermark = 8;
339 static const uint firstread = DHD_FIRSTREAD;
341 #define HDATLEN (firstread - (SDPCM_HDRLEN))
343 /* Retry count for register access failures */
344 static const uint retry_limit = 2;
346 /* Force even SD lengths (some host controllers mess up on odd bytes) */
347 static bool forcealign;
351 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
352 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
355 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
356 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
357 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
358 #define PKTALIGN(osh, p, len, align) \
361 datalign = (unsigned long)PKTDATA((p)); \
362 datalign = roundup(datalign, (align)) - datalign; \
363 ASSERT(datalign < (align)); \
364 ASSERT(PKTLEN((p)) >= ((len) + datalign)); \
366 PKTPULL((p), datalign); \
367 PKTSETLEN((p), (len)); \
370 /* Limit on rounding up frames */
371 static const uint max_roundup = 512;
373 /* Try doing readahead */
374 static bool dhd_readahead;
376 /* To check if there's window offered */
377 #define DATAOK(bus) \
378 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
379 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
381 /* Macros to get register read/write status */
382 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
383 #define R_SDREG(regvar, regaddr, retryvar) \
387 regvar = R_REG(bus->dhd->osh, regaddr); \
388 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
390 bus->regfails += (retryvar-1); \
391 if (retryvar > retry_limit) { \
392 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
393 __func__, __LINE__)); \
399 #define W_SDREG(regval, regaddr, retryvar) \
403 W_REG(bus->dhd->osh, regaddr, regval); \
404 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
406 bus->regfails += (retryvar-1); \
407 if (retryvar > retry_limit) \
408 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
409 __func__, __LINE__)); \
413 #define DHD_BUS SDIO_BUS
415 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
417 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
419 #define GSPI_PR55150_BAILOUT
422 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
423 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
427 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
428 static int dhdsdio_mem_dump(dhd_bus_t *bus);
429 #endif /* DHD_DEBUG */
430 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
432 static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
433 static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
434 static void dhdsdio_disconnect(void *ptr);
435 static bool dhdsdio_chipmatch(u16 chipid);
436 static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
437 void *regsva, u16 devid);
438 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
439 static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
440 static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
442 static uint process_nvram_vars(char *varbuf, uint len);
444 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
445 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
446 uint flags, u8 *buf, uint nbytes, void *pkt,
447 bcmsdh_cmplt_fn_t complete, void *handle);
448 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
449 uint flags, u8 *buf, uint nbytes, void *pkt,
450 bcmsdh_cmplt_fn_t complete, void *handle);
452 static bool dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh,
454 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
456 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
457 static int dhdsdio_download_nvram(struct dhd_bus *bus);
459 static int dhdsdio_download_code_array(struct dhd_bus *bus);
462 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
464 s32 min_size = DONGLE_MIN_MEMSIZE;
465 /* Restrict the memsize to user specified limit */
466 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
467 dhd_dongle_memsize, min_size));
468 if ((dhd_dongle_memsize > min_size) &&
469 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
470 bus->ramsize = dhd_dongle_memsize;
473 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
476 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
477 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
479 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
480 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
482 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
483 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
488 /* Turn backplane clock on or off */
489 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
492 u8 clkctl, clkreq, devctl;
495 DHD_TRACE(("%s: Enter\n", __func__));
497 #if defined(OOB_INTR_ONLY)
504 /* Request HT Avail */
506 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
508 if ((bus->sih->chip == BCM4329_CHIP_ID)
509 && (bus->sih->chiprev == 0))
510 clkreq |= SBSDIO_FORCE_ALP;
512 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
515 DHD_ERROR(("%s: HT Avail request error: %d\n",
520 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
521 && (bus->sih->buscorerev == 9))) {
523 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
526 /* Check current status */
528 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
531 DHD_ERROR(("%s: HT Avail read error: %d\n",
536 /* Go to pending and await interrupt if appropriate */
537 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
538 /* Allow only clock-available interrupt */
540 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
543 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
548 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
549 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
551 DHD_INFO(("CLKCTL: set PENDING\n"));
552 bus->clkstate = CLK_PENDING;
555 } else if (bus->clkstate == CLK_PENDING) {
556 /* Cancel CA-only interrupt filter */
558 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
560 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
561 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
565 /* Otherwise, wait here (polling) for HT Avail */
566 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
567 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
569 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
570 SBSDIO_FUNC1_CHIPCLKCSR,
572 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
573 PMU_MAX_TRANSITION_DLY);
576 DHD_ERROR(("%s: HT Avail request error: %d\n",
580 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
581 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
582 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
586 /* Mark clock available */
587 bus->clkstate = CLK_AVAIL;
588 DHD_INFO(("CLKCTL: turned ON\n"));
590 #if defined(DHD_DEBUG)
591 if (bus->alp_only == true) {
592 #if !defined(BCMLXSDMMC)
593 if (!SBSDIO_ALPONLY(clkctl)) {
594 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
597 #endif /* !defined(BCMLXSDMMC) */
599 if (SBSDIO_ALPONLY(clkctl)) {
600 DHD_ERROR(("%s: HT Clock should be on.\n",
604 #endif /* defined (DHD_DEBUG) */
606 bus->activity = true;
610 if (bus->clkstate == CLK_PENDING) {
611 /* Cancel CA-only interrupt filter */
613 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
615 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
616 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
620 bus->clkstate = CLK_SDONLY;
621 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
623 DHD_INFO(("CLKCTL: turned OFF\n"));
625 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
633 /* Change idle/active SD state */
634 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
639 DHD_TRACE(("%s: Enter\n", __func__));
642 if (bus->idleclock == DHD_IDLE_STOP) {
643 /* Turn on clock and restore mode */
645 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
646 &iovalue, sizeof(iovalue), true);
648 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
653 iovalue = bus->sd_mode;
654 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
655 &iovalue, sizeof(iovalue), true);
657 DHD_ERROR(("%s: error changing sd_mode: %d\n",
661 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
662 /* Restore clock speed */
663 iovalue = bus->sd_divisor;
664 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
665 &iovalue, sizeof(iovalue), true);
667 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
672 bus->clkstate = CLK_SDONLY;
674 /* Stop or slow the SD clock itself */
675 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
676 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
677 __func__, bus->sd_divisor, bus->sd_mode));
680 if (bus->idleclock == DHD_IDLE_STOP) {
682 /* Change to SD1 mode and turn off clock */
685 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
687 sizeof(iovalue), true);
689 DHD_ERROR(("%s: error changing sd_clock: %d\n",
696 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
697 &iovalue, sizeof(iovalue), true);
699 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
703 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
704 /* Set divisor to idle value */
705 iovalue = bus->idleclock;
706 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
707 &iovalue, sizeof(iovalue), true);
709 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
714 bus->clkstate = CLK_NONE;
720 /* Transition SD and backplane clock readiness */
721 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
724 uint oldstate = bus->clkstate;
725 #endif /* DHD_DEBUG */
727 DHD_TRACE(("%s: Enter\n", __func__));
729 /* Early exit if we're already there */
730 if (bus->clkstate == target) {
731 if (target == CLK_AVAIL) {
732 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
733 bus->activity = true;
740 /* Make sure SD clock is available */
741 if (bus->clkstate == CLK_NONE)
742 dhdsdio_sdclk(bus, true);
743 /* Now request HT Avail on the backplane */
744 dhdsdio_htclk(bus, true, pendok);
745 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
746 bus->activity = true;
750 /* Remove HT request, or bring up SD clock */
751 if (bus->clkstate == CLK_NONE)
752 dhdsdio_sdclk(bus, true);
753 else if (bus->clkstate == CLK_AVAIL)
754 dhdsdio_htclk(bus, false, false);
756 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
757 bus->clkstate, target));
758 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
762 /* Make sure to remove HT request */
763 if (bus->clkstate == CLK_AVAIL)
764 dhdsdio_htclk(bus, false, false);
765 /* Now remove the SD clock */
766 dhdsdio_sdclk(bus, false);
767 dhd_os_wd_timer(bus->dhd, 0);
771 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
772 #endif /* DHD_DEBUG */
777 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
779 bcmsdh_info_t *sdh = bus->sdh;
780 sdpcmd_regs_t *regs = bus->regs;
783 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
784 (sleep ? "SLEEP" : "WAKE"),
785 (bus->sleeping ? "SLEEP" : "WAKE")));
787 /* Done if we're already in the requested state */
788 if (sleep == bus->sleeping)
791 /* Going to sleep: set the alarm and turn off the lights... */
793 /* Don't sleep if something is pending */
794 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
797 /* Disable SDIO interrupts (no longer interested) */
798 bcmsdh_intr_disable(bus->sdh);
800 /* Make sure the controller has the bus up */
801 dhdsdio_clkctl(bus, CLK_AVAIL, false);
803 /* Tell device to start using OOB wakeup */
804 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
805 if (retries > retry_limit)
806 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
808 /* Turn off our contribution to the HT clock request */
809 dhdsdio_clkctl(bus, CLK_SDONLY, false);
811 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
812 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
814 /* Isolate the bus */
815 if (bus->sih->chip != BCM4329_CHIP_ID
816 && bus->sih->chip != BCM4319_CHIP_ID) {
817 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
818 SBSDIO_DEVCTL_PADS_ISO, NULL);
822 bus->sleeping = true;
825 /* Waking up: bus power up is ok, set local state */
827 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
830 /* Force pad isolation off if possible
831 (in case power never toggled) */
832 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
833 && (bus->sih->buscorerev >= 10))
834 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
837 /* Make sure the controller has the bus up */
838 dhdsdio_clkctl(bus, CLK_AVAIL, false);
840 /* Send misc interrupt to indicate OOB not needed */
841 W_SDREG(0, ®s->tosbmailboxdata, retries);
842 if (retries <= retry_limit)
843 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
845 if (retries > retry_limit)
846 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
848 /* Make sure we have SD bus access */
849 dhdsdio_clkctl(bus, CLK_SDONLY, false);
852 bus->sleeping = false;
854 /* Enable interrupts again */
855 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
857 bcmsdh_intr_enable(bus->sdh);
864 #if defined(OOB_INTR_ONLY)
865 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
868 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
870 sdpcmd_regs_t *regs = bus->regs;
873 dhdsdio_clkctl(bus, CLK_AVAIL, false);
874 if (enable == true) {
876 /* Tell device to start using OOB wakeup */
877 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
878 if (retries > retry_limit)
879 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
882 /* Send misc interrupt to indicate OOB not needed */
883 W_SDREG(0, ®s->tosbmailboxdata, retries);
884 if (retries <= retry_limit)
885 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
888 /* Turn off our contribution to the HT clock request */
889 dhdsdio_clkctl(bus, CLK_SDONLY, false);
890 #endif /* !defined(HW_OOB) */
892 #endif /* defined(OOB_INTR_ONLY) */
894 #define BUS_WAKE(bus) \
896 if ((bus)->sleeping) \
897 dhdsdio_bussleep((bus), false); \
900 /* Writes a HW/SW header into the packet and sends it. */
901 /* Assumes: (a) header space already there, (b) caller holds lock */
902 static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
914 DHD_TRACE(("%s: Enter\n", __func__));
919 if (bus->dhd->dongle_reset) {
924 frame = (u8 *) PKTDATA(pkt);
926 /* Add alignment padding, allocate new packet if needed */
927 pad = ((unsigned long)frame % DHD_SDALIGN);
929 if (PKTHEADROOM(pkt) < pad) {
930 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
931 __func__, (int)PKTHEADROOM(pkt), pad));
932 bus->dhd->tx_realloc++;
933 new = PKTGET(osh, (PKTLEN(pkt) + DHD_SDALIGN), true);
935 DHD_ERROR(("%s: couldn't allocate new %d-byte "
937 __func__, PKTLEN(pkt) + DHD_SDALIGN));
942 PKTALIGN(osh, new, PKTLEN(pkt), DHD_SDALIGN);
943 bcopy(PKTDATA(pkt), PKTDATA(new), PKTLEN(pkt));
945 PKTFREE(osh, pkt, true);
946 /* free the pkt if canned one is not used */
949 frame = (u8 *) PKTDATA(pkt);
950 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
954 frame = (u8 *) PKTDATA(pkt);
956 ASSERT((pad + SDPCM_HDRLEN) <= (int)PKTLEN(pkt));
957 bzero(frame, pad + SDPCM_HDRLEN);
960 ASSERT(pad < DHD_SDALIGN);
962 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
963 len = (u16) PKTLEN(pkt);
964 *(u16 *) frame = htol16(len);
965 *(((u16 *) frame) + 1) = htol16(~len);
967 /* Software tag: channel, sequence number, data offset */
969 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
971 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
972 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
973 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
976 tx_packets[PKTPRIO(pkt)]++;
977 if (DHD_BYTES_ON() &&
978 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
979 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
980 prhex("Tx Frame", frame, len);
981 } else if (DHD_HDRS_ON()) {
982 prhex("TxHdr", frame, min_t(u16, len, 16));
986 /* Raise len to next SDIO block to eliminate tail command */
987 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
988 u16 pad = bus->blocksize - (len % bus->blocksize);
989 if ((pad <= bus->roundup) && (pad < bus->blocksize))
991 if (pad <= PKTTAILROOM(pkt))
994 } else if (len % DHD_SDALIGN) {
995 len += DHD_SDALIGN - (len % DHD_SDALIGN);
998 /* Some controllers have trouble with odd bytes -- round to even */
999 if (forcealign && (len & (ALIGNMENT - 1))) {
1001 if (PKTTAILROOM(pkt))
1003 len = roundup(len, ALIGNMENT);
1006 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1013 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1014 F2SYNC, frame, len, pkt, NULL, NULL);
1016 ASSERT(ret != BCME_PENDING);
1019 /* On failure, abort the command
1020 and terminate the frame */
1021 DHD_INFO(("%s: sdio error %d, abort command and "
1022 "terminate frame.\n", __func__, ret));
1025 bcmsdh_abort(sdh, SDIO_FUNC_2);
1026 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1027 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1031 for (i = 0; i < 3; i++) {
1033 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_WFRAMEBCHI,
1036 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1037 SBSDIO_FUNC1_WFRAMEBCLO,
1039 bus->f1regdata += 2;
1040 if ((hi == 0) && (lo == 0))
1046 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1048 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1051 /* restore pkt buffer pointer before calling tx complete routine */
1052 PKTPULL(pkt, SDPCM_HDRLEN + pad);
1053 dhd_os_sdunlock(bus->dhd);
1054 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1055 dhd_os_sdlock(bus->dhd);
1058 PKTFREE(osh, pkt, true);
1063 int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1065 int ret = BCME_ERROR;
1069 DHD_TRACE(("%s: Enter\n", __func__));
1071 osh = bus->dhd->osh;
1072 datalen = PKTLEN(pkt);
1075 /* Push the test header if doing loopback */
1076 if (bus->ext_loop) {
1078 PKTPUSH(pkt, SDPCM_TEST_HDRLEN);
1079 data = PKTDATA(pkt);
1080 *data++ = SDPCM_TEST_ECHOREQ;
1081 *data++ = (u8) bus->loopid++;
1082 *data++ = (datalen >> 0);
1083 *data++ = (datalen >> 8);
1084 datalen += SDPCM_TEST_HDRLEN;
1088 /* Add space for the header */
1089 PKTPUSH(pkt, SDPCM_HDRLEN);
1090 ASSERT(IS_ALIGNED((unsigned long)PKTDATA(pkt), 2));
1092 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1094 /* Check for existing queue, current flow-control,
1095 pending event, or pending clock */
1096 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1097 || bus->dpc_sched || (!DATAOK(bus))
1098 || (bus->flowcontrol & NBITVAL(prec))
1099 || (bus->clkstate != CLK_AVAIL)) {
1100 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1101 pktq_len(&bus->txq)));
1104 /* Priority based enq */
1105 dhd_os_sdlock_txq(bus->dhd);
1106 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1107 PKTPULL(pkt, SDPCM_HDRLEN);
1108 dhd_txcomplete(bus->dhd, pkt, false);
1109 PKTFREE(osh, pkt, true);
1110 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1111 ret = BCME_NORESOURCE;
1115 dhd_os_sdunlock_txq(bus->dhd);
1117 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1118 dhd_txflowcontrol(bus->dhd, 0, ON);
1121 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1122 qcount[prec] = pktq_plen(&bus->txq, prec);
1124 /* Schedule DPC if needed to send queued packet(s) */
1125 if (dhd_deferred_tx && !bus->dpc_sched) {
1126 bus->dpc_sched = true;
1127 dhd_sched_dpc(bus->dhd);
1130 /* Lock: we're about to use shared data/code (and SDIO) */
1131 dhd_os_sdlock(bus->dhd);
1133 /* Otherwise, send it now */
1135 /* Make sure back plane ht clk is on, no pending allowed */
1136 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1139 DHD_TRACE(("%s: calling txpkt\n", __func__));
1140 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1142 ret = dhdsdio_txpkt(bus, pkt,
1143 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1144 SDPCM_DATA_CHANNEL), true);
1147 bus->dhd->tx_errors++;
1149 bus->dhd->dstats.tx_bytes += datalen;
1151 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1152 bus->activity = false;
1153 dhdsdio_clkctl(bus, CLK_NONE, true);
1156 dhd_os_sdunlock(bus->dhd);
1162 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1167 int ret = 0, prec_out;
1172 dhd_pub_t *dhd = bus->dhd;
1173 sdpcmd_regs_t *regs = bus->regs;
1175 DHD_TRACE(("%s: Enter\n", __func__));
1177 tx_prec_map = ~bus->flowcontrol;
1179 /* Send frames until the limit or some other event */
1180 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1181 dhd_os_sdlock_txq(bus->dhd);
1182 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1184 dhd_os_sdunlock_txq(bus->dhd);
1187 dhd_os_sdunlock_txq(bus->dhd);
1188 datalen = PKTLEN(pkt) - SDPCM_HDRLEN;
1191 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1193 ret = dhdsdio_txpkt(bus, pkt,
1194 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1195 SDPCM_DATA_CHANNEL), true);
1198 bus->dhd->tx_errors++;
1200 bus->dhd->dstats.tx_bytes += datalen;
1202 /* In poll mode, need to check for other events */
1203 if (!bus->intr && cnt) {
1204 /* Check device status, signal pending interrupt */
1205 R_SDREG(intstatus, ®s->intstatus, retries);
1207 if (bcmsdh_regfail(bus->sdh))
1209 if (intstatus & bus->hostintmask)
1214 /* Deflow-control stack if needed */
1215 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1216 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1217 dhd_txflowcontrol(dhd, 0, OFF);
1222 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1228 bcmsdh_info_t *sdh = bus->sdh;
1233 DHD_TRACE(("%s: Enter\n", __func__));
1235 if (bus->dhd->dongle_reset)
1238 /* Back the pointer to make a room for bus header */
1239 frame = msg - SDPCM_HDRLEN;
1240 len = (msglen += SDPCM_HDRLEN);
1242 /* Add alignment padding (optional for ctl frames) */
1244 doff = ((unsigned long)frame % DHD_SDALIGN);
1249 bzero(frame, doff + SDPCM_HDRLEN);
1251 ASSERT(doff < DHD_SDALIGN);
1253 doff += SDPCM_HDRLEN;
1255 /* Round send length to next SDIO block */
1256 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1257 u16 pad = bus->blocksize - (len % bus->blocksize);
1258 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1260 } else if (len % DHD_SDALIGN) {
1261 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1264 /* Satisfy length-alignment requirements */
1265 if (forcealign && (len & (ALIGNMENT - 1)))
1266 len = roundup(len, ALIGNMENT);
1268 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1270 /* Need to lock here to protect txseq and SDIO tx calls */
1271 dhd_os_sdlock(bus->dhd);
1275 /* Make sure backplane clock is on */
1276 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1278 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1279 *(u16 *) frame = htol16((u16) msglen);
1280 *(((u16 *) frame) + 1) = htol16(~msglen);
1282 /* Software tag: channel, sequence number, data offset */
1284 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1286 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1287 SDPCM_DOFFSET_MASK);
1288 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1289 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1292 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1293 __func__, bus->tx_max, bus->tx_seq));
1294 bus->ctrl_frame_stat = true;
1296 bus->ctrl_frame_buf = frame;
1297 bus->ctrl_frame_len = len;
1299 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1301 if (bus->ctrl_frame_stat == false) {
1302 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1305 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1312 if (DHD_BYTES_ON() && DHD_CTL_ON())
1313 prhex("Tx Frame", frame, len);
1314 else if (DHD_HDRS_ON())
1315 prhex("TxHdr", frame, min_t(u16, len, 16));
1319 bus->ctrl_frame_stat = false;
1321 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1322 SDIO_FUNC_2, F2SYNC, frame, len,
1325 ASSERT(ret != BCME_PENDING);
1328 /* On failure, abort the command and
1329 terminate the frame */
1330 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1334 bcmsdh_abort(sdh, SDIO_FUNC_2);
1336 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1337 SBSDIO_FUNC1_FRAMECTRL,
1341 for (i = 0; i < 3; i++) {
1343 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1344 SBSDIO_FUNC1_WFRAMEBCHI,
1346 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1347 SBSDIO_FUNC1_WFRAMEBCLO,
1349 bus->f1regdata += 2;
1350 if ((hi == 0) && (lo == 0))
1357 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1359 } while ((ret < 0) && retries++ < TXRETRIES);
1362 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1363 bus->activity = false;
1364 dhdsdio_clkctl(bus, CLK_NONE, true);
1367 dhd_os_sdunlock(bus->dhd);
1370 bus->dhd->tx_ctlerrs++;
1372 bus->dhd->tx_ctlpkts++;
1374 return ret ? -EIO : 0;
1377 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1383 DHD_TRACE(("%s: Enter\n", __func__));
1385 if (bus->dhd->dongle_reset)
1388 /* Wait until control frame is available */
1389 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1391 dhd_os_sdlock(bus->dhd);
1393 bcopy(bus->rxctl, msg, min(msglen, rxlen));
1395 dhd_os_sdunlock(bus->dhd);
1398 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1399 __func__, rxlen, msglen));
1400 } else if (timeleft == 0) {
1401 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1403 dhd_os_sdlock(bus->dhd);
1404 dhdsdio_checkdied(bus, NULL, 0);
1405 dhd_os_sdunlock(bus->dhd);
1406 #endif /* DHD_DEBUG */
1407 } else if (pending == true) {
1408 DHD_CTL(("%s: cancelled\n", __func__));
1409 return -ERESTARTSYS;
1411 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1413 dhd_os_sdlock(bus->dhd);
1414 dhdsdio_checkdied(bus, NULL, 0);
1415 dhd_os_sdunlock(bus->dhd);
1416 #endif /* DHD_DEBUG */
1420 bus->dhd->rx_ctlpkts++;
1422 bus->dhd->rx_ctlerrs++;
1424 return rxlen ? (int)rxlen : -ETIMEDOUT;
1463 const bcm_iovar_t dhdsdio_iovars[] = {
1464 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1465 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1466 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1467 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1468 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1469 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1470 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1471 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1472 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1473 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1474 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1475 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1476 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1477 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1478 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1479 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1481 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1483 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1485 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1487 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1489 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1491 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1493 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1495 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1498 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1500 #endif /* DHD_DEBUG */
1501 #endif /* DHD_DEBUG */
1503 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1505 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1513 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1518 bcm_bprintf(strbuf, "%s N/A", desc);
1521 q2 = (100 * (num - (q1 * div))) / div;
1522 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1526 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1528 dhd_bus_t *bus = dhdp->bus;
1530 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1532 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1533 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1535 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1536 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1537 bus->rxskip, bus->rxlen, bus->rx_seq);
1538 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1539 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1540 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1541 bus->pollrate, bus->pollcnt, bus->regfails);
1543 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1545 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1546 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1548 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1549 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1550 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1551 bus->fc_xoff, bus->fc_xon);
1552 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1553 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1554 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1555 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1556 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1558 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1559 (bus->f2rxhdrs + bus->f2rxdata));
1560 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1562 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1563 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1564 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1566 bcm_bprintf(strbuf, "\n");
1568 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1569 bus->dhd->rx_packets);
1570 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1572 bcm_bprintf(strbuf, "\n");
1574 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1576 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1578 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1579 (bus->f2txdata + bus->f1regdata));
1580 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1582 bcm_bprintf(strbuf, "\n");
1584 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1585 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1586 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1587 dhd_dump_pct(strbuf, ", pkts/f1sd",
1588 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1590 dhd_dump_pct(strbuf, ", pkts/sd",
1591 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1592 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1594 dhd_dump_pct(strbuf, ", pkts/int",
1595 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1597 bcm_bprintf(strbuf, "\n\n");
1601 if (bus->pktgen_count) {
1602 bcm_bprintf(strbuf, "pktgen config and count:\n");
1604 "freq %d count %d print %d total %d min %d len %d\n",
1605 bus->pktgen_freq, bus->pktgen_count,
1606 bus->pktgen_print, bus->pktgen_total,
1607 bus->pktgen_minlen, bus->pktgen_maxlen);
1608 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1609 bus->pktgen_sent, bus->pktgen_rcvd,
1614 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1616 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1617 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1619 #endif /* DHD_DEBUG */
1621 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1622 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1626 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1628 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1630 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1631 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1632 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1633 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1634 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1635 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1639 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1641 dhd_pktgen_t pktgen;
1643 pktgen.version = DHD_PKTGEN_VERSION;
1644 pktgen.freq = bus->pktgen_freq;
1645 pktgen.count = bus->pktgen_count;
1646 pktgen.print = bus->pktgen_print;
1647 pktgen.total = bus->pktgen_total;
1648 pktgen.minlen = bus->pktgen_minlen;
1649 pktgen.maxlen = bus->pktgen_maxlen;
1650 pktgen.numsent = bus->pktgen_sent;
1651 pktgen.numrcvd = bus->pktgen_rcvd;
1652 pktgen.numfail = bus->pktgen_fail;
1653 pktgen.mode = bus->pktgen_mode;
1654 pktgen.stop = bus->pktgen_stop;
1656 bcopy(&pktgen, arg, sizeof(pktgen));
1661 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1663 dhd_pktgen_t pktgen;
1664 uint oldcnt, oldmode;
1666 bcopy(arg, &pktgen, sizeof(pktgen));
1667 if (pktgen.version != DHD_PKTGEN_VERSION)
1670 oldcnt = bus->pktgen_count;
1671 oldmode = bus->pktgen_mode;
1673 bus->pktgen_freq = pktgen.freq;
1674 bus->pktgen_count = pktgen.count;
1675 bus->pktgen_print = pktgen.print;
1676 bus->pktgen_total = pktgen.total;
1677 bus->pktgen_minlen = pktgen.minlen;
1678 bus->pktgen_maxlen = pktgen.maxlen;
1679 bus->pktgen_mode = pktgen.mode;
1680 bus->pktgen_stop = pktgen.stop;
1682 bus->pktgen_tick = bus->pktgen_ptick = 0;
1683 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1684 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1686 /* Clear counts for a new pktgen (mode change, or was stopped) */
1687 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1688 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1695 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1702 /* Determine initial transfer parameters */
1703 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1704 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1705 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1709 /* Set the backplane window to include the start address */
1710 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1712 DHD_ERROR(("%s: window change failed\n", __func__));
1716 /* Do the transfer(s) */
1718 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1719 __func__, (write ? "write" : "read"), dsize,
1720 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1722 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1724 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1728 /* Adjust for next transfer (if any) */
1733 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1735 DHD_ERROR(("%s: window change failed\n",
1740 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1745 /* Return the window to backplane enumeration space for core access */
1746 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1747 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1748 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1755 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1760 /* Read last word in memory to determine address of
1761 sdpcm_shared structure */
1762 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1766 addr = ltoh32(addr);
1768 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1771 * Check if addr is valid.
1772 * NVRAM length at the end of memory should have been overwritten.
1774 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1775 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1780 /* Read hndrte_shared structure */
1781 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1782 sizeof(sdpcm_shared_t));
1787 sh->flags = ltoh32(sh->flags);
1788 sh->trap_addr = ltoh32(sh->trap_addr);
1789 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1790 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1791 sh->assert_line = ltoh32(sh->assert_line);
1792 sh->console_addr = ltoh32(sh->console_addr);
1793 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1795 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1796 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1797 "is different than sdpcm_shared version %d in dongle\n",
1798 __func__, SDPCM_SHARED_VERSION,
1799 sh->flags & SDPCM_SHARED_VERSION_MASK));
1806 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1810 char *mbuffer = NULL;
1811 uint maxstrlen = 256;
1814 sdpcm_shared_t sdpcm_shared;
1815 struct bcmstrbuf strbuf;
1817 DHD_TRACE(("%s: Enter\n", __func__));
1821 * Called after a rx ctrl timeout. "data" is NULL.
1822 * allocate memory to trace the trap or assert.
1825 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1826 if (mbuffer == NULL) {
1827 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1829 bcmerror = BCME_NOMEM;
1834 str = kmalloc(maxstrlen, GFP_ATOMIC);
1836 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1837 bcmerror = BCME_NOMEM;
1841 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1845 bcm_binit(&strbuf, data, size);
1847 bcm_bprintf(&strbuf,
1848 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1849 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1851 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1852 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1853 * (Avoids conflict with real asserts for programmatic
1854 * parsing of output.)
1856 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1859 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1861 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1862 * (Avoids conflict with real asserts for programmatic
1863 * parsing of output.)
1865 bcm_bprintf(&strbuf, "No trap%s in dongle",
1866 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1869 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1870 /* Download assert */
1871 bcm_bprintf(&strbuf, "Dongle assert");
1872 if (sdpcm_shared.assert_exp_addr != 0) {
1874 bcmerror = dhdsdio_membytes(bus, false,
1875 sdpcm_shared.assert_exp_addr,
1876 (u8 *) str, maxstrlen);
1880 str[maxstrlen - 1] = '\0';
1881 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1884 if (sdpcm_shared.assert_file_addr != 0) {
1886 bcmerror = dhdsdio_membytes(bus, false,
1887 sdpcm_shared.assert_file_addr,
1888 (u8 *) str, maxstrlen);
1892 str[maxstrlen - 1] = '\0';
1893 bcm_bprintf(&strbuf, " file \"%s\"", str);
1896 bcm_bprintf(&strbuf, " line %d ",
1897 sdpcm_shared.assert_line);
1900 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1901 bcmerror = dhdsdio_membytes(bus, false,
1902 sdpcm_shared.trap_addr, (u8 *)&tr,
1907 bcm_bprintf(&strbuf,
1908 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1909 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1910 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1911 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1912 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1913 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1918 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1919 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1922 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1923 /* Mem dump to a file on device */
1924 dhdsdio_mem_dump(bus);
1926 #endif /* DHD_DEBUG */
1937 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1940 int size; /* Full mem size */
1941 int start = 0; /* Start address */
1942 int read_size = 0; /* Read size of each iteration */
1943 u8 *buf = NULL, *databuf = NULL;
1945 /* Get full mem size */
1946 size = bus->ramsize;
1947 buf = kmalloc(size, GFP_ATOMIC);
1949 printf("%s: Out of memory (%d bytes)\n", __func__, size);
1953 /* Read mem content */
1954 printf("Dump dongle memory");
1957 read_size = min(MEMBLOCK, size);
1958 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1960 printf("%s: Error membytes %d\n", __func__, ret);
1967 /* Decrement size and increment start address */
1970 databuf += read_size;
1974 /* free buf before return !!! */
1975 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1976 printf("%s: Error writing to files\n", __func__);
1980 /* buf free handled in write_to_file, not here */
1984 #define CONSOLE_LINE_MAX 192
1986 static int dhdsdio_readconsole(dhd_bus_t *bus)
1988 dhd_console_t *c = &bus->console;
1989 u8 line[CONSOLE_LINE_MAX], ch;
1993 /* Don't do anything until FWREADY updates console address */
1994 if (bus->console_addr == 0)
1997 /* Read console log struct */
1998 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
1999 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2004 /* Allocate console buffer (one time only) */
2005 if (c->buf == NULL) {
2006 c->bufsize = ltoh32(c->log.buf_size);
2007 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2012 idx = ltoh32(c->log.idx);
2014 /* Protect against corrupt value */
2015 if (idx > c->bufsize)
2018 /* Skip reading the console buffer if the index pointer
2023 /* Read the console buffer */
2024 addr = ltoh32(c->log.buf);
2025 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2029 while (c->last != idx) {
2030 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2031 if (c->last == idx) {
2032 /* This would output a partial line.
2034 * the buffer pointer and output this
2035 * line next time around.
2040 c->last = c->bufsize - n;
2043 ch = c->buf[c->last];
2044 c->last = (c->last + 1) % c->bufsize;
2051 if (line[n - 1] == '\r')
2054 printf("CONSOLE: %s\n", line);
2061 #endif /* DHD_DEBUG */
2063 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2065 int bcmerror = BCME_OK;
2067 DHD_TRACE(("%s: Enter\n", __func__));
2069 /* Basic sanity checks */
2071 bcmerror = BCME_NOTDOWN;
2075 bcmerror = BCME_BUFTOOSHORT;
2079 /* Free the old ones and replace with passed variables */
2083 bus->vars = kmalloc(len, GFP_ATOMIC);
2084 bus->varsz = bus->vars ? len : 0;
2085 if (bus->vars == NULL) {
2086 bcmerror = BCME_NOMEM;
2090 /* Copy the passed variables, which should include the
2091 terminating double-null */
2092 bcopy(arg, bus->vars, bus->varsz);
2098 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2099 const char *name, void *params, int plen, void *arg, int len,
2106 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2107 "len %d val_size %d\n",
2108 __func__, actionid, name, params, plen, arg, len, val_size));
2110 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2114 if (plen >= (int)sizeof(int_val))
2115 bcopy(params, &int_val, sizeof(int_val));
2117 bool_val = (int_val != 0) ? true : false;
2119 /* Some ioctls use the bus */
2120 dhd_os_sdlock(bus->dhd);
2122 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2123 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2124 actionid == IOV_GVAL(IOV_DEVRESET))) {
2125 bcmerror = BCME_NOTREADY;
2129 /* Handle sleep stuff before any clock mucking */
2130 if (vi->varid == IOV_SLEEP) {
2131 if (IOV_ISSET(actionid)) {
2132 bcmerror = dhdsdio_bussleep(bus, bool_val);
2134 int_val = (s32) bus->sleeping;
2135 bcopy(&int_val, arg, val_size);
2140 /* Request clock to allow SDIO accesses */
2141 if (!bus->dhd->dongle_reset) {
2143 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2147 case IOV_GVAL(IOV_INTR):
2148 int_val = (s32) bus->intr;
2149 bcopy(&int_val, arg, val_size);
2152 case IOV_SVAL(IOV_INTR):
2153 bus->intr = bool_val;
2154 bus->intdis = false;
2157 DHD_INTR(("%s: enable SDIO device interrupts\n",
2159 bcmsdh_intr_enable(bus->sdh);
2161 DHD_INTR(("%s: disable SDIO interrupts\n",
2163 bcmsdh_intr_disable(bus->sdh);
2168 case IOV_GVAL(IOV_POLLRATE):
2169 int_val = (s32) bus->pollrate;
2170 bcopy(&int_val, arg, val_size);
2173 case IOV_SVAL(IOV_POLLRATE):
2174 bus->pollrate = (uint) int_val;
2175 bus->poll = (bus->pollrate != 0);
2178 case IOV_GVAL(IOV_IDLETIME):
2179 int_val = bus->idletime;
2180 bcopy(&int_val, arg, val_size);
2183 case IOV_SVAL(IOV_IDLETIME):
2184 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2185 bcmerror = BCME_BADARG;
2187 bus->idletime = int_val;
2190 case IOV_GVAL(IOV_IDLECLOCK):
2191 int_val = (s32) bus->idleclock;
2192 bcopy(&int_val, arg, val_size);
2195 case IOV_SVAL(IOV_IDLECLOCK):
2196 bus->idleclock = int_val;
2199 case IOV_GVAL(IOV_SD1IDLE):
2200 int_val = (s32) sd1idle;
2201 bcopy(&int_val, arg, val_size);
2204 case IOV_SVAL(IOV_SD1IDLE):
2208 case IOV_SVAL(IOV_MEMBYTES):
2209 case IOV_GVAL(IOV_MEMBYTES):
2215 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2217 ASSERT(plen >= 2 * sizeof(int));
2219 address = (u32) int_val;
2220 bcopy((char *)params + sizeof(int_val), &int_val,
2222 size = (uint) int_val;
2224 /* Do some validation */
2225 dsize = set ? plen - (2 * sizeof(int)) : len;
2227 DHD_ERROR(("%s: error on %s membytes, addr "
2228 "0x%08x size %d dsize %d\n",
2229 __func__, (set ? "set" : "get"),
2230 address, size, dsize));
2231 bcmerror = BCME_BADARG;
2235 DHD_INFO(("%s: Request to %s %d bytes at address "
2237 __func__, (set ? "write" : "read"), size, address));
2239 /* If we know about SOCRAM, check for a fit */
2240 if ((bus->orig_ramsize) &&
2241 ((address > bus->orig_ramsize)
2242 || (address + size > bus->orig_ramsize))) {
2243 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2244 "bytes at 0x%08x\n",
2245 __func__, bus->orig_ramsize, size, address));
2246 bcmerror = BCME_BADARG;
2250 /* Generate the actual data pointer */
2252 set ? (u8 *) params +
2253 2 * sizeof(int) : (u8 *) arg;
2255 /* Call to do the transfer */
2257 dhdsdio_membytes(bus, set, address, data, size);
2262 case IOV_GVAL(IOV_MEMSIZE):
2263 int_val = (s32) bus->ramsize;
2264 bcopy(&int_val, arg, val_size);
2267 case IOV_GVAL(IOV_SDIOD_DRIVE):
2268 int_val = (s32) dhd_sdiod_drive_strength;
2269 bcopy(&int_val, arg, val_size);
2272 case IOV_SVAL(IOV_SDIOD_DRIVE):
2273 dhd_sdiod_drive_strength = int_val;
2274 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
2275 dhd_sdiod_drive_strength);
2278 case IOV_SVAL(IOV_DOWNLOAD):
2279 bcmerror = dhdsdio_download_state(bus, bool_val);
2282 case IOV_SVAL(IOV_VARS):
2283 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2286 case IOV_GVAL(IOV_READAHEAD):
2287 int_val = (s32) dhd_readahead;
2288 bcopy(&int_val, arg, val_size);
2291 case IOV_SVAL(IOV_READAHEAD):
2292 if (bool_val && !dhd_readahead)
2294 dhd_readahead = bool_val;
2297 case IOV_GVAL(IOV_SDRXCHAIN):
2298 int_val = (s32) bus->use_rxchain;
2299 bcopy(&int_val, arg, val_size);
2302 case IOV_SVAL(IOV_SDRXCHAIN):
2303 if (bool_val && !bus->sd_rxchain)
2304 bcmerror = BCME_UNSUPPORTED;
2306 bus->use_rxchain = bool_val;
2308 case IOV_GVAL(IOV_ALIGNCTL):
2309 int_val = (s32) dhd_alignctl;
2310 bcopy(&int_val, arg, val_size);
2313 case IOV_SVAL(IOV_ALIGNCTL):
2314 dhd_alignctl = bool_val;
2317 case IOV_GVAL(IOV_SDALIGN):
2318 int_val = DHD_SDALIGN;
2319 bcopy(&int_val, arg, val_size);
2323 case IOV_GVAL(IOV_VARS):
2324 if (bus->varsz < (uint) len)
2325 bcopy(bus->vars, arg, bus->varsz);
2327 bcmerror = BCME_BUFTOOSHORT;
2329 #endif /* DHD_DEBUG */
2332 case IOV_GVAL(IOV_SDREG):
2337 sd_ptr = (sdreg_t *) params;
2339 addr = (unsigned long)bus->regs + sd_ptr->offset;
2340 size = sd_ptr->func;
2341 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2342 if (bcmsdh_regfail(bus->sdh))
2343 bcmerror = BCME_SDIO_ERROR;
2344 bcopy(&int_val, arg, sizeof(s32));
2348 case IOV_SVAL(IOV_SDREG):
2353 sd_ptr = (sdreg_t *) params;
2355 addr = (unsigned long)bus->regs + sd_ptr->offset;
2356 size = sd_ptr->func;
2357 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2358 if (bcmsdh_regfail(bus->sdh))
2359 bcmerror = BCME_SDIO_ERROR;
2363 /* Same as above, but offset is not backplane
2365 case IOV_GVAL(IOV_SBREG):
2370 bcopy(params, &sdreg, sizeof(sdreg));
2372 addr = SI_ENUM_BASE + sdreg.offset;
2374 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2375 if (bcmsdh_regfail(bus->sdh))
2376 bcmerror = BCME_SDIO_ERROR;
2377 bcopy(&int_val, arg, sizeof(s32));
2381 case IOV_SVAL(IOV_SBREG):
2386 bcopy(params, &sdreg, sizeof(sdreg));
2388 addr = SI_ENUM_BASE + sdreg.offset;
2390 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2391 if (bcmsdh_regfail(bus->sdh))
2392 bcmerror = BCME_SDIO_ERROR;
2396 case IOV_GVAL(IOV_SDCIS):
2400 strcat(arg, "\nFunc 0\n");
2401 bcmsdh_cis_read(bus->sdh, 0x10,
2402 (u8 *) arg + strlen(arg),
2403 SBSDIO_CIS_SIZE_LIMIT);
2404 strcat(arg, "\nFunc 1\n");
2405 bcmsdh_cis_read(bus->sdh, 0x11,
2406 (u8 *) arg + strlen(arg),
2407 SBSDIO_CIS_SIZE_LIMIT);
2408 strcat(arg, "\nFunc 2\n");
2409 bcmsdh_cis_read(bus->sdh, 0x12,
2410 (u8 *) arg + strlen(arg),
2411 SBSDIO_CIS_SIZE_LIMIT);
2415 case IOV_GVAL(IOV_FORCEEVEN):
2416 int_val = (s32) forcealign;
2417 bcopy(&int_val, arg, val_size);
2420 case IOV_SVAL(IOV_FORCEEVEN):
2421 forcealign = bool_val;
2424 case IOV_GVAL(IOV_TXBOUND):
2425 int_val = (s32) dhd_txbound;
2426 bcopy(&int_val, arg, val_size);
2429 case IOV_SVAL(IOV_TXBOUND):
2430 dhd_txbound = (uint) int_val;
2433 case IOV_GVAL(IOV_RXBOUND):
2434 int_val = (s32) dhd_rxbound;
2435 bcopy(&int_val, arg, val_size);
2438 case IOV_SVAL(IOV_RXBOUND):
2439 dhd_rxbound = (uint) int_val;
2442 case IOV_GVAL(IOV_TXMINMAX):
2443 int_val = (s32) dhd_txminmax;
2444 bcopy(&int_val, arg, val_size);
2447 case IOV_SVAL(IOV_TXMINMAX):
2448 dhd_txminmax = (uint) int_val;
2450 #endif /* DHD_DEBUG */
2453 case IOV_GVAL(IOV_EXTLOOP):
2454 int_val = (s32) bus->ext_loop;
2455 bcopy(&int_val, arg, val_size);
2458 case IOV_SVAL(IOV_EXTLOOP):
2459 bus->ext_loop = bool_val;
2462 case IOV_GVAL(IOV_PKTGEN):
2463 bcmerror = dhdsdio_pktgen_get(bus, arg);
2466 case IOV_SVAL(IOV_PKTGEN):
2467 bcmerror = dhdsdio_pktgen_set(bus, arg);
2471 case IOV_SVAL(IOV_DEVRESET):
2472 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2474 __func__, bool_val, bus->dhd->dongle_reset,
2475 bus->dhd->busstate));
2477 ASSERT(bus->dhd->osh);
2478 /* ASSERT(bus->cl_devid); */
2480 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2484 case IOV_GVAL(IOV_DEVRESET):
2485 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2487 /* Get its status */
2488 int_val = (bool) bus->dhd->dongle_reset;
2489 bcopy(&int_val, arg, val_size);
2494 bcmerror = BCME_UNSUPPORTED;
2499 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2500 bus->activity = false;
2501 dhdsdio_clkctl(bus, CLK_NONE, true);
2504 dhd_os_sdunlock(bus->dhd);
2506 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2507 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2512 static int dhdsdio_write_vars(dhd_bus_t *bus)
2520 char *nvram_ularray;
2521 #endif /* DHD_DEBUG */
2523 /* Even if there are no vars are to be written, we still
2524 need to set the ramsize. */
2525 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2526 varaddr = (bus->ramsize - 4) - varsize;
2529 vbuffer = kmalloc(varsize, GFP_ATOMIC);
2533 bzero(vbuffer, varsize);
2534 bcopy(bus->vars, vbuffer, bus->varsz);
2536 /* Write the vars list */
2538 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2540 /* Verify NVRAM bytes */
2541 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2542 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2546 /* Upload image to verify downloaded contents. */
2547 memset(nvram_ularray, 0xaa, varsize);
2549 /* Read the vars list to temp buffer for comparison */
2551 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2554 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2555 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2557 /* Compare the org NVRAM with the one read from RAM */
2558 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2559 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2562 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2565 kfree(nvram_ularray);
2566 #endif /* DHD_DEBUG */
2571 /* adjust to the user specified RAM */
2572 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2573 bus->orig_ramsize, bus->ramsize));
2574 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2575 varsize = ((bus->orig_ramsize - 4) - varaddr);
2578 * Determine the length token:
2579 * Varsize, converted to words, in lower 16-bits, checksum
2585 varsizew = varsize / 4;
2586 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2587 varsizew = htol32(varsizew);
2590 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2593 /* Write the length token to the last word */
2594 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2595 (u8 *)&varsizew, 4);
2600 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2605 /* To enter download state, disable ARM and reset SOCRAM.
2606 * To exit download state, simply reset ARM (default is RAM boot).
2610 bus->alp_only = true;
2612 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2613 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2614 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2615 bcmerror = BCME_ERROR;
2619 si_core_disable(bus->sih, 0);
2620 if (bcmsdh_regfail(bus->sdh)) {
2621 bcmerror = BCME_SDIO_ERROR;
2625 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2626 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2628 bcmerror = BCME_ERROR;
2632 si_core_reset(bus->sih, 0, 0);
2633 if (bcmsdh_regfail(bus->sdh)) {
2634 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2636 bcmerror = BCME_SDIO_ERROR;
2640 /* Clear the top bit of memory */
2643 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2647 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2648 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2650 bcmerror = BCME_ERROR;
2654 if (!si_iscoreup(bus->sih)) {
2655 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2657 bcmerror = BCME_ERROR;
2661 bcmerror = dhdsdio_write_vars(bus);
2663 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2667 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2668 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2669 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2671 bcmerror = BCME_ERROR;
2674 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2676 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2677 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2678 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2679 bcmerror = BCME_ERROR;
2683 si_core_reset(bus->sih, 0, 0);
2684 if (bcmsdh_regfail(bus->sdh)) {
2685 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2687 bcmerror = BCME_SDIO_ERROR;
2691 /* Allow HT Clock now that the ARM is running. */
2692 bus->alp_only = false;
2694 bus->dhd->busstate = DHD_BUS_LOAD;
2698 /* Always return to SDIOD core */
2699 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2700 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2706 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2707 void *params, int plen, void *arg, int len, bool set)
2709 dhd_bus_t *bus = dhdp->bus;
2710 const bcm_iovar_t *vi = NULL;
2715 DHD_TRACE(("%s: Enter\n", __func__));
2720 /* Get MUST have return space */
2721 ASSERT(set || (arg && len));
2723 /* Set does NOT take qualifiers */
2724 ASSERT(!set || (!params && !plen));
2726 /* Look up var locally; if not found pass to host driver */
2727 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2729 dhd_os_sdlock(bus->dhd);
2733 /* Turn on clock in case SD command needs backplane */
2734 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2737 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2740 /* Check for bus configuration changes of interest */
2742 /* If it was divisor change, read the new one */
2743 if (set && strcmp(name, "sd_divisor") == 0) {
2744 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2745 &bus->sd_divisor, sizeof(s32),
2746 false) != BCME_OK) {
2747 bus->sd_divisor = -1;
2748 DHD_ERROR(("%s: fail on %s get\n", __func__,
2751 DHD_INFO(("%s: noted %s update, value now %d\n",
2752 __func__, name, bus->sd_divisor));
2755 /* If it was a mode change, read the new one */
2756 if (set && strcmp(name, "sd_mode") == 0) {
2757 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2758 &bus->sd_mode, sizeof(s32),
2759 false) != BCME_OK) {
2761 DHD_ERROR(("%s: fail on %s get\n", __func__,
2764 DHD_INFO(("%s: noted %s update, value now %d\n",
2765 __func__, name, bus->sd_mode));
2768 /* Similar check for blocksize change */
2769 if (set && strcmp(name, "sd_blocksize") == 0) {
2772 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2773 &bus->blocksize, sizeof(s32),
2774 false) != BCME_OK) {
2776 DHD_ERROR(("%s: fail on %s get\n", __func__,
2779 DHD_INFO(("%s: noted %s update, value now %d\n",
2780 __func__, "sd_blocksize",
2784 bus->roundup = min(max_roundup, bus->blocksize);
2786 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2787 bus->activity = false;
2788 dhdsdio_clkctl(bus, CLK_NONE, true);
2791 dhd_os_sdunlock(bus->dhd);
2795 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2796 name, (set ? "set" : "get"), len, plen));
2798 /* set up 'params' pointer in case this is a set command so that
2799 * the convenience int and bool code can be common to set and get
2801 if (params == NULL) {
2806 if (vi->type == IOVT_VOID)
2808 else if (vi->type == IOVT_BUFFER)
2811 /* all other types are integer sized */
2812 val_size = sizeof(int);
2814 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2816 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2823 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2825 osl_t *osh = bus->dhd->osh;
2826 u32 local_hostintmask;
2831 DHD_TRACE(("%s: Enter\n", __func__));
2834 dhd_os_sdlock(bus->dhd);
2838 /* Enable clock for device interrupts */
2839 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2841 /* Disable and clear interrupts at the chip level also */
2842 W_SDREG(0, &bus->regs->hostintmask, retries);
2843 local_hostintmask = bus->hostintmask;
2844 bus->hostintmask = 0;
2846 /* Change our idea of bus state */
2847 bus->dhd->busstate = DHD_BUS_DOWN;
2849 /* Force clocks on backplane to be sure F2 interrupt propagates */
2851 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2854 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2855 (saveclk | SBSDIO_FORCE_HT), &err);
2858 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2862 /* Turn off the bus (F2), free any pending packets */
2863 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2864 bcmsdh_intr_disable(bus->sdh);
2865 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2866 SDIO_FUNC_ENABLE_1, NULL);
2868 /* Clear any pending interrupts now that F2 is disabled */
2869 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2871 /* Turn off the backplane clock (only) */
2872 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2874 /* Clear the data packet queues */
2875 pktq_flush(osh, &bus->txq, true);
2877 /* Clear any held glomming stuff */
2879 PKTFREE(osh, bus->glomd, false);
2882 PKTFREE(osh, bus->glom, false);
2884 bus->glom = bus->glomd = NULL;
2886 /* Clear rx control and wake any waiters */
2888 dhd_os_ioctl_resp_wake(bus->dhd);
2890 /* Reset some F2 state stuff */
2891 bus->rxskip = false;
2892 bus->tx_seq = bus->rx_seq = 0;
2895 dhd_os_sdunlock(bus->dhd);
2898 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2900 dhd_bus_t *bus = dhdp->bus;
2907 DHD_TRACE(("%s: Enter\n", __func__));
2914 dhd_os_sdlock(bus->dhd);
2916 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2917 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2918 if (bus->clkstate != CLK_AVAIL)
2921 /* Force clocks on backplane to be sure F2 interrupt propagates */
2923 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2926 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2927 (saveclk | SBSDIO_FORCE_HT), &err);
2930 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2935 /* Enable function 2 (frame transfers) */
2936 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2937 &bus->regs->tosbmailboxdata, retries);
2938 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2940 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2942 /* Give the dongle some time to do its thing and set IOR2 */
2943 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2946 while (ready != enable && !dhd_timeout_expired(&tmo))
2948 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2951 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2952 __func__, enable, ready, tmo.elapsed));
2954 /* If F2 successfully enabled, set core and enable interrupts */
2955 if (ready == enable) {
2956 /* Make sure we're talking to the core. */
2957 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2959 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2961 /* Set up the interrupt mask and enable interrupts */
2962 bus->hostintmask = HOSTINTMASK;
2963 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2965 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2966 (u8) watermark, &err);
2968 /* Set bus state according to enable result */
2969 dhdp->busstate = DHD_BUS_DATA;
2971 /* bcmsdh_intr_unmask(bus->sdh); */
2973 bus->intdis = false;
2975 DHD_INTR(("%s: enable SDIO device interrupts\n",
2977 bcmsdh_intr_enable(bus->sdh);
2979 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2980 bcmsdh_intr_disable(bus->sdh);
2986 /* Disable F2 again */
2987 enable = SDIO_FUNC_ENABLE_1;
2988 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2992 /* Restore previous clock setting */
2993 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2996 /* If we didn't come up, turn off backplane clock */
2997 if (dhdp->busstate != DHD_BUS_DATA)
2998 dhdsdio_clkctl(bus, CLK_NONE, false);
3002 dhd_os_sdunlock(bus->dhd);
3007 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3009 bcmsdh_info_t *sdh = bus->sdh;
3010 sdpcmd_regs_t *regs = bus->regs;
3016 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3017 (abort ? "abort command, " : ""),
3018 (rtx ? ", send NAK" : "")));
3021 bcmsdh_abort(sdh, SDIO_FUNC_2);
3023 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3027 /* Wait until the packet has been flushed (device/FIFO stable) */
3028 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3029 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3031 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3033 bus->f1regdata += 2;
3035 if ((hi == 0) && (lo == 0))
3038 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3039 DHD_ERROR(("%s: count growing: last 0x%04x now "
3041 __func__, lastrbc, ((hi << 8) + lo)));
3043 lastrbc = (hi << 8) + lo;
3047 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3048 __func__, lastrbc));
3050 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3051 (0xffff - retries)));
3056 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3058 if (retries <= retry_limit)
3062 /* Clear partial in any case */
3065 /* If we can't reach the device, signal failure */
3066 if (err || bcmsdh_regfail(sdh))
3067 bus->dhd->busstate = DHD_BUS_DOWN;
3071 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3073 bcmsdh_info_t *sdh = bus->sdh;
3078 DHD_TRACE(("%s: Enter\n", __func__));
3080 /* Control data already received in aligned rxctl */
3081 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3085 /* Set rxctl for frame (w/optional alignment) */
3086 bus->rxctl = bus->rxbuf;
3088 bus->rxctl += firstread;
3089 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3091 bus->rxctl += (DHD_SDALIGN - pad);
3092 bus->rxctl -= firstread;
3094 ASSERT(bus->rxctl >= bus->rxbuf);
3096 /* Copy the already-read portion over */
3097 bcopy(hdr, bus->rxctl, firstread);
3098 if (len <= firstread)
3101 /* Copy the full data pkt in gSPI case and process ioctl. */
3102 if (bus->bus == SPI_BUS) {
3103 bcopy(hdr, bus->rxctl, len);
3107 /* Raise rdlen to next SDIO block to avoid tail command */
3108 rdlen = len - firstread;
3109 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3110 pad = bus->blocksize - (rdlen % bus->blocksize);
3111 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3112 ((len + pad) < bus->dhd->maxctl))
3114 } else if (rdlen % DHD_SDALIGN) {
3115 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3118 /* Satisfy length-alignment requirements */
3119 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3120 rdlen = roundup(rdlen, ALIGNMENT);
3122 /* Drop if the read is too big or it exceeds our maximum */
3123 if ((rdlen + firstread) > bus->dhd->maxctl) {
3124 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3125 __func__, rdlen, bus->dhd->maxctl));
3126 bus->dhd->rx_errors++;
3127 dhdsdio_rxfail(bus, false, false);
3131 if ((len - doff) > bus->dhd->maxctl) {
3132 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3134 __func__, len, (len - doff), bus->dhd->maxctl));
3135 bus->dhd->rx_errors++;
3137 dhdsdio_rxfail(bus, false, false);
3141 /* Read remainder of frame body into the rxctl buffer */
3143 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3144 (bus->rxctl + firstread), rdlen, NULL, NULL,
3147 ASSERT(sdret != BCME_PENDING);
3149 /* Control frame failures need retransmission */
3151 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3152 __func__, rdlen, sdret));
3153 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3154 dhdsdio_rxfail(bus, true, true);
3161 if (DHD_BYTES_ON() && DHD_CTL_ON())
3162 prhex("RxCtrl", bus->rxctl, len);
3165 /* Point to valid data and indicate its length */
3167 bus->rxlen = len - doff;
3170 /* Awake any waiters */
3171 dhd_os_ioctl_resp_wake(bus->dhd);
3174 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3180 void *pfirst, *plast, *pnext, *save_pfirst;
3181 osl_t *osh = bus->dhd->osh;
3184 u8 chan, seq, doff, sfdoff;
3188 bool usechain = bus->use_rxchain;
3190 /* If packets, issue read(s) and send up packet chain */
3191 /* Return sequence numbers consumed? */
3193 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3196 /* If there's a descriptor, generate the packet chain */
3198 dhd_os_sdlock_rxq(bus->dhd);
3200 pfirst = plast = pnext = NULL;
3201 dlen = (u16) PKTLEN(bus->glomd);
3202 dptr = PKTDATA(bus->glomd);
3203 if (!dlen || (dlen & 1)) {
3204 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3209 for (totlen = num = 0; dlen; num++) {
3210 /* Get (and move past) next length */
3211 sublen = ltoh16_ua(dptr);
3212 dlen -= sizeof(u16);
3213 dptr += sizeof(u16);
3214 if ((sublen < SDPCM_HDRLEN) ||
3215 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3216 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3217 __func__, num, sublen));
3221 if (sublen % DHD_SDALIGN) {
3222 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3223 __func__, sublen, DHD_SDALIGN));
3228 /* For last frame, adjust read len so total
3229 is a block multiple */
3232 (roundup(totlen, bus->blocksize) - totlen);
3233 totlen = roundup(totlen, bus->blocksize);
3236 /* Allocate/chain packet for next subframe */
3237 pnext = PKTGET(osh, sublen + DHD_SDALIGN, false);
3238 if (pnext == NULL) {
3239 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
3240 __func__, num, sublen));
3243 ASSERT(!PKTLINK(pnext));
3246 pfirst = plast = pnext;
3249 PKTSETNEXT(plast, pnext);
3253 /* Adhere to start alignment requirements */
3254 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3257 /* If all allocations succeeded, save packet chain
3260 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3261 "subframes\n", __func__, totlen, num));
3262 if (DHD_GLOM_ON() && bus->nextlen) {
3263 if (totlen != bus->nextlen) {
3264 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3265 __func__, bus->nextlen,
3270 pfirst = pnext = NULL;
3273 PKTFREE(osh, pfirst, false);
3278 /* Done with descriptor packet */
3279 PKTFREE(osh, bus->glomd, false);
3283 dhd_os_sdunlock_rxq(bus->dhd);
3286 /* Ok -- either we just generated a packet chain,
3287 or had one from before */
3289 if (DHD_GLOM_ON()) {
3290 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3292 for (pnext = bus->glom; pnext; pnext = PKTNEXT(pnext)) {
3293 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3294 pnext, (u8 *) PKTDATA(pnext),
3295 PKTLEN(pnext), PKTLEN(pnext)));
3300 dlen = (u16) pkttotlen(osh, pfirst);
3302 /* Do an SDIO read for the superframe. Configurable iovar to
3303 * read directly into the chained packet, or allocate a large
3304 * packet and and copy into the chain.
3307 errcode = dhd_bcmsdh_recv_buf(bus,
3309 (bus->sdh), SDIO_FUNC_2,
3311 (u8 *) PKTDATA(pfirst),
3312 dlen, pfirst, NULL, NULL);
3313 } else if (bus->dataptr) {
3314 errcode = dhd_bcmsdh_recv_buf(bus,
3316 (bus->sdh), SDIO_FUNC_2,
3317 F2SYNC, bus->dataptr,
3318 dlen, NULL, NULL, NULL);
3320 (u16) pktfrombuf(osh, pfirst, 0, dlen,
3322 if (sublen != dlen) {
3323 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3324 __func__, dlen, sublen));
3329 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3334 ASSERT(errcode != BCME_PENDING);
3336 /* On failure, kill the superframe, allow a couple retries */
3338 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3339 __func__, dlen, errcode));
3340 bus->dhd->rx_errors++;
3342 if (bus->glomerr++ < 3) {
3343 dhdsdio_rxfail(bus, true, true);
3346 dhdsdio_rxfail(bus, true, false);
3347 dhd_os_sdlock_rxq(bus->dhd);
3348 PKTFREE(osh, bus->glom, false);
3349 dhd_os_sdunlock_rxq(bus->dhd);
3356 if (DHD_GLOM_ON()) {
3357 prhex("SUPERFRAME", PKTDATA(pfirst),
3358 min_t(int, PKTLEN(pfirst), 48));
3362 /* Validate the superframe header */
3363 dptr = (u8 *) PKTDATA(pfirst);
3364 sublen = ltoh16_ua(dptr);
3365 check = ltoh16_ua(dptr + sizeof(u16));
3367 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3368 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3369 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3370 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3371 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3372 __func__, bus->nextlen, seq));
3375 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3376 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3379 if ((u16)~(sublen ^ check)) {
3380 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3381 "0x%04x/0x%04x\n", __func__, sublen, check));
3383 } else if (roundup(sublen, bus->blocksize) != dlen) {
3384 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3385 "0x%04x, expect 0x%04x\n",
3387 roundup(sublen, bus->blocksize), dlen));
3389 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3390 SDPCM_GLOM_CHANNEL) {
3391 DHD_ERROR(("%s (superframe): bad channel %d\n",
3393 SDPCM_PACKET_CHANNEL(&dptr
3394 [SDPCM_FRAMETAG_LEN])));
3396 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3397 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3400 } else if ((doff < SDPCM_HDRLEN) ||
3401 (doff > (PKTLEN(pfirst) - SDPCM_HDRLEN))) {
3402 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3404 __func__, doff, sublen,
3405 PKTLEN(pfirst), SDPCM_HDRLEN));
3409 /* Check sequence number of superframe SW header */
3411 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3412 __func__, seq, rxseq));
3417 /* Check window for sanity */
3418 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3419 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3420 __func__, txmax, bus->tx_seq));
3421 txmax = bus->tx_seq + 2;
3423 bus->tx_max = txmax;
3425 /* Remove superframe header, remember offset */
3426 PKTPULL(pfirst, doff);
3429 /* Validate all the subframe headers */
3430 for (num = 0, pnext = pfirst; pnext && !errcode;
3431 num++, pnext = PKTNEXT(pnext)) {
3432 dptr = (u8 *) PKTDATA(pnext);
3433 dlen = (u16) PKTLEN(pnext);
3434 sublen = ltoh16_ua(dptr);
3435 check = ltoh16_ua(dptr + sizeof(u16));
3436 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3437 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3440 prhex("subframe", dptr, 32);
3443 if ((u16)~(sublen ^ check)) {
3444 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3445 "len/check 0x%04x/0x%04x\n",
3446 __func__, num, sublen, check));
3448 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3449 DHD_ERROR(("%s (subframe %d): length mismatch: "
3450 "len 0x%04x, expect 0x%04x\n",
3451 __func__, num, sublen, dlen));
3453 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3454 (chan != SDPCM_EVENT_CHANNEL)) {
3455 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3456 __func__, num, chan));
3458 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3459 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3460 __func__, num, doff, sublen,
3467 /* Terminate frame on error, request
3469 if (bus->glomerr++ < 3) {
3470 /* Restore superframe header space */
3471 PKTPUSH(pfirst, sfdoff);
3472 dhdsdio_rxfail(bus, true, true);
3475 dhdsdio_rxfail(bus, true, false);
3476 dhd_os_sdlock_rxq(bus->dhd);
3477 PKTFREE(osh, bus->glom, false);
3478 dhd_os_sdunlock_rxq(bus->dhd);
3486 /* Basic SD framing looks ok - process each packet (header) */
3487 save_pfirst = pfirst;
3491 dhd_os_sdlock_rxq(bus->dhd);
3492 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3493 pnext = PKTNEXT(pfirst);
3494 PKTSETNEXT(pfirst, NULL);
3496 dptr = (u8 *) PKTDATA(pfirst);
3497 sublen = ltoh16_ua(dptr);
3498 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3499 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3500 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3502 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3504 __func__, num, pfirst, PKTDATA(pfirst),
3505 PKTLEN(pfirst), sublen, chan, seq));
3507 ASSERT((chan == SDPCM_DATA_CHANNEL)
3508 || (chan == SDPCM_EVENT_CHANNEL));
3511 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3512 __func__, seq, rxseq));
3517 if (DHD_BYTES_ON() && DHD_DATA_ON())
3518 prhex("Rx Subframe Data", dptr, dlen);
3521 PKTSETLEN(pfirst, sublen);
3522 PKTPULL(pfirst, doff);
3524 if (PKTLEN(pfirst) == 0) {
3525 PKTFREE(bus->dhd->osh, pfirst, false);
3527 PKTSETNEXT(plast, pnext);
3529 ASSERT(save_pfirst == pfirst);
3530 save_pfirst = pnext;
3533 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3535 DHD_ERROR(("%s: rx protocol error\n",
3537 bus->dhd->rx_errors++;
3538 PKTFREE(osh, pfirst, false);
3540 PKTSETNEXT(plast, pnext);
3542 ASSERT(save_pfirst == pfirst);
3543 save_pfirst = pnext;
3548 /* this packet will go up, link back into
3549 chain and count it */
3550 PKTSETNEXT(pfirst, pnext);
3555 if (DHD_GLOM_ON()) {
3556 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3558 __func__, num, pfirst, PKTDATA(pfirst),
3559 PKTLEN(pfirst), PKTNEXT(pfirst),
3561 prhex("", (u8 *) PKTDATA(pfirst),
3562 min_t(int, PKTLEN(pfirst), 32));
3564 #endif /* DHD_DEBUG */
3566 dhd_os_sdunlock_rxq(bus->dhd);
3568 dhd_os_sdunlock(bus->dhd);
3569 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3570 dhd_os_sdlock(bus->dhd);
3573 bus->rxglomframes++;
3574 bus->rxglompkts += num;
3579 /* Return true if there may be more frames to read */
3580 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3582 osl_t *osh = bus->dhd->osh;
3583 bcmsdh_info_t *sdh = bus->sdh;
3585 u16 len, check; /* Extracted hardware header fields */
3586 u8 chan, seq, doff; /* Extracted software header fields */
3587 u8 fcbits; /* Extracted fcbits from software header */
3590 void *pkt; /* Packet for event or data frames */
3591 u16 pad; /* Number of pad bytes to read */
3592 u16 rdlen; /* Total number of bytes to read */
3593 u8 rxseq; /* Next sequence number to expect */
3594 uint rxleft = 0; /* Remaining number of frames allowed */
3595 int sdret; /* Return code from bcmsdh calls */
3596 u8 txmax; /* Maximum tx sequence offered */
3597 bool len_consistent; /* Result of comparing readahead len and
3601 uint rxcount = 0; /* Total frames read */
3603 #if defined(DHD_DEBUG) || defined(SDTEST)
3604 bool sdtest = false; /* To limit message spew from test mode */
3607 DHD_TRACE(("%s: Enter\n", __func__));
3612 /* Allow pktgen to override maxframes */
3613 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3614 maxframes = bus->pktgen_count;
3619 /* Not finished unless we encounter no more frames indication */
3622 for (rxseq = bus->rx_seq, rxleft = maxframes;
3623 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3624 rxseq++, rxleft--) {
3626 /* Handle glomming separately */
3627 if (bus->glom || bus->glomd) {
3629 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3630 __func__, bus->glomd, bus->glom));
3631 cnt = dhdsdio_rxglom(bus, rxseq);
3632 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3634 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3638 /* Try doing single read if we can */
3639 if (dhd_readahead && bus->nextlen) {
3640 u16 nextlen = bus->nextlen;
3643 if (bus->bus == SPI_BUS) {
3644 rdlen = len = nextlen;
3646 rdlen = len = nextlen << 4;
3648 /* Pad read to blocksize for efficiency */
3649 if (bus->roundup && bus->blocksize
3650 && (rdlen > bus->blocksize)) {
3653 (rdlen % bus->blocksize);
3654 if ((pad <= bus->roundup)
3655 && (pad < bus->blocksize)
3656 && ((rdlen + pad + firstread) <
3659 } else if (rdlen % DHD_SDALIGN) {
3661 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3665 /* We use bus->rxctl buffer in WinXP for initial
3666 * control pkt receives.
3667 * Later we use buffer-poll for data as well
3668 * as control packets.
3669 * This is required becuase dhd receives full
3670 * frame in gSPI unlike SDIO.
3671 * After the frame is received we have to
3672 * distinguish whether it is data
3673 * or non-data frame.
3675 /* Allocate a packet buffer */
3676 dhd_os_sdlock_rxq(bus->dhd);
3677 pkt = PKTGET(osh, rdlen + DHD_SDALIGN, false);
3679 if (bus->bus == SPI_BUS) {
3680 bus->usebufpool = false;
3681 bus->rxctl = bus->rxbuf;
3683 bus->rxctl += firstread;
3684 pad = ((unsigned long)bus->rxctl %
3688 (DHD_SDALIGN - pad);
3689 bus->rxctl -= firstread;
3691 ASSERT(bus->rxctl >= bus->rxbuf);
3693 /* Read the entire frame */
3694 sdret = dhd_bcmsdh_recv_buf(bus,
3703 ASSERT(sdret != BCME_PENDING);
3705 /* Control frame failures need
3708 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3711 /* dhd.rx_ctlerrs is higher */
3713 dhd_os_sdunlock_rxq(bus->dhd);
3714 dhdsdio_rxfail(bus, true,
3722 request rtx of events */
3723 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d " "expected rxseq %d\n",
3724 __func__, len, rdlen, rxseq));
3725 /* Just go try again w/normal
3727 dhd_os_sdunlock_rxq(bus->dhd);
3731 if (bus->bus == SPI_BUS)
3732 bus->usebufpool = true;
3734 ASSERT(!PKTLINK(pkt));
3735 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3736 rxbuf = (u8 *) PKTDATA(pkt);
3737 /* Read the entire frame */
3739 dhd_bcmsdh_recv_buf(bus,
3740 bcmsdh_cur_sbwad(sdh),
3741 SDIO_FUNC_2, F2SYNC,
3742 rxbuf, rdlen, pkt, NULL,
3745 ASSERT(sdret != BCME_PENDING);
3748 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3749 __func__, rdlen, sdret));
3750 PKTFREE(bus->dhd->osh, pkt, false);
3751 bus->dhd->rx_errors++;
3752 dhd_os_sdunlock_rxq(bus->dhd);
3753 /* Force retry w/normal header read.
3754 * Don't attemp NAK for
3757 dhdsdio_rxfail(bus, true,
3764 dhd_os_sdunlock_rxq(bus->dhd);
3766 /* Now check the header */
3767 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3769 /* Extract hardware header fields */
3770 len = ltoh16_ua(bus->rxhdr);
3771 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3773 /* All zeros means readahead info was bad */
3774 if (!(len | check)) {
3775 DHD_INFO(("%s (nextlen): read zeros in HW "
3776 "header???\n", __func__));
3777 dhd_os_sdlock_rxq(bus->dhd);
3779 dhd_os_sdunlock_rxq(bus->dhd);
3780 GSPI_PR55150_BAILOUT;
3784 /* Validate check bytes */
3785 if ((u16)~(len ^ check)) {
3786 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3787 __func__, nextlen, len, check));
3788 dhd_os_sdlock_rxq(bus->dhd);
3790 dhd_os_sdunlock_rxq(bus->dhd);
3792 dhdsdio_rxfail(bus, false, false);
3793 GSPI_PR55150_BAILOUT;
3797 /* Validate frame length */
3798 if (len < SDPCM_HDRLEN) {
3799 DHD_ERROR(("%s (nextlen): HW hdr length "
3800 "invalid: %d\n", __func__, len));
3801 dhd_os_sdlock_rxq(bus->dhd);
3803 dhd_os_sdunlock_rxq(bus->dhd);
3804 GSPI_PR55150_BAILOUT;
3808 /* Check for consistency withreadahead info */
3809 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3810 if (len_consistent) {
3811 /* Mismatch, force retry w/normal
3812 header (may be >4K) */
3813 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3815 len, roundup(len, 16), rxseq));
3816 dhd_os_sdlock_rxq(bus->dhd);
3818 dhd_os_sdunlock_rxq(bus->dhd);
3819 dhdsdio_rxfail(bus, true,
3821 SPI_BUS) ? false : true);
3822 GSPI_PR55150_BAILOUT;
3826 /* Extract software header fields */
3828 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3829 [SDPCM_FRAMETAG_LEN]);
3831 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3832 [SDPCM_FRAMETAG_LEN]);
3834 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3835 [SDPCM_FRAMETAG_LEN]);
3837 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3840 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3841 SDPCM_NEXTLEN_OFFSET];
3842 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3843 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3844 __func__, bus->nextlen, seq));
3848 bus->dhd->rx_readahead_cnt++;
3849 /* Handle Flow Control */
3851 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3854 if (~bus->flowcontrol & fcbits) {
3858 if (bus->flowcontrol & ~fcbits) {
3865 bus->flowcontrol = fcbits;
3868 /* Check and update sequence number */
3870 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3871 "%d\n", __func__, seq, rxseq));
3876 /* Check window for sanity */
3877 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3878 DHD_ERROR(("%s: got unlikely tx max %d with "
3880 __func__, txmax, bus->tx_seq));
3881 txmax = bus->tx_seq + 2;
3883 bus->tx_max = txmax;
3886 if (DHD_BYTES_ON() && DHD_DATA_ON())
3887 prhex("Rx Data", rxbuf, len);
3888 else if (DHD_HDRS_ON())
3889 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3892 if (chan == SDPCM_CONTROL_CHANNEL) {
3893 if (bus->bus == SPI_BUS) {
3894 dhdsdio_read_control(bus, rxbuf, len,
3896 if (bus->usebufpool) {
3897 dhd_os_sdlock_rxq(bus->dhd);
3898 PKTFREE(bus->dhd->osh, pkt,
3900 dhd_os_sdunlock_rxq(bus->dhd);
3904 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3906 /* Force retry w/normal header read */
3908 dhdsdio_rxfail(bus, false, true);
3909 dhd_os_sdlock_rxq(bus->dhd);
3911 dhd_os_sdunlock_rxq(bus->dhd);
3916 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3917 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3922 /* Validate data offset */
3923 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3924 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3925 __func__, doff, len, SDPCM_HDRLEN));
3926 dhd_os_sdlock_rxq(bus->dhd);
3928 dhd_os_sdunlock_rxq(bus->dhd);
3930 dhdsdio_rxfail(bus, false, false);
3934 /* All done with this one -- now deliver the packet */
3937 /* gSPI frames should not be handled in fractions */
3938 if (bus->bus == SPI_BUS)
3941 /* Read frame header (hardware and software) */
3943 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3944 F2SYNC, bus->rxhdr, firstread, NULL,
3947 ASSERT(sdret != BCME_PENDING);
3950 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3953 dhdsdio_rxfail(bus, true, true);
3957 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3958 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3961 /* Extract hardware header fields */
3962 len = ltoh16_ua(bus->rxhdr);
3963 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
3965 /* All zeros means no more frames */
3966 if (!(len | check)) {
3971 /* Validate check bytes */
3972 if ((u16) ~(len ^ check)) {
3973 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3974 __func__, len, check));
3976 dhdsdio_rxfail(bus, false, false);
3980 /* Validate frame length */
3981 if (len < SDPCM_HDRLEN) {
3982 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3987 /* Extract software header fields */
3988 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3989 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3990 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3991 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3993 /* Validate data offset */
3994 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3995 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3997 __func__, doff, len, SDPCM_HDRLEN, seq));
4000 dhdsdio_rxfail(bus, false, false);
4004 /* Save the readahead length if there is one */
4006 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4007 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4008 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4010 __func__, bus->nextlen, seq));
4014 /* Handle Flow Control */
4015 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4018 if (~bus->flowcontrol & fcbits) {
4022 if (bus->flowcontrol & ~fcbits) {
4029 bus->flowcontrol = fcbits;
4032 /* Check and update sequence number */
4034 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4040 /* Check window for sanity */
4041 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4042 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4043 __func__, txmax, bus->tx_seq));
4044 txmax = bus->tx_seq + 2;
4046 bus->tx_max = txmax;
4048 /* Call a separate function for control frames */
4049 if (chan == SDPCM_CONTROL_CHANNEL) {
4050 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4054 ASSERT((chan == SDPCM_DATA_CHANNEL)
4055 || (chan == SDPCM_EVENT_CHANNEL)
4056 || (chan == SDPCM_TEST_CHANNEL)
4057 || (chan == SDPCM_GLOM_CHANNEL));
4059 /* Length to read */
4060 rdlen = (len > firstread) ? (len - firstread) : 0;
4062 /* May pad read to blocksize for efficiency */
4063 if (bus->roundup && bus->blocksize &&
4064 (rdlen > bus->blocksize)) {
4065 pad = bus->blocksize - (rdlen % bus->blocksize);
4066 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4067 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4069 } else if (rdlen % DHD_SDALIGN) {
4070 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4073 /* Satisfy length-alignment requirements */
4074 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4075 rdlen = roundup(rdlen, ALIGNMENT);
4077 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4078 /* Too long -- skip this frame */
4079 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4080 __func__, len, rdlen));
4081 bus->dhd->rx_errors++;
4083 dhdsdio_rxfail(bus, false, false);
4087 dhd_os_sdlock_rxq(bus->dhd);
4088 pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), false);
4090 /* Give up on data, request rtx of events */
4091 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
4092 __func__, rdlen, chan));
4093 bus->dhd->rx_dropped++;
4094 dhd_os_sdunlock_rxq(bus->dhd);
4095 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4098 dhd_os_sdunlock_rxq(bus->dhd);
4100 ASSERT(!PKTLINK(pkt));
4102 /* Leave room for what we already read, and align remainder */
4103 ASSERT(firstread < (PKTLEN(pkt)));
4104 PKTPULL(pkt, firstread);
4105 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4107 /* Read the remaining frame data */
4109 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4110 F2SYNC, ((u8 *) PKTDATA(pkt)), rdlen,
4113 ASSERT(sdret != BCME_PENDING);
4116 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4119 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4121 ? "data" : "test")),
4123 dhd_os_sdlock_rxq(bus->dhd);
4124 PKTFREE(bus->dhd->osh, pkt, false);
4125 dhd_os_sdunlock_rxq(bus->dhd);
4126 bus->dhd->rx_errors++;
4127 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4131 /* Copy the already-read portion */
4132 PKTPUSH(pkt, firstread);
4133 bcopy(bus->rxhdr, PKTDATA(pkt), firstread);
4136 if (DHD_BYTES_ON() && DHD_DATA_ON())
4137 prhex("Rx Data", PKTDATA(pkt), len);
4141 /* Save superframe descriptor and allocate packet frame */
4142 if (chan == SDPCM_GLOM_CHANNEL) {
4143 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4144 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4147 if (DHD_GLOM_ON()) {
4148 prhex("Glom Data", PKTDATA(pkt), len);
4151 PKTSETLEN(pkt, len);
4152 ASSERT(doff == SDPCM_HDRLEN);
4153 PKTPULL(pkt, SDPCM_HDRLEN);
4156 DHD_ERROR(("%s: glom superframe w/o "
4157 "descriptor!\n", __func__));
4158 dhdsdio_rxfail(bus, false, false);
4163 /* Fill in packet len and prio, deliver upward */
4164 PKTSETLEN(pkt, len);
4168 /* Test channel packets are processed separately */
4169 if (chan == SDPCM_TEST_CHANNEL) {
4170 dhdsdio_testrcv(bus, pkt, seq);
4175 if (PKTLEN(pkt) == 0) {
4176 dhd_os_sdlock_rxq(bus->dhd);
4177 PKTFREE(bus->dhd->osh, pkt, false);
4178 dhd_os_sdunlock_rxq(bus->dhd);
4180 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4181 DHD_ERROR(("%s: rx protocol error\n", __func__));
4182 dhd_os_sdlock_rxq(bus->dhd);
4183 PKTFREE(bus->dhd->osh, pkt, false);
4184 dhd_os_sdunlock_rxq(bus->dhd);
4185 bus->dhd->rx_errors++;
4189 /* Unlock during rx call */
4190 dhd_os_sdunlock(bus->dhd);
4191 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4192 dhd_os_sdlock(bus->dhd);
4194 rxcount = maxframes - rxleft;
4196 /* Message if we hit the limit */
4197 if (!rxleft && !sdtest)
4198 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4201 #endif /* DHD_DEBUG */
4202 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4203 /* Back off rxseq if awaiting rtx, update rx_seq */
4206 bus->rx_seq = rxseq;
4211 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4213 sdpcmd_regs_t *regs = bus->regs;
4219 DHD_TRACE(("%s: Enter\n", __func__));
4221 /* Read mailbox data and ack that we did so */
4222 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4223 if (retries <= retry_limit)
4224 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4225 bus->f1regdata += 2;
4227 /* Dongle recomposed rx frames, accept them again */
4228 if (hmb_data & HMB_DATA_NAKHANDLED) {
4229 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4232 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4234 bus->rxskip = false;
4235 intstatus |= I_HMB_FRAME_IND;
4239 * DEVREADY does not occur with gSPI.
4241 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4243 (hmb_data & HMB_DATA_VERSION_MASK) >>
4244 HMB_DATA_VERSION_SHIFT;
4245 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4246 DHD_ERROR(("Version mismatch, dongle reports %d, "
4248 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4250 DHD_INFO(("Dongle ready, protocol version %d\n",
4255 * Flow Control has been moved into the RX headers and this out of band
4256 * method isn't used any more. Leae this here for possibly
4257 * remaining backward
4258 * compatible with older dongles
4260 if (hmb_data & HMB_DATA_FC) {
4262 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4264 if (fcbits & ~bus->flowcontrol)
4266 if (bus->flowcontrol & ~fcbits)
4270 bus->flowcontrol = fcbits;
4273 /* Shouldn't be any others */
4274 if (hmb_data & ~(HMB_DATA_DEVREADY |
4275 HMB_DATA_NAKHANDLED |
4278 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4279 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4285 bool dhdsdio_dpc(dhd_bus_t *bus)
4287 bcmsdh_info_t *sdh = bus->sdh;
4288 sdpcmd_regs_t *regs = bus->regs;
4289 u32 intstatus, newstatus = 0;
4291 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4292 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4293 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4294 bool rxdone = true; /* Flag for no more read data */
4295 bool resched = false; /* Flag indicating resched wanted */
4297 DHD_TRACE(("%s: Enter\n", __func__));
4299 /* Start with leftover status bits */
4300 intstatus = bus->intstatus;
4302 dhd_os_sdlock(bus->dhd);
4304 /* If waiting for HTAVAIL, check status */
4305 if (bus->clkstate == CLK_PENDING) {
4307 u8 clkctl, devctl = 0;
4310 /* Check for inconsistent device control */
4312 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4314 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4316 bus->dhd->busstate = DHD_BUS_DOWN;
4318 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4320 #endif /* DHD_DEBUG */
4322 /* Read CSR, if clock on switch to AVAIL, else ignore */
4324 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4327 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4329 bus->dhd->busstate = DHD_BUS_DOWN;
4332 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4335 if (SBSDIO_HTAV(clkctl)) {
4337 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4340 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4342 bus->dhd->busstate = DHD_BUS_DOWN;
4344 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4345 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4348 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4350 bus->dhd->busstate = DHD_BUS_DOWN;
4352 bus->clkstate = CLK_AVAIL;
4360 /* Make sure backplane clock is on */
4361 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4362 if (bus->clkstate == CLK_PENDING)
4365 /* Pending interrupt indicates new device status */
4368 R_SDREG(newstatus, ®s->intstatus, retries);
4370 if (bcmsdh_regfail(bus->sdh))
4372 newstatus &= bus->hostintmask;
4373 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4375 W_SDREG(newstatus, ®s->intstatus, retries);
4380 /* Merge new bits with previous */
4381 intstatus |= newstatus;
4384 /* Handle flow-control change: read new state in case our ack
4385 * crossed another change interrupt. If change still set, assume
4386 * FC ON for safety, let next loop through do the debounce.
4388 if (intstatus & I_HMB_FC_CHANGE) {
4389 intstatus &= ~I_HMB_FC_CHANGE;
4390 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4391 R_SDREG(newstatus, ®s->intstatus, retries);
4392 bus->f1regdata += 2;
4394 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4395 intstatus |= (newstatus & bus->hostintmask);
4398 /* Handle host mailbox indication */
4399 if (intstatus & I_HMB_HOST_INT) {
4400 intstatus &= ~I_HMB_HOST_INT;
4401 intstatus |= dhdsdio_hostmail(bus);
4404 /* Generally don't ask for these, can get CRC errors... */
4405 if (intstatus & I_WR_OOSYNC) {
4406 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4407 intstatus &= ~I_WR_OOSYNC;
4410 if (intstatus & I_RD_OOSYNC) {
4411 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4412 intstatus &= ~I_RD_OOSYNC;
4415 if (intstatus & I_SBINT) {
4416 DHD_ERROR(("Dongle reports SBINT\n"));
4417 intstatus &= ~I_SBINT;
4420 /* Would be active due to wake-wlan in gSPI */
4421 if (intstatus & I_CHIPACTIVE) {
4422 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4423 intstatus &= ~I_CHIPACTIVE;
4426 /* Ignore frame indications if rxskip is set */
4428 intstatus &= ~I_HMB_FRAME_IND;
4430 /* On frame indication, read available frames */
4431 if (PKT_AVAILABLE()) {
4432 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4433 if (rxdone || bus->rxskip)
4434 intstatus &= ~I_HMB_FRAME_IND;
4435 rxlimit -= min(framecnt, rxlimit);
4438 /* Keep still-pending events for next scheduling */
4439 bus->intstatus = intstatus;
4442 #if defined(OOB_INTR_ONLY)
4443 bcmsdh_oob_intr_set(1);
4444 #endif /* (OOB_INTR_ONLY) */
4445 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4446 * or clock availability. (Allows tx loop to check ipend if desired.)
4447 * (Unless register access seems hosed, as we may not be able to ACK...)
4449 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4450 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4451 __func__, rxdone, framecnt));
4452 bus->intdis = false;
4453 bcmsdh_intr_enable(sdh);
4456 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4457 (bus->clkstate == CLK_AVAIL)) {
4461 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4462 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4463 (u32) bus->ctrl_frame_len, NULL,
4465 ASSERT(ret != BCME_PENDING);
4468 /* On failure, abort the command and
4469 terminate the frame */
4470 DHD_INFO(("%s: sdio error %d, abort command and "
4471 "terminate frame.\n", __func__, ret));
4474 bcmsdh_abort(sdh, SDIO_FUNC_2);
4476 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4477 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4481 for (i = 0; i < 3; i++) {
4483 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4484 SBSDIO_FUNC1_WFRAMEBCHI,
4486 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4487 SBSDIO_FUNC1_WFRAMEBCLO,
4489 bus->f1regdata += 2;
4490 if ((hi == 0) && (lo == 0))
4496 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4498 printf("Return_dpc value is : %d\n", ret);
4499 bus->ctrl_frame_stat = false;
4500 dhd_wait_event_wakeup(bus->dhd);
4502 /* Send queued frames (limit 1 if rx may still be pending) */
4503 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4504 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4506 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4507 framecnt = dhdsdio_sendfromq(bus, framecnt);
4508 txlimit -= framecnt;
4511 /* Resched if events or tx frames are pending,
4512 else await next interrupt */
4513 /* On failed register access, all bets are off:
4514 no resched or interrupts */
4515 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4516 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4517 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4518 bus->dhd->busstate = DHD_BUS_DOWN;
4520 } else if (bus->clkstate == CLK_PENDING) {
4521 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4522 "I_CHIPACTIVE interrupt\n", __func__));
4524 } else if (bus->intstatus || bus->ipend ||
4525 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4526 DATAOK(bus)) || PKT_AVAILABLE()) {
4530 bus->dpc_sched = resched;
4532 /* If we're done for now, turn off clock request. */
4533 if ((bus->clkstate != CLK_PENDING)
4534 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4535 bus->activity = false;
4536 dhdsdio_clkctl(bus, CLK_NONE, false);
4539 dhd_os_sdunlock(bus->dhd);
4544 bool dhd_bus_dpc(struct dhd_bus *bus)
4548 /* Call the DPC directly. */
4549 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4550 resched = dhdsdio_dpc(bus);
4555 void dhdsdio_isr(void *arg)
4557 dhd_bus_t *bus = (dhd_bus_t *) arg;
4560 DHD_TRACE(("%s: Enter\n", __func__));
4563 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4568 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4569 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4573 /* Count the interrupt call */
4577 /* Shouldn't get this interrupt if we're sleeping? */
4578 if (bus->sleeping) {
4579 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4583 /* Disable additional interrupts (is this needed now)? */
4585 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4587 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4589 bcmsdh_intr_disable(sdh);
4592 #if defined(SDIO_ISR_THREAD)
4593 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4594 while (dhdsdio_dpc(bus))
4597 bus->dpc_sched = true;
4598 dhd_sched_dpc(bus->dhd);
4604 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4606 /* Default to specified length, or full range */
4607 if (dhd_pktgen_len) {
4608 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4609 bus->pktgen_minlen = bus->pktgen_maxlen;
4611 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4612 bus->pktgen_minlen = 0;
4614 bus->pktgen_len = (u16) bus->pktgen_minlen;
4616 /* Default to per-watchdog burst with 10s print time */
4617 bus->pktgen_freq = 1;
4618 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4619 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4621 /* Default to echo mode */
4622 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4623 bus->pktgen_stop = 1;
4626 static void dhdsdio_pktgen(dhd_bus_t *bus)
4632 osl_t *osh = bus->dhd->osh;
4635 /* Display current count if appropriate */
4636 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4637 bus->pktgen_ptick = 0;
4638 printf("%s: send attempts %d rcvd %d\n",
4639 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4642 /* For recv mode, just make sure dongle has started sending */
4643 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4644 if (!bus->pktgen_rcvd)
4645 dhdsdio_sdtest_set(bus, true);
4649 /* Otherwise, generate or request the specified number of packets */
4650 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4651 /* Stop if total has been reached */
4652 if (bus->pktgen_total
4653 && (bus->pktgen_sent >= bus->pktgen_total)) {
4654 bus->pktgen_count = 0;
4658 /* Allocate an appropriate-sized packet */
4659 len = bus->pktgen_len;
4661 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4664 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4667 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4669 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4671 /* Write test header cmd and extra based on mode */
4672 switch (bus->pktgen_mode) {
4673 case DHD_PKTGEN_ECHO:
4674 *data++ = SDPCM_TEST_ECHOREQ;
4675 *data++ = (u8) bus->pktgen_sent;
4678 case DHD_PKTGEN_SEND:
4679 *data++ = SDPCM_TEST_DISCARD;
4680 *data++ = (u8) bus->pktgen_sent;
4683 case DHD_PKTGEN_RXBURST:
4684 *data++ = SDPCM_TEST_BURST;
4685 *data++ = (u8) bus->pktgen_count;
4689 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4691 PKTFREE(osh, pkt, true);
4692 bus->pktgen_count = 0;
4696 /* Write test header length field */
4697 *data++ = (len >> 0);
4698 *data++ = (len >> 8);
4700 /* Then fill in the remainder -- N/A for burst,
4702 for (fillbyte = 0; fillbyte < len; fillbyte++)
4704 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4707 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4708 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4709 prhex("dhdsdio_pktgen: Tx Data", data,
4710 PKTLEN(pkt) - SDPCM_HDRLEN);
4715 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4717 if (bus->pktgen_stop
4718 && bus->pktgen_stop == bus->pktgen_fail)
4719 bus->pktgen_count = 0;
4723 /* Bump length if not fixed, wrap at max */
4724 if (++bus->pktgen_len > bus->pktgen_maxlen)
4725 bus->pktgen_len = (u16) bus->pktgen_minlen;
4727 /* Special case for burst mode: just send one request! */
4728 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4733 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4737 osl_t *osh = bus->dhd->osh;
4739 /* Allocate the packet */
4740 pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4743 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4746 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4747 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
4749 /* Fill in the test header */
4750 *data++ = SDPCM_TEST_SEND;
4752 *data++ = (bus->pktgen_maxlen >> 0);
4753 *data++ = (bus->pktgen_maxlen >> 8);
4756 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4760 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
4762 osl_t *osh = bus->dhd->osh;
4771 /* Check for min length */
4772 pktlen = PKTLEN(pkt);
4773 if (pktlen < SDPCM_TEST_HDRLEN) {
4774 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4776 PKTFREE(osh, pkt, false);
4780 /* Extract header fields */
4781 data = PKTDATA(pkt);
4785 len += *data++ << 8;
4787 /* Check length for relevant commands */
4788 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4789 || cmd == SDPCM_TEST_ECHORSP) {
4790 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4791 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4792 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4793 pktlen, seq, cmd, extra, len));
4794 PKTFREE(osh, pkt, false);
4799 /* Process as per command */
4801 case SDPCM_TEST_ECHOREQ:
4802 /* Rx->Tx turnaround ok (even on NDIS w/current
4804 *(u8 *) (PKTDATA(pkt)) = SDPCM_TEST_ECHORSP;
4805 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4809 PKTFREE(osh, pkt, false);
4814 case SDPCM_TEST_ECHORSP:
4815 if (bus->ext_loop) {
4816 PKTFREE(osh, pkt, false);
4821 for (offset = 0; offset < len; offset++, data++) {
4822 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4823 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4825 SDPCM_TEST_FILL(offset, extra), *data));
4829 PKTFREE(osh, pkt, false);
4833 case SDPCM_TEST_DISCARD:
4834 PKTFREE(osh, pkt, false);
4838 case SDPCM_TEST_BURST:
4839 case SDPCM_TEST_SEND:
4841 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4842 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4843 pktlen, seq, cmd, extra, len));
4844 PKTFREE(osh, pkt, false);
4848 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4849 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4850 if (bus->pktgen_total
4851 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4852 bus->pktgen_count = 0;
4853 dhdsdio_sdtest_set(bus, false);
4859 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4863 DHD_TIMER(("%s: Enter\n", __func__));
4867 if (bus->dhd->dongle_reset)
4870 /* Ignore the timer if simulating bus down */
4874 dhd_os_sdlock(bus->dhd);
4876 /* Poll period: check device if appropriate. */
4877 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4880 /* Reset poll tick */
4883 /* Check device if no interrupts */
4884 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4886 if (!bus->dpc_sched) {
4888 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4892 devpend & (INTR_STATUS_FUNC1 |
4896 /* If there is something, make like the ISR and
4902 bcmsdh_intr_disable(bus->sdh);
4904 bus->dpc_sched = true;
4905 dhd_sched_dpc(bus->dhd);
4910 /* Update interrupt tracking */
4911 bus->lastintrs = bus->intrcount;
4914 /* Poll for console output periodically */
4915 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4916 bus->console.count += dhd_watchdog_ms;
4917 if (bus->console.count >= dhd_console_ms) {
4918 bus->console.count -= dhd_console_ms;
4919 /* Make sure backplane clock is on */
4920 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4921 if (dhdsdio_readconsole(bus) < 0)
4922 dhd_console_ms = 0; /* On error,
4926 #endif /* DHD_DEBUG */
4929 /* Generate packets if configured */
4930 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4931 /* Make sure backplane clock is on */
4932 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4933 bus->pktgen_tick = 0;
4934 dhdsdio_pktgen(bus);
4938 /* On idle timeout clear activity flag and/or turn off clock */
4939 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4940 if (++bus->idlecount >= bus->idletime) {
4942 if (bus->activity) {
4943 bus->activity = false;
4944 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4946 dhdsdio_clkctl(bus, CLK_NONE, false);
4951 dhd_os_sdunlock(bus->dhd);
4957 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4959 dhd_bus_t *bus = dhdp->bus;
4964 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4965 if (bus->console_addr == 0)
4966 return BCME_UNSUPPORTED;
4968 /* Exclusive bus access */
4969 dhd_os_sdlock(bus->dhd);
4971 /* Don't allow input if dongle is in reset */
4972 if (bus->dhd->dongle_reset) {
4973 dhd_os_sdunlock(bus->dhd);
4974 return BCME_NOTREADY;
4977 /* Request clock to allow SDIO accesses */
4979 /* No pend allowed since txpkt is called later, ht clk has to be on */
4980 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4982 /* Zero cbuf_index */
4983 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4985 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4989 /* Write message into cbuf */
4990 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4991 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4995 /* Write length into vcons_in */
4996 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
4997 val = htol32(msglen);
4998 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5002 /* Bump dongle by sending an empty event pkt.
5003 * sdpcm_sendup (RX) checks for virtual console input.
5005 pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, true);
5006 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5007 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5010 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5011 bus->activity = false;
5012 dhdsdio_clkctl(bus, CLK_NONE, true);
5015 dhd_os_sdunlock(bus->dhd);
5019 #endif /* DHD_DEBUG */
5022 static void dhd_dump_cis(uint fn, u8 *cis)
5024 uint byte, tag, tdata;
5025 DHD_INFO(("Function %d CIS:\n", fn));
5027 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5028 if ((byte % 16) == 0)
5030 DHD_INFO(("%02x ", cis[byte]));
5031 if ((byte % 16) == 15)
5039 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5040 tdata = cis[byte + 1] + 1;
5045 if ((byte % 16) != 15)
5048 #endif /* DHD_DEBUG */
5050 static bool dhdsdio_chipmatch(u16 chipid)
5052 if (chipid == BCM4325_CHIP_ID)
5054 if (chipid == BCM4329_CHIP_ID)
5056 if (chipid == BCM4319_CHIP_ID)
5061 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5062 u16 slot, u16 func, uint bustype, void *regsva,
5063 osl_t *osh, void *sdh)
5068 /* Init global variables at run-time, not as part of the declaration.
5069 * This is required to support init/de-init of the driver.
5071 * of globals as part of the declaration results in non-deterministic
5072 * behavior since the value of the globals may be different on the
5073 * first time that the driver is initialized vs subsequent
5076 dhd_txbound = DHD_TXBOUND;
5077 dhd_rxbound = DHD_RXBOUND;
5078 dhd_alignctl = true;
5080 dhd_readahead = true;
5083 dhd_dongle_memsize = 0;
5084 dhd_txminmax = DHD_TXMINMAX;
5090 DHD_TRACE(("%s: Enter\n", __func__));
5091 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5093 /* We make assumptions about address window mappings */
5094 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5096 /* BCMSDH passes venid and devid based on CIS parsing -- but
5098 * means early parse could fail, so here we should get either an ID
5099 * we recognize OR (-1) indicating we must request power first.
5101 /* Check the Vendor ID */
5104 case VENDOR_BROADCOM:
5107 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5111 /* Check the Device ID and make sure it's one that we support */
5113 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5114 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5115 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5116 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5118 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5119 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5120 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5122 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5124 case BCM4319_D11N_ID: /* 4319 802.11n id */
5125 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5126 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5127 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5130 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5135 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5136 __func__, venid, devid));
5141 /* Ask the OS interface part for an OSL handle */
5142 osh = dhd_osl_attach(sdh, DHD_BUS);
5144 DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5149 /* Allocate private bus interface state */
5150 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5152 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5156 bus->cl_devid = (u16) devid;
5158 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5159 bus->usebufpool = false; /* Use bufpool if allocated,
5160 else use locally malloced rxbuf */
5162 /* attempt to attach to the dongle */
5163 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5164 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5168 /* Attach to the dhd/OS/network interface */
5169 bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
5171 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5175 /* Allocate buffers */
5176 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5177 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5181 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5182 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5186 /* Register interrupt callback, but mask it (not operational yet). */
5187 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5189 bcmsdh_intr_disable(sdh);
5190 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5192 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5196 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5198 DHD_INFO(("%s: completed!!\n", __func__));
5200 /* if firmware path present try to download and bring up bus */
5201 ret = dhd_bus_start(bus->dhd);
5203 if (ret == BCME_NOTUP) {
5204 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5208 /* Ok, have the per-port tell the stack we're open for business */
5209 if (dhd_net_attach(bus->dhd, 0) != 0) {
5210 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5217 dhdsdio_release(bus, osh);
5222 dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
5228 bus->alp_only = true;
5230 /* Return the window to backplane enumeration space for core access */
5231 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5232 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5235 printf("F1 signature read @0x18000000=0x%4x\n",
5236 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5238 #endif /* DHD_DEBUG */
5240 /* Force PLL off until si_attach() programs PLL control regs */
5242 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5243 DHD_INIT_CLKCTL1, &err);
5246 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5249 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5250 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5251 "0x%02x read 0x%02x\n",
5252 err, DHD_INIT_CLKCTL1, clkctl));
5256 if (DHD_INFO_ON()) {
5258 u8 *cis[SDIOD_MAX_IOFUNCS];
5261 numfn = bcmsdh_query_iofnum(sdh);
5262 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5264 /* Make sure ALP is available before trying to read CIS */
5265 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5266 SBSDIO_FUNC1_CHIPCLKCSR,
5268 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5270 /* Now request ALP be put on the bus */
5271 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5272 DHD_INIT_CLKCTL2, &err);
5275 for (fn = 0; fn <= numfn; fn++) {
5276 cis[fn] = kmalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5278 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5282 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5284 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5285 SBSDIO_CIS_SIZE_LIMIT);
5287 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5288 "err %d\n", fn, err));
5292 dhd_dump_cis(fn, cis[fn]);
5301 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5305 #endif /* DHD_DEBUG */
5307 /* si_attach() will provide an SI handle and scan the backplane */
5308 bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5309 &bus->vars, &bus->varsz);
5311 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5315 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5317 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5318 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5319 __func__, bus->sih->chip));
5323 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5325 /* Get info on the ARM and SOCRAM cores... */
5326 if (!DHD_NOPMU(bus)) {
5327 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5328 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5329 bus->armrev = si_corerev(bus->sih);
5331 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5334 bus->orig_ramsize = si_socram_size(bus->sih);
5335 if (!(bus->orig_ramsize)) {
5336 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5340 bus->ramsize = bus->orig_ramsize;
5341 if (dhd_dongle_memsize)
5342 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5344 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5345 bus->ramsize, bus->orig_ramsize));
5348 /* ...but normally deal with the SDPCMDEV core */
5349 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5351 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5353 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5358 bus->sdpcmrev = si_corerev(bus->sih);
5360 /* Set core control so an SDIO reset does a backplane reset */
5361 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5363 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5365 /* Locate an appropriately-aligned portion of hdrbuf */
5366 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5368 /* Set the poll and/or interrupt flags */
5369 bus->intr = (bool) dhd_intr;
5370 bus->poll = (bool) dhd_poll;
5380 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
5382 DHD_TRACE(("%s: Enter\n", __func__));
5384 if (bus->dhd->maxctl) {
5386 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5387 ALIGNMENT) + DHD_SDALIGN;
5388 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5389 if (!(bus->rxbuf)) {
5390 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5391 __func__, bus->rxblen));
5396 /* Allocate buffer to receive glomed packet */
5397 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5398 if (!(bus->databuf)) {
5399 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5400 __func__, MAX_DATA_BUF));
5401 /* release rxbuf which was already located as above */
5407 /* Align the buffer */
5408 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5410 bus->databuf + (DHD_SDALIGN -
5411 ((unsigned long)bus->databuf % DHD_SDALIGN));
5413 bus->dataptr = bus->databuf;
5421 static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
5425 DHD_TRACE(("%s: Enter\n", __func__));
5428 dhdsdio_pktgen_init(bus);
5431 /* Disable F2 to clear any intermediate frame state on the dongle */
5432 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5435 bus->dhd->busstate = DHD_BUS_DOWN;
5436 bus->sleeping = false;
5437 bus->rxflow = false;
5438 bus->prev_rxlim_hit = 0;
5440 /* Done with backplane-dependent accesses, can drop clock... */
5441 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5443 /* ...and initialize clock/power states */
5444 bus->clkstate = CLK_SDONLY;
5445 bus->idletime = (s32) dhd_idletime;
5446 bus->idleclock = DHD_IDLE_ACTIVE;
5448 /* Query the SD clock speed */
5449 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5450 &bus->sd_divisor, sizeof(s32),
5451 false) != BCME_OK) {
5452 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5453 bus->sd_divisor = -1;
5455 DHD_INFO(("%s: Initial value for %s is %d\n",
5456 __func__, "sd_divisor", bus->sd_divisor));
5459 /* Query the SD bus mode */
5460 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5461 &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
5462 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5465 DHD_INFO(("%s: Initial value for %s is %d\n",
5466 __func__, "sd_mode", bus->sd_mode));
5469 /* Query the F2 block size, set roundup accordingly */
5471 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5472 &bus->blocksize, sizeof(s32), false) != BCME_OK) {
5474 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5476 DHD_INFO(("%s: Initial value for %s is %d\n",
5477 __func__, "sd_blocksize", bus->blocksize));
5479 bus->roundup = min(max_roundup, bus->blocksize);
5481 /* Query if bus module supports packet chaining,
5482 default to use if supported */
5483 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5484 &bus->sd_rxchain, sizeof(s32),
5485 false) != BCME_OK) {
5486 bus->sd_rxchain = false;
5488 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5490 (bus->sd_rxchain ? "supports" : "does not support")));
5492 bus->use_rxchain = (bool) bus->sd_rxchain;
5498 dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
5499 char *fw_path, char *nv_path)
5502 bus->fw_path = fw_path;
5503 bus->nv_path = nv_path;
5505 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5511 dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
5515 /* Download the firmware */
5516 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5518 ret = _dhdsdio_download_firmware(bus) == 0;
5520 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5525 /* Detach and free everything */
5526 static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
5528 DHD_TRACE(("%s: Enter\n", __func__));
5533 /* De-register interrupt handler */
5534 bcmsdh_intr_disable(bus->sdh);
5535 bcmsdh_intr_dereg(bus->sdh);
5539 dhdsdio_release_dongle(bus, osh);
5541 dhd_detach(bus->dhd);
5545 dhdsdio_release_malloc(bus, osh);
5551 dhd_osl_detach(osh);
5553 DHD_TRACE(("%s: Disconnected\n", __func__));
5556 static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
5558 DHD_TRACE(("%s: Enter\n", __func__));
5560 if (bus->dhd && bus->dhd->dongle_reset)
5565 bus->rxctl = bus->rxbuf = NULL;
5570 kfree(bus->databuf);
5571 bus->databuf = NULL;
5575 static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh)
5577 DHD_TRACE(("%s: Enter\n", __func__));
5579 if (bus->dhd && bus->dhd->dongle_reset)
5583 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5584 #if !defined(BCMLXSDMMC)
5585 si_watchdog(bus->sih, 4);
5586 #endif /* !defined(BCMLXSDMMC) */
5587 dhdsdio_clkctl(bus, CLK_NONE, false);
5588 si_detach(bus->sih);
5589 if (bus->vars && bus->varsz)
5594 DHD_TRACE(("%s: Disconnected\n", __func__));
5597 static void dhdsdio_disconnect(void *ptr)
5599 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5601 DHD_TRACE(("%s: Enter\n", __func__));
5605 dhdsdio_release(bus, bus->dhd->osh);
5608 DHD_TRACE(("%s: Disconnected\n", __func__));
5611 /* Register/Unregister functions are called by the main DHD entry
5612 * point (e.g. module insertion) to link with the bus driver, in
5613 * order to look for or await the device.
5616 static bcmsdh_driver_t dhd_sdio = {
5621 int dhd_bus_register(void)
5623 DHD_TRACE(("%s: Enter\n", __func__));
5625 return bcmsdh_register(&dhd_sdio);
5628 void dhd_bus_unregister(void)
5630 DHD_TRACE(("%s: Enter\n", __func__));
5632 bcmsdh_unregister();
5635 #ifdef BCMEMBEDIMAGE
5636 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5641 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5643 /* Download image */
5644 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5646 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5649 DHD_ERROR(("%s: error %d on writing %d membytes at "
5651 __func__, bcmerror, MEMBLOCK, offset));
5658 if (offset < sizeof(dlarray)) {
5659 bcmerror = dhdsdio_membytes(bus, true, offset,
5661 sizeof(dlarray) - offset);
5663 DHD_ERROR(("%s: error %d on writing %d membytes at "
5664 "0x%08x\n", __func__, bcmerror,
5665 sizeof(dlarray) - offset, offset));
5670 /* Upload and compare the downloaded code */
5672 unsigned char *ularray;
5674 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5675 /* Upload image to verify downloaded contents. */
5677 memset(ularray, 0xaa, bus->ramsize);
5678 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5680 dhdsdio_membytes(bus, false, offset,
5681 ularray + offset, MEMBLOCK);
5683 DHD_ERROR(("%s: error %d on reading %d membytes"
5685 __func__, bcmerror, MEMBLOCK, offset));
5692 if (offset < sizeof(dlarray)) {
5693 bcmerror = dhdsdio_membytes(bus, false, offset,
5695 sizeof(dlarray) - offset);
5697 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5699 sizeof(dlarray) - offset, offset));
5704 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5705 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5710 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5715 #endif /* DHD_DEBUG */
5720 #endif /* BCMEMBEDIMAGE */
5722 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5728 u8 *memblock = NULL, *memptr;
5730 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5732 image = dhd_os_open_image(fw_path);
5736 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5737 if (memblock == NULL) {
5738 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5739 __func__, MEMBLOCK));
5742 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5744 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5746 /* Download image */
5748 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5749 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5751 DHD_ERROR(("%s: error %d on writing %d membytes at "
5752 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5764 dhd_os_close_image(image);
5770 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5771 * and ending in a NUL.
5772 * Removes carriage returns, empty lines, comment lines, and converts
5774 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5778 static uint process_nvram_vars(char *varbuf, uint len)
5787 findNewline = false;
5790 for (n = 0; n < len; n++) {
5793 if (varbuf[n] == '\r')
5795 if (findNewline && varbuf[n] != '\n')
5797 findNewline = false;
5798 if (varbuf[n] == '#') {
5802 if (varbuf[n] == '\n') {
5812 buf_len = dp - varbuf;
5814 while (dp < varbuf + n)
5821 EXAMPLE: nvram_array
5824 Use carriage return at the end of each assignment,
5825 and an empty string with
5826 carriage return at the end of array.
5829 unsigned char nvram_array[] = {"name1=value1\n",
5830 "name2=value2\n", "\n"};
5831 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5833 Search "EXAMPLE: nvram_array" to see how the array is activated.
5836 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5838 bus->nvram_params = nvram_params;
5841 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5846 char *memblock = NULL;
5849 bool nvram_file_exists;
5851 nv_path = bus->nv_path;
5853 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5854 if (!nvram_file_exists && (bus->nvram_params == NULL))
5857 if (nvram_file_exists) {
5858 image = dhd_os_open_image(nv_path);
5863 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5864 if (memblock == NULL) {
5865 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5866 __func__, MEMBLOCK));
5870 /* Download variables */
5871 if (nvram_file_exists) {
5872 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5874 len = strlen(bus->nvram_params);
5875 ASSERT(len <= MEMBLOCK);
5878 memcpy(memblock, bus->nvram_params, len);
5881 if (len > 0 && len < MEMBLOCK) {
5882 bufp = (char *)memblock;
5884 len = process_nvram_vars(bufp, len);
5888 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5890 DHD_ERROR(("%s: error downloading vars: %d\n",
5891 __func__, bcmerror));
5894 DHD_ERROR(("%s: error reading nvram file: %d\n",
5896 bcmerror = BCME_SDIO_ERROR;
5904 dhd_os_close_image(image);
5909 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5913 bool embed = false; /* download embedded firmware */
5914 bool dlok = false; /* download firmware succeeded */
5916 /* Out immediately if no image to download */
5917 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5918 #ifdef BCMEMBEDIMAGE
5925 /* Keep arm in reset */
5926 if (dhdsdio_download_state(bus, true)) {
5927 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5931 /* External image takes precedence if specified */
5932 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5933 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5934 DHD_ERROR(("%s: dongle image file download failed\n",
5936 #ifdef BCMEMBEDIMAGE
5946 #ifdef BCMEMBEDIMAGE
5948 if (dhdsdio_download_code_array(bus)) {
5949 DHD_ERROR(("%s: dongle image array download failed\n",
5958 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5962 /* EXAMPLE: nvram_array */
5963 /* If a valid nvram_arry is specified as above, it can be passed
5965 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5967 /* External nvram takes precedence if specified */
5968 if (dhdsdio_download_nvram(bus)) {
5969 DHD_ERROR(("%s: dongle nvram file download failed\n",
5973 /* Take arm out of reset */
5974 if (dhdsdio_download_state(bus, false)) {
5975 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5987 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5988 u8 *buf, uint nbytes, void *pkt,
5989 bcmsdh_cmplt_fn_t complete, void *handle)
5993 /* 4329: GSPI check */
5995 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6001 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6002 u8 *buf, uint nbytes, void *pkt,
6003 bcmsdh_cmplt_fn_t complete, void *handle)
6005 return bcmsdh_send_buf
6006 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
6010 uint dhd_bus_chip(struct dhd_bus *bus)
6012 ASSERT(bus->sih != NULL);
6013 return bus->sih->chip;
6016 void *dhd_bus_pub(struct dhd_bus *bus)
6021 void *dhd_bus_txq(struct dhd_bus *bus)
6026 uint dhd_bus_hdrlen(struct dhd_bus *bus)
6028 return SDPCM_HDRLEN;
6031 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6039 if (!bus->dhd->dongle_reset) {
6040 /* Expect app to have torn down any
6041 connection before calling */
6042 /* Stop the bus, disable F2 */
6043 dhd_bus_stop(bus, false);
6045 /* Clean tx/rx buffer pointers,
6046 detach from the dongle */
6047 dhdsdio_release_dongle(bus, bus->dhd->osh);
6049 bus->dhd->dongle_reset = true;
6050 bus->dhd->up = false;
6052 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6053 /* App can now remove power from device */
6055 bcmerror = BCME_SDIO_ERROR;
6057 /* App must have restored power to device before calling */
6059 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6061 if (bus->dhd->dongle_reset) {
6063 /* Reset SD client */
6064 bcmsdh_reset(bus->sdh);
6066 /* Attempt to re-attach & download */
6067 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6068 (u32 *) SI_ENUM_BASE,
6070 /* Attempt to download binary to the dongle */
6071 if (dhdsdio_probe_init
6072 (bus, bus->dhd->osh, bus->sdh)
6073 && dhdsdio_download_firmware(bus,
6077 /* Re-init bus, enable F2 transfer */
6078 dhd_bus_init((dhd_pub_t *) bus->dhd,
6081 #if defined(OOB_INTR_ONLY)
6082 dhd_enable_oob_intr(bus, true);
6083 #endif /* defined(OOB_INTR_ONLY) */
6085 bus->dhd->dongle_reset = false;
6086 bus->dhd->up = true;
6088 DHD_TRACE(("%s: WLAN ON DONE\n",
6091 bcmerror = BCME_SDIO_ERROR;
6093 bcmerror = BCME_SDIO_ERROR;
6095 bcmerror = BCME_NOTDOWN;
6096 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6097 "is on\n", __func__));
6098 bcmerror = BCME_SDIO_ERROR;
projects / mv-sheeva.git / blob